Prosecution Insights
Last updated: August 16, 2026
Application No. 18/345,270

STACKED LED CHIPS

Non-Final OA §102§103
Filed
Jun 30, 2023
Examiner
AHMAD, KHAJA
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
766 granted / 946 resolved
+13.0% vs TC avg
Strong +26% interview lift
Without
With
+26.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
38 currently pending
Career history
992
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 04/29/2026. Currently, claims 1-2, 4-10 and 14-23 are pending in the application. Claims 4, 8-10 and 14-20 have been withdrawn and claims 3 and 11-13 have been cancelled. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LI et al (US 20200403026 A1). Regarding claim 1, Figure 1-2 of LI disclose a light-emitting diode (LED) device, comprising: a first LED chip (red LED at 210, [0112]), wherein the first LED chip, comprises: a first anode connection (P-electrode for red LED, [0073]) and a first cathode connection (256, [0120]); a second LED chip (green LED at 220, [0088]) mounted to the first LED chip, the second LED chip comprising: a second anode connection (P-electrode for red green LED, [0073]) and a second cathode connection (258, [0120]); a third LED chip (blue LED at 230, [0096]) mounted to the first LED chip, the third LED chip comprising: a third anode connection (P-electrode for blue LED, [0073]) and a third cathode connection (260, [0120]); wherein the second anode connection and the second cathode connection of the second LED chip are connected to the third anode connection and the third cathode connection of the third LED chip in a string (since anode or p-electrodes of three color are connected together and cathode or n-electrodes are connected to common ground, [0068]). Regarding claim 2, Figure 1-2 of LI disclose that the LED device of claim 1, wherein: the first LED chip (red LED at 210, [0112]) defines a first surface; the second LED chip (green LED at 220, [0088]) defines a second surface; and the second surface of the second LED chip is mounted on the first surface of the first LED chip (red LED at 210, [0112]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 21-23 are rejected under 35 U.S.C. 103 as being obvious over Chin et al (US 20070018189 A1) in view of Oraw (US 20150357315 A1). Regarding claim 1, Figure 7/8 of Chin disclose a light-emitting diode (LED) device, comprising: a first LED chip (30, [0023]), wherein the first LED chip, comprises: a first anode connection and a first cathode connection (anode and cathode connections are not explicitly recited or leveled but a LED inherently has an anode and a cathode electrode that needs connectivity and the connections are at the bottom side of 30 as shown in Figure 7); a second LED chip (40, [0021]) mounted to the first LED chip, the second LED chip comprising: a second anode connection (considering the left wire 60 connected with 40, [0021]) and a second cathode connection (considering the right wire 60 connected with 40); and a third LED chip (50) mounted to the first LED chip, the third LED chip comprising: a third anode connection (considering the left wire 60 connected with 50, [0021]) and a third cathode connection (considering the right wire 60 connected with 50). Chin does not explicitly teach wherein the second anode connection and the second cathode connection of the second LED chip (40) are connected to the third anode connection and the third cathode connection of the third LED chip (50) in a string. However, Oraw is a pertinent art which teaches a plurality of overlapping, transparent light emitting diode (LED) layers and, in particular, wherein Oraw teaches a single light sheet may be formed by multiple areas of LEDs tiled on a single substrate, where each separate area of LEDs comprises LEDs electrically connected in parallel and series by the various conductor layers. As an example, one strip of LEDs may be electrically isolated from an adjacent strip as a result of the pattern used during the screen printing of the LEDs and conductor layers. In this way, the separate strips may be connected together in series and/or parallel, or isolated, by metal patterns on the light sheet to achieve the desired electrical characteristics of the light sheet. Dividing the LEDs into areas also reduces the required current for each conductor layer and improves reliability in the event of a short or open circuit. By enabling driving the strips with different voltages, different types of LEDs (having different forward voltages) may be used in adjacent strips to combine the different colors from the strips. In one embodiment, red, green, and blue LEDs are in adjacent narrow strips to create white light without a phosphor ([0074] and [0081]). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the LED device of Chin such that wherein the second anode connection and the second cathode connection of the second LED chip are connected to the third anode connection and the third cathode connection of the third LED chip in a string according to the teaching of Oraw in order to connect different LED in parallel to the desired electrical characteristics and improves reliability in the event of a short or open circuit (Oraw, [0074]). Regarding claim 2, Figure 7/8 of Chin disclose that the LED device of claim 1, wherein: the first LED chip (30) defines a first surface; the second LED chip (40) defines a second surface; and the second surface of the second LED chip is mounted on the first surface of the first LED chip (30). Regarding claims 21-23, Figure 7/8 of Chin does not explicitly teach that the LED device of claim 1, wherein: the first anode connection of the first LED chip is configured to receive a first voltage; the second anode connection of the second LED chip is configured to receive a second voltage that is different from the first voltage; the third anode connection of the third LED chip is connected to the first anode connection of the first LED chip; the second cathode connection is connected to the third cathode connection. Or The LED device of claim 1, wherein the first anode connection of the first LED chip and the first cathode connection of the first LED chip is isolated from the second anode connection of the second LED chip, the second cathode connection of the second LED chip, the third anode connection of the third LED chip, and the third cathode connection of the third LED chip. Or The LED device of claim 1, wherein: the first anode connection of the first LED chip is configured to receive a first voltage; the second anode connection of the second LED chip is configured to receive a second voltage that is different from the first voltage; the third anode connection of the third LED chip is configured to receive a third voltage that is different from the first voltage and the second voltage; the second cathode connection is connected to the third cathode connection. However, Oraw is a pertinent art which teaches a plurality of overlapping, transparent light emitting diode (LED) layers and, in particular, wherein Oraw teaches a single light sheet may be formed by multiple areas of LEDs tiled on a single substrate, where each separate area of LEDs comprises LEDs electrically connected in parallel and series by the various conductor layers. As an example, one strip of LEDs may be electrically isolated from an adjacent strip as a result of the pattern used during the screen printing of the LEDs and conductor layers. In this way, the separate strips may be connected together in series and/or parallel, or isolated, by metal patterns on the light sheet to achieve the desired electrical characteristics of the light sheet. Dividing the LEDs into areas also reduces the required current for each conductor layer and improves reliability in the event of a short or open circuit. By enabling driving the strips with different voltages, different types of LEDs (having different forward voltages) may be used in adjacent strips to combine the different colors from the strips. In one embodiment, red, green, and blue LEDs are in adjacent narrow strips to create white light without a phosphor ([0074] and [0081]). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the LED device of Chin as claimed above according to the teaching of Oraw in order to connect different LED in parallel or series to the desired electrical characteristics and improves reliability in the event of a short or open circuit (Oraw, [0074]). Claims 5-7 are rejected under 35 U.S.C. 103 as being obvious over Chin et al (US 20070018189 A1) in view of Oraw (US 20150357315 A1) as applied to claim 1, and further in view of Chen et al (US 20100109028 A1). Regarding claims 5-6, Figure 7/8 of Chin does not explicitly teach that the LED device of claim 1, wherein: the first LED chip (30), comprises: a first growth substrate; and a first active LED region mounted on the first growth substrate; the second LED chip (40), comprises: a second growth substrate; and a second active LED region mounted on the second growth substrate; and the second growth substrate is mounted on the first growth substrate, wherein: the third LED chip (50), comprises: a third growth substrate; and a third active LED region mounted on the third growth substrate; and the third growth substrate is mounted on the first growth substrate. However, Chen is a pertinent art which teaches a vertical stack of LED device, wherein Figure 1 of Chen teaches that the first light emitting diodes A contains a first substrate 111 (Figure 1), a first n-type semiconductor layer 110, a first light emitting layer 109, and a first p-type semiconductor layer 108 formed on the first substrate 111, and the second light emitting diodes B contains a second substrate 113, a second n-type semiconductor layer 114, a second light emitting layer 115 and a second p-type semiconductor layer 116 formed on the second substrate 113 ([0020] and [0022]). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the first to third LEDs in the device of Chin in combination with Oraw the first LED chip (30), comprises: a first growth substrate; and a first active LED region mounted on the first growth substrate; the second LED chip (40), comprises: a second growth substrate; and a second active LED region mounted on the second growth substrate; and the second growth substrate is mounted on the first growth substrate, wherein: the third LED chip (50), comprises: a third growth substrate; and a third active LED region mounted on the third growth substrate; and the third growth substrate is mounted on the first growth substrate according to the teaching of Chen in order to improve light efficiency, operation life and the brightness ([0005] of Chen). Regarding claim 7, Figure 7/8 of Chin in view of Oraw teach that the LED device of claim 5, wherein: the first anode connection and the first cathode connection are arranged such that the first LED chip (30, Figure 7 of Chin) has a flip-chip configuration; and the second anode connection and the second cathode connection are arranged such that the second LED chip has a lateral configuration (Figures 7/8 of Chin). Response to Arguments Applicant’s arguments/amendments regarding the rejection of claims 1-2, 5-7 and 21-23, filed on 04/29/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jun 30, 2023
Application Filed
Dec 12, 2025
Non-Final Rejection (signed) — §102, §103
Feb 13, 2026
Non-Final Rejection mailed — §102, §103
Apr 29, 2026
Response Filed
Jun 12, 2026
Final Rejection mailed — §102, §103
Jul 10, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+26.0%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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