DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Arguments, filed 02/12/2026, with respect to the drawing objections and the rejections of claims under 35 USC 102 and 103 have been fully considered and are persuasive, the US 20220109046 A1 Hong does not teach the amended limitations. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20230207553 A1 Xie et al and US 20240421156 A1 Xie et al
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13 and 16-25 are rejected under 35 U.S.C. 103 as being obvious over US 20220109046 A1 Hong et al hereafter “Hong” and in further view of US 20230207553 A1 Xie et al hereafter “Xie 2021” and US 20240421156 A1 Xie et al hereafter “Xie 2023”.
Claim 1 Hong teaches an integrated circuit device (300 fig. 3A-3E), comprising:
a first semiconductor layer (310 fig. 3A-3E, best illustrated fig. 3A) and a second semiconductor layer (320 fig. 3A-3E, best illustrated fig. 3A ) above the first semiconductor layer [sufficiently illustrated fig. 3A-3E], wherein the first and second semiconductor layers are vertically spaced apart from each other [sufficiently illustrated fig. 3A-3E];
a first source/drain epitaxial structure (312 and 311 fig. 3A-3E, best illustrated fig. 3A) on a side (D2+ side fig. 3A-3E, best illustrated fig. 3A)of the first semiconductor layer [sufficiently illustrated fig. 3A-3E];
a second source/drain epitaxial structure (314 and 313 fig. 3A-3E, best illustrated fig. 3A) on a side (D2+ side fig. 3A-3E, best illustrated fig. 3A) of the second semiconductor layer and above the first source/drain epitaxial structure [sufficiently illustrated fig. 3A-3E], wherein the first source/drain epitaxial structure has a portion non-overlapping the second source/drain epitaxial structure from a top view [sufficiently illustrated fig. 3A-3E best illustrated fig. 3D see annotation below];
a first contact plug (322 and/or 332 fig. 3A-3E, best illustrated fig. 3) over a backside (D3+ side fig. 3A-3E, backside met under broadest interpretation wherein the D3+ side is viewed as the back of the device) of the first source/drain epitaxial structure, wherein the first contact plug overlaps the portion of the first source/drain epitaxial structure from the top view [sufficiently illustrated fig. 3A] wherein the first contact plug interfaces a back-side metal (340 best illustrated fig. 3ED); and
a second contact plug (323 best illustrated fig. 3E) below a backside of the second source/drain epitaxial structure [D3+ side fig. 3E], wherein the second contact plug interfaces the backside metal at a second level height.
Hong does not teach the first contact plug interfaces a front-side metal at a first level height; the second level height lower than the first level height.
Xie 2021 teaches a device comprising front-side and back-side metals (170 and 190 fig. 1A) interfacing to front-side and back-side contact plugs (160/161 and 181/182 fig. 1A).
It would have been obvious to one of ordinary skill in the art to combine the device of Hong with the device of Xie 2021 such that Hong includes both “a front-side metal” and “a back-side metal” to necessarily enable the device to be powered and/or facilitate processing from both the front side and the back side [sufficiently disclosed Xie paragraph 0049 “a full backside power delivery structure” and Paragraph 0097 “the BEOL interconnect structure 170 to facilitate backside processing”].
Xie 2023 teaches a semiconductor device wherein in a first cross-section (1220 fig. 12B) wherein upper and lower sources/drains (1222 fig. 12B) are addressed by source/drain contact plugs (1224 and 1226 fig. 12B) from the frontside of the device;
a second cross-section (1240 fig. 12C) wherein upper and lower sources/drains (1242 fig. 12C) are addressed by source/drain contact plugs (1244 and 1246 fig. 12C) from the backside of the device;
a third cross-section (1260 fig. 12D) wherein upper and lower sources/drains (1262 fig. 12D) are addressed by source/drain contact plugs (1224 and 1226 fig. 12D) from the frontside and backside of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first contact plug of Hong in view of Xie 2021 and 2023 such that “the first contact plug interfaces the front-side metal at a first level height”.
A person of ordinary skill in the art would have been motivated to make this modification to effectively address and/or power the first source/drain epitaxial structure from the front-side of the device, as taught by Xie 2023
Modify the routing of contact plugs to interface with front-side versus back-side metals constitutes a rearrangement of parts that does not change the principle of operation of the device [see MPEP 2144.04 VI C]. Furthermore, utilizing front-side contacts and back-side contacts to power source/drain regions are art-recognized equivalents for powering semiconductor devices [See MPEP 2144.06]
In view of the modification made above the limitation “the second level height lower than the first level height” is met as the front-side metal layer is above the back-side metal layer when viewed from top to bottom.
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Annotated fig. 3E: highlighting the portion
Claim 2 Hong in view of Xie 2021 and Xie 2023 teaches as shown above the integrated circuit device of claim 1, wherein the first source/drain epitaxial structure and the second source/drain epitaxial structure are of opposite conductive types [Sufficiently disclosed paragraph 0063, “source/drain region 312 functions as a drain of the transistor 301 (NMOS), and the 4.sup.th source/drain region 314 functions as a drain of the transistor 302 (PMOS)” wherein NMOS and PMOS refer to the conductivities of “N-Type” and “P-Type” further disclosed paragraph 0041].
Claim 3 Hong in view of Xie 2021 and Xie 2023 as shown above teaches the integrated circuit device of claim 1, wherein a width of the first source/drain (W3 fig. 3E) epitaxial structure is greater than a width of the second source/drain epitaxial structure (W4 fig. 3E) [sufficiently illustrated fig. 3E].
Claim 4 Hong in view of Xie 2021 and Xie 2023 as shown above teaches the integrated circuit device of claim 1, wherein a center of the first source/drain epitaxial structure (center of W3 fig. 3E) is laterally offset from a center of the second source/drain epitaxial structure (center of W4 fig. 3E) [sufficiently illustrated fig. 3E].
Claim 5 Hong in view of Xie 2021 and Xie 2023 as shown above teaches the integrated circuit device of claim 1, further comprising:
a first interlayer dielectric layer (illustrated fig. 3D, see annotated below, disclosed as dielectric in paragraph 0037 “It is understood in advance that some elements shown in the drawings without reference numbers or characters are those included in conventional semiconductor devices and well known in the field. For example, dielectric layers are provided in corresponding positions of the semiconductor devices to insulate neighboring elements”) surrounding the second source/drain epitaxial structure, wherein the first contact plug extends in the first interlayer dielectric layer downward to the portion of the first source/drain epitaxial structure [illustrated fig. 3D].
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Annotated fig. 3E: highlighting a first dielectric layer
Claim 6 Hong in view of Xie 2021 and Xie 2023 as shown above teaches the integrated circuit device of claim 5, wherein the first contact plug is spaced apart from the second source/drain epitaxial structure by the first interlayer dielectric layer [sufficiently illustrated fig. 3A-E].
Claim 8 Hong in Xie 2021 and Xie 2023 teaches as shown above the integrated circuit device of claim 1, further comprising:
a second interlayer dielectric layer (see annotation below, illustrated fig. 3A-3E, best illustrated fig. 3E in conjunction with the disclosure of Paragraph 0037 “It is understood in advance that some elements shown in the drawings without reference numbers or characters are those included in conventional semiconductor devices and well known in the field. For example, dielectric layers are provided in corresponding positions of the semiconductor devices to insulate neighboring elements”) surrounding the first source/drain epitaxial structure, wherein the second contact plug extends in the second interlayer dielectric layer upward to the portion of the second source/drain epitaxial structure [necessarily met by the second interlayer dielectric of Hong in view of Xie and the rearrangement of parts, fig. 12B Xie 2023].
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Annotated fig. 3E: highlighting the first interlayer dielectric layer and the second interlayer dielectric layer
Claim 9 Hong in view of Xie 2021 and Xie 2023 as shown above teaches the integrated circuit device of claim 8, wherein the second contact plug is spaced apart from the first source/drain epitaxial structure by the second interlayer dielectric layer [met in view of Xie 2023 fig. 12B].
Claim 10 Hong teaches an integrated circuit device (300 fig. 3A-3E), comprising:
a first transistor (301 fig. 3A-3E, illustrated not labeled but disclosed) comprising a first semiconductor layer (310 fig. 3A-3E best illustrated fig. 3A), a first gate structure surrounding the first semiconductor layer (315 fig. 3A-3E best illustrated fig. 3A), and a first source/drain epitaxial structure (311 and 312 fig. 3A-3E, best illustrated fig. 3A) on a side (D2+ side fig. 3A-3E, best illustrated fig. 3A) of the first semiconductor layer;
a second transistor (302 fig. 3A-3E, illustrated not labeled but disclosed) stacked over the first transistor [sufficiently illustrated fig. 3A] , wherein the second transistor comprises a second semiconductor layer (320 fig. 3A-3E, best illustrated fig. 3A) above the first semiconductor layer, a second gate structure (325 fig. 3A-3E, best illustrated fig. 3A) surrounding the second semiconductor layer, and a second source/drain epitaxial structure (314 and 313 fig. 3A-3E, best illustrated fig. 3A) on a side of the second semiconductor layer (D2+ fig. 3A-3E), wherein from a top view, the second source/drain epitaxial structure overlaps the first source/drain epitaxial structure [sufficiently illustrated fig. 3A-3E, best illustrated fig. 3E], and a center of the second source/drain epitaxial structure (center of W4 fig. 3E) is laterally offset from a center of the first source/drain epitaxial structure (center of W3 fig. 3E) [sufficiently illustrated fig. 3A-3E, best illustrated fig. 3E].
a first contact plug (322 fig. 3D) below and overlapping a backside of the first source/drain epitaxial structure (D3+ side fig. 3A-E, under broadest reasonable interpretation wherein D3+ side is the bottom of the device), wherein the first contact plug interfaces a back-side metal (340 fig. 3A-E); and
a second contact plug (323 fig. 3E) below and overlapping the backside of the second source/drain epitaxial structure, wherein the second contact plug interfaces the backside metal at a second level height [sufficiently illustrated fig. 3A-3E best illustrated fig. 3E].
Hong does not teach the first contact plug above a front side of the first source/drain epitaxial structure and interfaces a front-side metal at a first level height; the second level height lower than the first level height.
Xie 2021 teaches a device comprising front-side and back-side metals (170 and 190 fig. 1A) interfacing to front-side and back-side contact plugs (160/161 and 181/182 fig. 1A).
It would have been obvious to one of ordinary skill in the art to combine the device of Hong with the device of Xie 2021 such that Hong includes both “a front-side metal” and “a back-side metal” to necessarily enable the device to be powered and/or facilitate processing from both the front side and the back side [sufficiently disclosed Xie paragraph 0049 “a full backside power delivery structure” and Paragraph 0097 “the BEOL interconnect structure 170 to facilitate backside processing”].
Xie 2023 teaches a semiconductor device wherein in a first cross-section (1220 fig. 12B) wherein upper and lower sources/drains (1222 fig. 12B) are addressed by source/drain contact plugs (1224 and 1226 fig. 12B) from the frontside of the device;
a second cross-section (1240 fig. 12C) wherein upper and lower sources/drains (1242 fig. 12C) are addressed by source/drain contact plugs (1244 and 1246 fig. 12C) from the backside of the device;
a third cross-section (1260 fig. 12D) wherein upper and lower sources/drains (1262 fig. 12D) are addressed by source/drain contact plugs (1224 and 1226 fig. 12D) from the frontside and backside of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first contact plug of Hong in view of Xie 2021 and 2023 such that “the first contact plug interfaces the front-side metal at a first level height”.
A person of ordinary skill in the art would have been motivated to make this modification to effectively address and/or power the first source/drain epitaxial structure from the front-side of the device, as taught by Xie 2023
Modify the routing of contact plugs to interface with front-side versus back-side metals constitutes a rearrangement of parts that does not change the principle of operation of the device [see MPEP 2144.04 VI C]. Furthermore, utilizing front-side contacts and back-side contacts to power source/drain regions are art-recognized equivalents for powering semiconductor devices [See MPEP 2144.06]
In view of the modification made above the limitation “the second level height lower than the first level height” is met as the front-side metal layer is above the back-side metal layer when viewed from top to bottom.
In view of the modification made above the limitation “the second level height lower than the first level height” is met as the front-side metal layer is above the back-side metal layer when viewed from top to bottom.
Claim 11 Hong in view of Xie 2021 and Xie 2023 teaches as shown above the integrated circuit device of claim 10, wherein the second source/drain epitaxial structure is electrically isolated from the first source/drain epitaxial structure [best illustrated fig. 3E in conjunction with the disclosure of paragraph 0037 “It is understood in advance that some elements shown in the drawings without reference numbers or characters are those included in conventional semiconductor devices and well known in the field. For example, dielectric layers are provided in corresponding positions of the semiconductor devices to insulate neighboring elements”].
Claim 16 Hong teaches a method, comprising:
forming a first transistor (301 fig. 3A-3E, disclosed but not labeled) over a substrate (305 fig. 3A-3E, best illustrated fig. 3A), wherein the first transistor comprises a first semiconductor layer (310 fig. 3A-3E, best illustrated fig. 3A), a first gate structure (315 fig. 3A-3E, best illustrated fig. 3A) over the first semiconductor layer, and a first source/drain epitaxial structure (311 and 312 fig. 3A-3E, best illustrated fig. 3A) on a side of the first semiconductor layer (D2+ fig. 3A-3E best illustrated fig. 3A);
forming a first interlayer dielectric layer (see annotation below, illustrated fig. 3A-3E, best illustrated fig. 3E in conjunction with the disclosure of Paragraph 0037 “It is understood in advance that some elements shown in the drawings without reference numbers or characters are those included in conventional semiconductor devices and well known in the field. For example, dielectric layers are provided in corresponding positions of the semiconductor devices to insulate neighboring elements”) around the first transistor;
stacking a second semiconductor layer (320 fig. 3A-3E, best illustrated fig. 3A) over the first semiconductor layer;
forming a second gate structure (325 fig. 3A-3E, best illustrated fig. 3A) over the second semiconductor layer; and
epitaxially growing a second source/drain epitaxial structure (313 and 314 fig. 3A-3E, best illustrated fig. 3A, disclosed Paragraph 0058 “source/drain region 314 may be formed by epitaxially growing silicon layers”) on a side of the second semiconductor layer (D2+ fig. 3A-3E best illustrated fig. 3A), wherein from a top view, the second source/drain epitaxial structure overlaps the first source/drain epitaxial structure [sufficiently illustrated fig. 3A-3E], and a center of the second source/drain epitaxial structure (center of W4 fig. 3E) is laterally offset from a center of the first source/drain epitaxial structure (center of W3 fig. 3E) [sufficiently illustrated fig. 3A-3E];
forming a second interlayer dielectric layer (see annotation below, illustrated fig. 3A-3E, best illustrated fig. 3E in conjunction with the disclosure of Paragraph 0037 “It is understood in advance that some elements shown in the drawings without reference numbers or characters are those included in conventional semiconductor devices and well known in the field. For example, dielectric layers are provided in corresponding positions of the semiconductor devices to insulate neighboring elements”) around the second source/drain epitaxial structure
forming a first contact plug (322 and 332 fig. 3D) below and overlapping a backside of the first source/drain epitaxial structure (D3+ side fig. 3A-E, under broadest reasonable interpretation wherein the D3+ side is the back and bottom of the device); and
forming a second contact plug (323 fig. 3E) below and overlapping a backside of the second source/drain epitaxial structure (D3+ side fig. 3A-E).
Hong does not teach the first contact plug above and overlapping a frontside of the first source/drain epitaxial structure nor after the first contact plug is formed, forming the second contact plug.
Xie 2023 teaches a semiconductor device wherein in a first cross-section (1220 fig. 12B) wherein upper and lower sources/drains (1222 fig. 12B) are addressed by source/drain contact plugs (1224 and 1226 fig. 12B) from the frontside of the device;
a second cross-section (1240 fig. 12C) wherein upper and lower sources/drains (1242 fig. 12C) are addressed by source/drain contact plugs (1244 and 1246 fig. 12C) from the backside of the device;
a third cross-section (1260 fig. 12D) wherein upper and lower sources/drains (1262 fig. 12D) are addressed by source/drain contact plugs (1224 and 1226 fig. 12D) from the frontside and backside of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first contact plug of Hong in view of Xie 2021 and 2023 such that “the first contact plug above and overlapping a frontside of the first source/drain epitaxial”.
A person of ordinary skill in the art would have been motivated to make this modification to effectively address and/or power the first source/drain epitaxial structure from the front-side of the device, as taught by Xie 2023
Modify the routing of contact plugs to interface with front-side versus back-side metals constitutes a rearrangement of parts that does not change the principle of operation of the device [see MPEP 2144.04 VI C]. Furthermore, utilizing front-side contacts and back-side contacts to power source/drain regions are art-recognized equivalents for powering semiconductor devices [See MPEP 2144.06]
In view of the modification made above the limitation “the second level height lower than the first level height” is met as the front-side metal layer is above the back-side metal layer when viewed from top to bottom.
Xie 2021 teaches forming a first contact plug (160 and/or 161 fig. 7) on a front side (the side of 170 fig. 7); after forming the first contact plug, forming a second contact plug (181 and/or 182 fig. 8) on a back side (190 fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hong in view of Xie 2023 in further view of Xie 2023 such that “after forming the first contact plug, forming a second contact plug” occurs to flip the device and access the back side and enable the deposition process [sufficiently illustrated fig. 8 to fig. 9].
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Annotated fig. 3E: highlighting the first interlayer dielectric layer and the second interlayer dielectric layer
Claim 17 Hong in view of Xie 2023 and Xie 2021 as shown above teaches the method of claim 16, further comprising:
, wherein the first contact plug extends though the first and second interlayer dielectric layers (sufficiently illustrated in fig. 3A-3E, and met under broadest reasonable interpretation).
Claim 18 Hong in view of Xie 2023 and Xie 2021 as shown above teaches the method of claim 16, further comprising:
, wherein the second contact plug extends though the first and second interlayer dielectric layers [sufficiently illustrated fig. 3D, still met when modified in view of Xie 2023 and Xie 2021].
Claim 19 Hong teaches as shown above the method of claim 16, wherein stacking the second semiconductor layer over the first semiconductor layer comprises:
forming a first dielectric layer (330 fig. 3A-3E) over the first transistor;
forming a second dielectric layer (343 fig. 3A-3E) over the second semiconductor layer; and
bonding the first dielectric layer to the second dielectric layer [sufficiently illustrated as being bonded together fig. 3B under broadest reasonable interpretation].
Claim 20 Hong teaches as shown above the method of claim 16, wherein epitaxially growing the second source/drain epitaxial structure is performed such that a width of the second source/drain epitaxial structure [W4 fig. 3E and/or 3D] is different from a width of the first source/drain epitaxial structure [W3 fig. 3E and/or 3D] [sufficiently illustrated fig. 3A-3E].
Claim 21 Hong in view of Xie 2021 and Xie 2023 teach as shown above the integrated circuit device of claim 1, wherein the first contact plug has a bottom end at a third level height higher than the second level height [met in view of the combination and/or rearrangement of parts as shown above fig. 3D illustrates that the top (D3- side) of the first contact plug 322 does not extend to the front side (D3- side), when combined Xie 2021 and Xie 2023 when view topside up (D3- side and/or the side with 305) the bottom of the such that it extend from the front side the bottom would not extend to the second level height and/or the top of the back-side metal].
Claim 22 Hong in view of Xie 2021 and Xie 2023 as shown above the integrated circuit device of claim 1, wherein the second contact plug has a top end at a fourth level height lower than the first level height [sufficiently illustrated fig. 3E in view of Xie 2021 and Xie 2023 when viewed top-side up, the top side of 323 (D3- side) is lower than 305 where the front-side metal and the first level height would be when modified].
Claim 23 Hong in view of Xie 2021 and Xie 2023 as shown above the integrated circuit device of claim 1, wherein a vertical distance from the first level height to the second level height is greater than a total thickness of the first source/drain epitaxial structure and the second source/drain epitaxial structure [met in view of Xie 2021 and Xie 2023 see annotation below, note 305 represents wherein the front-side metal layer would be].
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Annotated fig. 3E: highlight a vertical distance when modified and total thickness
Claim 24 Hong in view of Xie 2021 and 2023 as shown above the integrated circuit device of claim 1, wherein the first source/drain epitaxial structure and the second source/drain epitaxial structure are vertically between the front-side metal and the backside metal [necessarily met in view of Xie 2021 and Xie 2023 ].
Claim 25 Hong in view of Xie 2023 and Xie 2021 as shown above the method of claim 16, a bottom end at a level different from both the top and bottom ends of the second contact plug [met in view of the modification Xie 2023 and Xie 2021, illustrated fig. 3A-E neither the top or bottom of 323 extends to 305, when modified the bottom of 322 would extend from at least 305 ].
Hong in view of Xie 2023 and Xie 2021 does not explicitly teach the first contact plug has a top end at a level different than both top and bottom ends of the second contact plug.
It would be obvious to one of ordinary skill in the art to modify Hong in view of Xie 2023 and Xie 2021 such that “a top end at a level different than both top and bottom ends of the second contact plug”.
A person of ordinary skill in the art would have been motivated to make this modification to effectively address and/or power the first source/drain epitaxial structure from the front-side of the device, as taught by Xie 2023.
Modify the routing of contact plugs to interface with the device at such that the top and bottom surfaces are at different height levels constitutes a rearrangement of parts that does not change the principle of operation of the device [see MPEP 2144.04 VI C]. Furthermore, change the size of the contact plugs such that the top and bottom surfaces are at different heigh levels constitutes a relative change size that does not change the principle of operation of the device [See MPEP 2144.04 IV A.]
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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