Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16, lines 6 and 9: states “a dielectric layer”. It is not clear whether the second “a dielectric layer” is introducing a second dielectric or is referring to the first “dielectric layer”.
For purpose of examination, claim 16, lines 8-9 will be treated as: “the at least one VSS pad and the at least one VDD pad at least partially embedded in a dielectric layer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (US 2018/0145030 A1) in view of Yeh et al. (US 2022/0285338 A1).
Regarding independent claim 1: Beyne teaches (e.g., Figs. 3A-9) an integrated circuit device comprising:
a plurality of transistors ([0051]: transistors) located on a first side of a substrate ([0046]: upper surface of substrate 6);
a plurality of buried power rails ([0058]: 8 and 9) connected to the plurality of transistors,
the plurality of buried power rails comprising a plurality of VSS power rails and a plurality of VDD power rails ([0058]-[0059]: the power rails are capable of being used as VDD or VSS);
at least one VSS pad and at least one VDD pad ([0058]-[0059]: 46 and 47);
a first plurality of vias ([0058]: 16 and 17) electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails ([0058]-[0059]: 46 and 47),
wherein the at least one VSS pad is located on a second side of the substrate ([0058]-[0059]: pad 46 or 47 pad is located on a second side/bottom side of the substrate) opposite of the first side;
a second plurality of vias ([0058]: 66 and 67) electrically connecting the at least one VDD pad (46 and 47) to at least two of the plurality of buried VDD power rails ([0058]-[0059]: 46 and 47),
wherein the at least one VDD pad is located on a second side of the substrate opposite of the first side ([0058]-[0059]: VDD pad is located on a second side/backside of the substrate opposite of the first side).
Beyne does not expressly teach
a bonding surface comprising the at least one VDD pad, the at least one VSS pad, and
a dielectric surface of a dielectric layer in which the at least one VDD pad and the at least one VSS pad are at least partially embedded,
the bonding surface configured for hybrid bonding.
Yeh teaches (e.g., Fig. 1) an integrated circuit comprising:
a bonding surface (shown in Fig. 1 at the lower surface in dotted lines) comprising the at least one VDD pad (Fig. 1; [0019]: 109), the at least one VSS pad (Fig. 1; [0019]: 109), and
a dielectric surface of a dielectric layer ([0012]-[0013], [0016]-[0018] and [0028]: layer 103 similar to layer 113 is a dielectric layer) in which the at least one VDD pad (Fig. 1; [0016] and [0019]: 109 and last element 111) and the at least one VSS pad (Fig. 1; [0016] and [0019]: 109 and last element 111) are at least partially embedded, the bonding surface configured for hybrid bonding ([0012], [0016], [0019] and [0028]).
Applicant is reminded that a "product claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product claim" and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not; MPEP § 2113.
Regarding claim 2: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein at least one VSS pad comprises a plurality of VSS pads (Yeh: Fig. 1; [0019]: 109) and the at least one VDD pad comprises a plurality of VDD pads (Yeh: Fig. 1; [0019]: 109), wherein the plurality of VSS pads and the plurality of VDD pads (Yeh: Fig. 1; [0019]: 109) are provided on the second side of the substrate (Yeh: back side of the substrate) corresponding to the plurality VSS and VDD pads on the backside of the substrate (Beyne: Fig. 7; [0058]-[0059]).
Regarding claim 3: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein the at least one VSS pad and the at least one VDD pad are configured for hybrid bonding (Beyne: Fig. 7; [0058]-[0059]: the at least one VSS and the at least one VDD pads are capable of being used for hybrid bonding) corresponds to (Yeh: Fig. 1; [0019]: 109).
Regarding claim 4: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein the plurality of VSS power rails or the plurality of VDD power rails provide power to the plurality of transistors (Fig. 7; [0058]-[0059]: the plurality of buried VSS power rails or the plurality of VDD buried power rails, inherently, provide power to the plurality of transistors).
Regarding claim 5: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein the plurality of buried power rails are located in a front end of the line (FEOL) (Fig. 7; [0058]-[0059]).
Regarding claim 6: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein the at least one VSS pad and/or the at least one VDD pad has a length to width ratio in the range of 1:1 to 10:1 (Fig. 7; [0058]-[0059]: at least one VSS pad and/or the at least one VDD pad (47 and 46) has a length to width ratio in the range of 1:1 to 10:1 from the proportion of the length and the width).
Regarding claim 7 Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends,
wherein the plurality of transistors comprise fin field effect transistors (FinFETs) or gate all around field effect transistors (GAA) ([0054]: FinFET).
Regarding claim 9: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends.
Although, Beyne does not expressly teach that at least one VSS pad and the at least one VDD pad are located 100 nm to 3 microns below the plurality of buried power rails, the wide range does not prove to be critically, since all the elements are known, one of ordinary skill in the art could choose a suitable range based on the device size and device constraints.
Applicant's disclosure does not teach why the range as claimed is critical to the invention when juxtaposed with the one in the prior art.
In view of the absence of a teaching why a range is critical to the invention, Applicant is reminded that it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10: Beyne teaches the claim limitation of the integrated circuit device of claim 8, on which this claim depends.
Although, Beyne does not expressly teach that the ground or reference plane is located 100 nm to 3 microns below the plurality of buried power rails, the wide range does not prove to be critically, since all the elements are known, one of ordinary skill in the art could choose a suitable range based on the device size and device constraints.
Applicant's disclosure does not teach why the range as claimed is critical to the invention when juxtaposed with the one in the prior art.
In view of the absence of a teaching why a range is critical to the invention, Applicant is reminded that it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (US 2018/0145030 A1) in view of Yu et al. (US 2021/0407942 A1).
Regarding independent claim 16: Beyne teaches (e.g., Figs. 3A-9) an integrated circuit device comprising:
a plurality of transistors ([0051]: transistors) located on a first side of a substrate ([0046]: upper surface of substrate 6);
a plurality of buried power rails ([0058]: 8 and 9) connected to the plurality of transistors,
the plurality of buried power rails comprising a plurality of VSS power rails and a plurality of VDD power rails ([0058]-[0059]: the power rails are capable of being used as VDD or VSS);
at least one VSS pad and at least one VDD pad located on a second side of the substrate ([0058]-[0059]: pad 46 or 47 pad is located on a second side/bottom side of the substrate) opposite of the first side; and.
a power distribution network element ([0058]: PDN 12) hybrid bonded to a hybrid bonding surface including the at least one VSS pad and the at least one VDD pad ([0058]-[0059]; Applicant is reminded that a "product" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. MPEP 2113),
Beyne does not expressly teach
a dielectric, the at least one VSS pad and the at least one VDD pad at least partially embedded in the dielectric layer,
a power distribution network element on a second substrate, the power distribution network element hybrid bonded to a hybrid bonding surface including the at least one VSS;
wherein the at least one VSS pad and the at least one VDD pad are directly bonded to and contact conductive features of the power distribution network element without an intervening adhesive, and
wherein the dielectric layer is directly bonded to and contacts a nonconductive bonding layer of the power distribution network element.
Yu teaches (E.G., Figs. 1-19B) an integrated circuit device comprising at least one VSS pad and the at least one VDD pad ([0052]: 136 and 136 respectively) and a power distribution network element ([0048]: 100B);
Yu further teaches a dielectric ([0052]: 138/134), the at least one VSS pad and the at least one VDD pad at least partially embedded in the dielectric layer (138/134),
a power distribution network element on a second substrate ([00364]: 72),
the power distribution network element (100B) hybrid bonded to a hybrid bonding surface including the at least one VSS ([0052]: 136).
wherein the at least one VSS pad and the at least one VDD pad ([0052]: 136 and 136 respectively) are directly bonded to and contact conductive features ([0047]: 112/114) of the power distribution network element (100B) without an intervening adhesive, and
wherein the dielectric layer is directly bonded to and contacts a nonconductive bonding layer ([0052]: 138) of the power distribution network element (100B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the integrated circuit device of Beyne, the at least one VSS pad and the at least one VDD pad at least partially embedded in the dielectric layer, a power distribution network element on a second substrate, the power distribution network element hybrid bonded to a hybrid bonding surface including the at least one VSS; wherein the at least one VSS pad and the at least one VDD pad are directly bonded to and contact conductive features of the power distribution network element without an intervening adhesive, and wherein the dielectric layer is directly bonded to and contacts a nonconductive bonding layer of the power distribution network element, as taught by Yu, for the benefits of increasing the device density with a small footprint, and powering all the devices and managing power to all devices effectively with minimal wiring length.
Regarding claim 17: Beyne and Yu teach the claim limitation of the integrated circuit device of claim 16, on which this claim depends, further comprising:
Beyne as modified by Yu teaches a first plurality of vias (Beyne: [0058]: 66 and 67) electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails (Beyne: [0058]-[0059]); and
a second plurality of second vias electrically (Beyne: [0058]: 16 and 17) connecting the at least one VDD pad to at least two of the plurality of VDD power rails.
Claims 8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (US 2018/0145030 A1) in view of Yeh et al. (US 2022/0285338 A1) as applied above and further in view of (Yu et al. US 2021/0407942 A1).
Regarding claim 8: Beyne teaches the claim limitation of the integrated circuit device of claim 1, on which this claim depends.
Beyne does not expressly teach that the device further comprises a ground or reference plane located below the plurality of buried power rails.
Yu teaches (e.g., Figs. 1-19B) an integrated circuit device comprising at least one VSS pad and the at least one VDD pad ([0052]: 136 and 136 respectively) and a buried power rail ([0040]-[0041] and [0048]: 70);
Yu further teaches that the integrated circuit device further comprises a ground or reference plane ([0047]-[0048]: 118) located below the plurality of buried power rails.
Regarding claim 14: Beyne, Yeh and Yu teach the claim limitation of the integrated circuit device of claim 8, on which this claim depends.
Beyne as modified by Yeh and Yu teaches that the ground or reference plane is located directly on the at least one VSS pad (Yu: [0047]-[0048]: 118).
Regarding claim 15: Beyne, Yeh and Yu teach the claim limitation of the integrated circuit device of claim 8, on which this claim depends.
Beyne as modified by Yeh and Yu teaches that the ground or reference plane (Yu: [0047]-[0048]: 118) is electrically connected to the at least one VSS pad with vias (Yu: [0049]-[0050]: 125).
Allowable Subject Matter
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, an integrated circuit device comprising:
“wherein at least one of a length, width, and thickness of the at least one VSS pad is different from a length, width, and thickness of the at least one VDD pad”.
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, an integrated circuit device comprising:
“wherein the first plurality of vias comprises VSS vias and VDD vias and all of the VSS vias are shorted to the ground or reference plane”.
Regarding claim 13: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, an integrated circuit device comprising:
“wherein the ground or reference plane comprises openings allowing the VDD second plurality of vias to pass through the ground or reference plane without being shorted to the ground or reference plane”.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference or combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or of newly introduced limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812