DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Claims 1-15, in the reply filed on 11/24/2025 is acknowledged.
Response to Amendment
Applicant’s amendments filed 11/24/2025 have been entered. Claims 16-20 have been cancelled. Claims 1-15 and 21-25 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 10-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20220165731 A1) hereinafter “Huang”.
Regarding Claim 1, Figures 1-41C of Huang teach: A method (Paragraph 0020) comprising: forming a fin structure (112; Figure 2) over a substrate (101), wherein the fin structure comprises a first sacrificial layer (108b), a first channel layer (106b), a second sacrificial layer (108a), and a second channel layer (106a) arranged in a stacking direction (up/down vertically); forming a dummy gate structure (130; Figure 13A) across the fin structure; forming gate spacers (138) on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers (146; Figure 18A) on opposite sides of the first channel layer and spaced apart from the second channel layer (Figure 18A); forming second source/drain epitaxial layers (149) on opposite sides of the second channel layer and spaced apart from the first source/drain epitaxial layers (Figure 18A); removing the dummy gate structure (Figure 21A; Paragraph 0056), the first sacrificial layer (Figure 22A), and the second sacrificial layer (Figure 22A) to form a gate trench (166) defined by the gate spacers; forming an oxynitride layer (148; Figure 24; Paragraph 0062) in the gate trench to surround the first channel layer; forming a dipole layer (150/154; Figure 25 and 28) comprising dipole dopants (Paragraphs 0063 and 0068) in the gate trench to surround the oxynitride layer; performing an anneal process (131; Figure 30; Paragraph 0075) to drive the dipole dopants (Paragraphs 0073-0074) into the oxynitride layer; and after performing the anneal process, sequentially depositing a high-k gate dielectric layer (160; Figure 32) and a work function metal layer (172; Paragraph 0090) in the gate trench to form a gate structure (combination of 160, 172, and 179).
Regarding Claim 3, Figures 1-41C of Huang teach: a thickness of the oxynitride layer (148) is less than about 50 Angstrom (Paragraph 0062; 0.5 nm to about 2 nm is equal to 5-20 Angstrom.
Regarding Claim 10, Figures 1-41C of Huang teach: A method comprising: forming a bottom transistor (155) over a substrate (101); forming a fin structure (112) over the bottom transistor, wherein the fin structure comprises a sacrificial layer (108a) and a channel layer (106a) over the sacrificial layer; forming a dummy gate structure (130) across the fin structure; forming source/drain epitaxial layers (149) on opposite sides of the channel layer and over the bottom transistor; removing the dummy gate structure (Figure 21A; Paragraph 0056) and the sacrificial layer (Figure 22A); forming a nitrogen-containing interfacial layer (148; Paragraph 0062) to surround the channel layer; depositing a dipole layer (150/154) to surround the nitrogen-containing interfacial layer; performing an anneal process (131) to drive dipole dopants (Paragraph 0073-0074) into the nitrogen-containing interfacial layer; and forming a high-k gate dielectric layer (160) and a work function metal layer (172; Paragraph 0090) to surround the nitrogen-containing interfacial layer to form a gate structure (combination of 160, 172, and 179).
Regarding Claim 11, Figures 1-41C of Huang teach: the nitrogen-containing interfacial layer (148) is in contact with the channel layer (106a).
Regarding Claim 13, Figures 1-41C of Huang teach: after forming the gate structure (combination of 160, 172, and 179), the dipole layer (150/154) is in contact with the nitrogen-containing interfacial layer (148) and the high-k gate dielectric layer (160).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Furusawa et al. (US 20080230847 A1) hereinafter “Furusawa.”
Regarding Claim 2, Huang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: an amount of nitrogen atoms in the oxynitride layer is less than an amount of oxygen atoms in the oxynitride layer.
Figure 8 of Furusawa teaches: a semiconductor device (Figure 8) with an insulating film (14) comprising silicon oxyniride (Paragraph 0074), wherein an amount of nitrogen atoms (Paragraph 0074; y= 0.2 or less) in the oxynitride layer is less than an amount of oxygen atoms (Paragraph 0074; x=1.5 or more) in the oxynitride layer
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an amount of nitrogen atoms in the oxynitride layer is less than an amount of oxygen atoms in the oxynitride layer because Furusawa teaches a composition ratio that suppresses an increase of the dielectric constant of the insulating film, which reduces parasitic capacitance (Furusawa Paragraph 0074).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Chen et al. (US 20220181494 A1) hereinafter “Chen.”
Regarding Claim 4, Huang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: removing an oxide layer in contact with the first channel layer to expose the first channel layer prior to forming the oxynitride layer.
Figures 21-24 of Chen teach: a semiconductor fin (215) wherein a cleaning process is performed (Paragraph 0065) on a native oxide that naturally grows (Paragraph 0038) on exposed surfaces of the semiconductor fin
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove an oxide layer in contact with the first channel layer to expose the first channel layer prior to forming the oxynitride layer because a cleaning process is performed to ensure good quality of gate stacks in transistors (Chen Paragraph 0038).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Bao et al. (US 20240429277 A1) hereinafter “Bao”.
Regarding Claim 8, Huang teaches all of the limitations of the claimed invention as stated above.
Huang further teaches: the fin structure (112) further comprises a third sacrificial layer (108c) between the first channel layer (106b) and the second sacrificial layer (108a)
Huang does not teach: replacing the third sacrificial layer with a dielectric isolator between the first channel layer and the second channel layer.
Figure 3A of Bao teaches: a stacked finFET transistor (Paragraph 0038) with first channel layers (14) and upper channel layers (20) and a dielectric isolator (16) between the first channel layers and the second channel layers
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the third sacrificial layer with a dielectric isolator between the first channel layer and the second channel layer because Bao teaches the middle dielectric isolation layer electrically separates each stacked pair of devices from each other (Bao Paragraph 0028).
Regarding Claim 9, the combination of Huang and Bao teach all of the limitations of the claimed invention as stated above.
Huang does not teach: the oxynitride layer exposes a surface of the dielectric isolator.
However, when the middle dielectric isolator of Bao in combined with the structure of Huang, a structure will be yielded such that the oxynitride layer exposes a surface of the dielectric isolator, specifically the left/right horizontal surfaces of the dielectric layer.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Chang et al. (US 20190165185 A1) hereinafter “Chang.”
Regarding Claim 14, Huang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: forming the nitrogen-containing interfacial layer comprises: forming an oxide layer to surround the channel layer; and providing nitrogen-containing plasma to the oxide layer to form the nitrogen-containing interfacial layer.
Figure 10 of Chang teaches: a semiconductor device (10) comprising forming an interfacial layer (52) of silicon oxide (Paragraph 0023) over a channel region (32) and performing a nitridation treatment containing nitrogen-containing plasma (Paragraph 0027) to the interfacial layer to form a silicon oxynitride interfacial layer.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that forming the nitrogen-containing interfacial layer comprises: forming an oxide layer to surround the channel layer; and providing nitrogen-containing plasma to the oxide layer to form the nitrogen-containing interfacial layer because Chang teaches the nitridation of the interfacial layer prevents out-diffusion of underlying layers (Chang Paragraph 0027).
Regarding Claim 15, Huang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: the nitrogen-containing interfacial layer is formed at a temperature lower than about 800 °C.
Figure 10 of Chang teaches: a nitrogen-containing interfacial layer (52c) is formed at about a temperature of 300° C to 500° C.
It would be obvious to one of ordinary skill in the art to have the nitrogen-containing interfacial layer is formed at a temperature lower than about 800 °C because Chang teaches a nitridation treatment formed at about a temperature of 300° C to 500° C results in sufficient nitridation of the interfacial layer (Chang Paragraph 0027).
Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, less than about 800 °C, overlaps the range of Chang, 300° C to 500° C.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Bao et al. (US 20230170352 A1) hereinafter Bao2023.
Regarding Claim 12, Huang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: forming an insulator layer over the bottom transistor prior to form the fin structure, wherein the nitrogen-containing interfacial layer is spaced apart from the insulator layer.
Figures 3A-3D of Bao2023 teach: a stacked semiconductor structure (360; Figure 3C; Paragraph 0057) wherein an insulator layer (316) is formed over a bottom transistor (S1) prior to forming the fin structure (S2; Figure 3C)
It would be obvious to one of ordinary skill before the effective filing date of the claimed invention to have forming an insulator layer over the bottom transistor prior to form the fin structure because Bao2023 teaches multiple methods of forming a stacked CMOS, including the formation of a bottom transistor and a separating dielectric layer, before the formation of a top transistor (Bao2023 Paragraph 0048).
Claims 21-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220165731 A1) hereinafter “Huang” in view of Chen et al. (US 20220181494 A1) hereinafter “Chen” and Chang et al. (US 20190165185 A1) hereinafter “Chang.”
Regarding Claim 21, Figures 1-41C of Huang teach: A method (Paragraph 0020) comprising: forming a semiconductor structure (112; Figure 2) over a substrate (101), wherein the semiconductor structure comprises a sacrificial layer (108b) over the substrate and a channel layer (106b) over the sacrificial layer; forming a dummy gate structure (130; Figure 13A) across the semiconductor structure; forming gate spacers (138) to laterally surround the dummy gate structure; forming source/drain structures 146; Figure 18A) on opposite sides of the dummy gate structure and connected to the channel layer; removing the dummy gate structure (Figure 21A; Paragraph 0056) and the sacrificial layer (Figure 22A) to form a gate trench (166) surrounded by the gate spacers; depositing an interfacial layer (148) to surround the channel layer; depositing a high-k gate dielectric layer (160) in the gate trench to cover the interfacial layer comprising nitrogen (Paragraph 0062); and depositing a work function metal material (172) in the gate trench and covering the high-k gate dielectric layer (Paragraph 0090).
Huang does not teach: removing an oxide layer surrounding the channel layer to expose the channel layer;
Figures 21-24 of Chen teach: a semiconductor fin (215) wherein a cleaning process is performed (Paragraph 0065) on a native oxide that naturally grows (Paragraph 0038) on exposed surfaces of the semiconductor fin
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove an oxide layer surrounding the channel layer to expose the channel layer because a cleaning process is performed to ensure good quality of gate stacks in transistors (Chen Paragraph 0038).
Huang does not teach: after depositing the interfacial layer, introducing nitrogen-containing plasma into the gate trench to introduce nitrogen into the interfacial layer
Figure 10 of Chang teaches: a semiconductor device (10) comprising forming an interfacial layer (52) of silicon oxide (Paragraph 0023) over a channel region (32) and performing a nitridation treatment containing nitrogen-containing plasma (Paragraph 0027) to the interfacial layer to form a silicon oxynitride interfacial layer.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that forming the nitrogen-containing interfacial layer comprises after depositing a silicon oxide interfacial layer, introducing nitrogen-containing plasma into the gate trench to introduce nitrogen into the interfacial layer because Chang teaches the nitridation of a silicon oxide interfacial layer creating a silicon oxynitride prevents out-diffusion of underlying layers (Chang Paragraph 0027).
Regarding Claim 22, the combination of Huang, Chen, and Chang teaches all of the limitations of the claimed invention as stated above.
Huang does not teach: wherein introducing nitrogen-containing plasma is performed at a temperature lower than about 800 °C.
Figure 10 of Chang teaches: a nitrogen-containing interfacial layer (52c) is formed at about a temperature of 300° C to 500° C.
It would be obvious to one of ordinary skill in the art to have the nitrogen-containing interfacial layer is formed at a temperature lower than about 800 °C because Chang teaches a nitridation treatment formed at about a temperature of 300° C to 500° C results in sufficient nitridation of the interfacial layer (Chang Paragraph 0027).
Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, less than about 800 °C, overlaps the range of Chang, 300° C to 500° C.
Regarding Claim 25, the combination of Huang, Chen, and Chang teaches all of the limitations of the claimed invention as stated above.
Figures 1-41C of Huang further teach: forming a transistor (153) over the work function metal material (172 of item 155).
Allowable Subject Matter
Claims 5-7 and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have a thickness of the oxynitride layer is less than a thickness of the oxide layer along with all of the limitations of Claims 4 and 1.
Regarding Claim 6, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the oxide layer comprises dangling bonds along with all of the limitations of Claim 1. Claim 7 is also objected to as it depends from and includes all of the limitations of Claim 6.
Regarding Claim 23, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have a thickness of the interfacial layer comprising the nitrogen is less than a thickness of the oxide layer along with all of the limitations of Claim 21.
Regarding Claim 24, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the interfacial layer comprises oxygen and at least one dangling bond prior to introducing nitrogen-containing plasma into the gate trench along with all of the limitations of Claim 21.
Conclusion
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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