DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 03/12/2026. Claims 1 and 9 are amended, and claims 11-20 remain withdrawn.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tain et al (US 20090294947 A1, hereafter Tain).
Regarding claim 1, Tain, in at least one embodiment, discloses: An electronic package (Tain 500, ¶0021, 0027, 0048, 0053), comprising:
a packaging layer (Tain 102, 110, 500, fig 1D, 5, ¶0024);
a first electronic element (Tain 104, ¶0021, 0007, 0033) embedded in the packaging layer (Tain ¶0024, 0027, fig 1D, 5, at least within 110), wherein a heat dissipation body (Tain 106, ¶0023) is disposed on an active surface (Tain 104a, ¶0021, 0027) of the first electronic element (Tain fig 1D, 5, ¶0023, 0027);
a second electronic element (Tain middle 104, fig 5) embedded in the packaging layer (Tain ¶0021, 0024, fig 1D, 5) and spaced apart from the first electronic element (Tain fig 5); and
a circuit structure (Tain 107, 108a, 112, 114, 116, 134, 136, ¶0021, 0028) disposed on the packaging layer (Tain fig 1D, 5) and electrically connected to the first electronic element and the second electronic element (Tain fig 1D, 5, ¶0021, at least 114 and 116 are directly electrically connected to 104), wherein the circuit structure has a heat dissipation portion (Tain 112, ¶0027, 0031, 0048, at least capable thereof) thermally connected to the first electronic element via the heat dissipation body (Tain fig 1D, 5, ¶0027, “106 is connected to the thermal conductive vias 112”, “106 contacts the active surface 104a of the chip 104”).
Regarding claim 2, Tain discloses: The electronic package of claim 1, wherein the circuit structure (Tain 107, 108a, 112, 114, 116, 134, 136) includes an insulating layer (Tain 107), a circuit layer (Tain 108a, 116, ¶0028) formed on the insulating layer (Tain fig 1D, ¶0028), and a plurality of conductive blind vias (Tain 108a, 116) formed in the insulating layer and electrically connected to the circuit layer and the first electronic element (Tain 106)(Tain fig 1D, 5, ¶0027, 0048, at least via 114).
Regarding claim 3, Tain discloses: The electronic package of claim 1, wherein the heat dissipation portion (Tain 112) includes a plurality of heat dissipation pillars stacked on each other (Tain fig 5).
Regarding claim 4, Chen teaches: The electronic package of claim 1, wherein the heat dissipation portion (Tain 112) is a single heat dissipation pillar (Tain fig 1D, ¶0028).
Regarding claim 5, Tain discloses: The electronic package of claim 1, wherein the heat dissipation portion (Tain 112) further comprises at least one heat dissipation pillar and at least one heat dissipation layer thermally connected to the heat dissipation pillar (Tain fig 1D, 5, ¶0048, 0053-0054, 106 is between vertically adjacent 112s).
Regarding claim 7, Tain discloses: The electronic package of claim 1, wherein the circuit structure (Tain 107, 108a, 112, 114, 116, 134, 136) is penetrated through by the heat dissipation portion (Tain 112)(Tain fig 1D, 5).
Regarding claim 8, Tain discloses: The electronic package of claim 1, wherein the circuit structure (Tain 107, 108a, 112, 114, 116, 134, 136) is free from being penetrated through by the heat dissipation portion (Tain 112)(Tain fig 1D,5, 112 does not penetrate other features comprising the circuit structure).
Regarding claim 9, Tain discloses: The electronic package of claim 1, wherein the heat dissipation body (Tain 106) is located at a position corresponding to the heat dissipation portion (Tain 112)(Tain fig 1D, 5, ¶0023).
Regarding claim 10, Tain discloses: The electronic package of claim 9, wherein the heat dissipation body (Tain 106) is a heat sink (Tain ¶0023, fig 1D, at least functions to dissipate heat from 104, therefore meets a broadest reasonable interpretation of a “heat sink”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Tain et al (US 20090294947 A1, hereafter Tain), as applied to claim 1 above, and further in view of Nomoto et al (US 20050199995 A1, hereafter Nomoto).
Regarding claim 6, Tain teaches: The electronic package of claim 1.
Tain does not explicitly teach: wherein the circuit structure has a ground wire connected to the heat dissipation portion.
Nomoto, in the same field of endeavor of semiconductor device manufacturing, teaches: a ground wire (Nomoto 45, ¶0179, under a broadest reasonable interpretation of a “wire”) connected to a heat dissipation portion (Nomoto 37, 27, 9, ¶0173- 0179, “serves as an electrode … for ground”)(Nomoto fig 1-3, ¶0175, 0179).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the circuit structure of Tain to include a ground wire connected to the heat dissipation portion, as taught by Nomoto, in order to enable a single conductive structure to provide both thermal dissipation and electrical grounding functions (Nomoto ¶0175), thereby reducing the number of separate conductive paths required in the package.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yu et al (US 20130056871 A1), Hsieh et al (US 20240055385 A1) and Choi et al (US 20200144192 A1) are cited as examples of an analogous device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818
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