Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
This correspondence is in response to the communications received on 04/16/2026. Claims 8, 21, 27, 29 and 31 have been amended, new claim 32 has been added and claims 1-7, 9 are canceled. Claims 8, 10-16, 21-32 are pending.
Response to Arguments
Applicant’s arguments and amendments, see pages 9-10, filed 04/16/2026, with respect to claims 8, 10-16, 21-26, 32 have been fully considered and are persuasive. The previous rejection of claims 8, 10-16, 21-26 and 32 has been withdrawn.
Applicant’s arguments with respect to claim(s) 27-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 27-29, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20190157421 A1; hereinafter “Wang”) in view of Li et al. (US 20180012890 A1; hereinafter “Li”).
In re claim 27, Wang discloses in figs. 1-10, a method comprising:
forming a gate dielectric layer 120/120a on a substrate over a plurality of doped regions 144b (fig. 1; ¶16-17);
forming a gate structure G2 on the gate dielectric layer 120 (¶16-17),
wherein a first portion of the gate dielectric layer (e.g., a middle portion of 120) is under the gate structure G2 and between the gate structure G2 and the substrate 110 (fig. 6), and
wherein a second portion and a third portion of the gate dielectric layer (e.g., the thinned portions, 120a in fig. 6) extend laterally outward past the gate structure G2 and are left uncovered by the gate structure G2 (fig. 6); and
performing an implantation operation to form a plurality of source/drain regions 166 in the substrate 110 (fig. 7; ¶23).
Wang does not expressly disclose wherein the gate dielectric layer is used as an implantation mask, and wherein implantation of ions into the substrate is blocked in locations of the substrate covered by the gate dielectric layer, causing the plurality of source/drain regions to be formed on sides of the gate dielectric layer without extending under the gate dielectric layer.
In the same field of endeavor, Li discloses in figs. 1-10, a method comprising:
performing an implantation operation to form a plurality of source/drain regions 318, 318 in the substrate 306 (fig. 8; ¶63);
wherein the gate dielectric layer 312 is used as an implantation mask, and
wherein implantation of ions into the substrate 306 is blocked in locations of the substrate covered by the gate dielectric layer 312, causing the plurality of source/drain regions 318, 318 to be formed on sides of the gate dielectric layer 312 without extending under the gate dielectric layer 312.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Li into the method of Wang and perform the ion implantation operation utilizing the gate dielectric layer as an implantation mask as Li teaches the source and drain ion implantation can be directly performed after the formation of the polysilicon gate without introducing a single processing step to grind the residual oxide layer in the high-voltage device region, thereby simplifying the processing step and reducing the processing cost (¶24 of Li).
In re claim 28, Wang, as modified by Li, method of claim 27 outlined above.
Wang further discloses in figs. 1-10, wherein the second portion of the gate dielectric layer 120a extends laterally outward past a first end of the gate structure (e.g., left end of G2),
wherein the third portion of the gate dielectric layer 120a extends laterally outward past a second end of the gate structure (e.g., right end of G2), and wherein the first end is opposite to the second end.
In re claim 29, Wang, as modified by Li, method of claim 27 outlined above.
Wang further discloses in figs. 1-10, wherein a first source/drain region of the plurality of source/drain regions 166 is formed in a first doped region of the plurality of doped regions 144b (¶17, 23), and
wherein a second source/drain region of the plurality of source/drain regions 166 is formed in a second doped region of the plurality of doped regions 144b (¶17, 23).
In re claim 31, Wang, as modified by Li, method of claim 27 outlined above.
Wang further discloses in figs. 1-10, further comprising depositing an inter-layer dielectric (ILD) layer 170 over the gate structure G2 and the gate dielectric layer 120 (fig. 10; ¶27),
wherein a portion of the ILD layer 170 is formed on and in contact with top surfaces of the second portion 120a and the third portion 120a of the gate dielectric layer.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Li, as applied to claim 27 above and further in view of Cheng et al. (US 20230335641 A1; hereinafter “Cheng”).
In re claim 30, Wang, as modified by Li, method of claim 27 outlined above.
Wang does not expressly disclose wherein the second portion and the third portion of the gate dielectric layer each have a width included a range of approximately 0.014 microns to approximately 0.05 microns.
In the same field of endeavor, Li discloses a method of forming high voltage MOS transistor (figs. 1-10) wherein a width of an edge portion of a gate dielectric layer 312 which extends from a gate structure 314 is in a range of approximately 0.05 microns to 0.5 microns (“wherein the width of the second gate oxide layer is 0.2 to 1 micrometers greater than the width of the second polysilicon gate”; see claim 2 of Li), which overlap the claimed range of approximately 0.014 microns to approximately 0.05 microns.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Li into the method of Wang and extend the gate oxide layer from the edge of the gate structure by a threshold distance as claimed value of approximately 0.014 microns to approximately 0.05 microns.
One would have been motivated to do so as Cheng teaches under the same drain voltage Vd, Ioff corresponding to a drain current Id decreases as the threshold distance increases and this improves GIDL problem (¶120 of Cheng).
Allowable Subject Matter
Claims 8, 10-16, 21-32 are allowed over prior art of record.
Prior art of record Wang et al. (US 20190157421 A1), Lee et al. (US 7067365 B1), Li et al. (US 20180012890 A1), Tsai et al. (US 20220376071 A1) have been found to be closest prior art of record.
Regarding Claim 8: None of the prior art of record, alone or in combination, discloses combination of the method steps cited in claim 8, for example, forming an oxide layer over the first doped region and over the second doped region; forming, over the oxide layer, a gate structure of a high voltage transistor structure of the semiconductor device; performing an etch operation to remove material from the oxide layer to form a gate oxide layer of the high voltage transistor structure, in combination with wherein forming the plurality of source/drain regions comprises doping the substrate using the gate oxide layer as a self-aligned implantation mask, and wherein implantation of ions into the substrate is blocked in locations of the substrate covered by the gate oxide layer, causing the plurality of source/drain regions to be formed on sides of the gate oxide layer without extending under the gate oxide layer.
The above cited prior art teaches some steps individually. However, it would not have been obvious to combine the steps from different prior art to arrive at the claimed invention.
Regarding Claim 21: None of the prior art of record, alone or in combination, discloses combination of the method steps cited in claim 21, for example, depositing an oxide layer on a substrate over a well region and over a plurality of lightly doped regions adjacent to the well region; depositing, over the oxide layer, a gate structure of a high voltage transistor structure of a semiconductor device; etching the oxide layer to form a gate oxide layer of the high voltage transistor structure, wherein the gate oxide layer is used as a self-aligned implantation mask during the ion implantation operation, and wherein implantation of ions into the lightly doped regions is blocked in locations of the lightly doped regions covered by the gate oxide layer, causing the plurality of source/drain regions to be formed on sides of the gate oxide layer without extending under the gate oxide layer.
Claims 10-16, 21-26, 32 are allowable based on their dependency on claims 1 and 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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