Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
Examiner acknowledges the preliminary amendments to the Specification, Abstract and Drawings submitted by the Applicant on 10/27/2023. The IDS filed on 02/20/2024 has been considered by the Examiner.
Election/Restrictions
Applicant’s election without traverse of Group II, reading on claims 8-16 in the reply filed on 11/06/2025 is acknowledged. New claims 21-31 have been added and Examiner acknowledges they read on the elected invention as well.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 27-29 and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 20220376071 A1; hereinafter “Tsai”).
In re claim 27, Tsai discloses a method (figs. 3-11), comprising:
forming a gate dielectric layer 22 on a substrate 10 over a plurality of doped regions 12, 12 (figs. 3-5; ¶31-32);
forming a gate structure 30A on the gate dielectric layer 22 (fig. 6; ¶32),
wherein a first portion of the gate dielectric layer 22B is under the gate structure 30A and between the gate structure 30A and the substrate 10 (¶30), and
wherein a second portion 22A and a third portion 22A of the gate dielectric layer extend laterally outward past the gate structure 30A and are left uncovered by the gate structure 30A (¶30); and
performing an implantation operation 90 to form a plurality of source/drain regions 42B, 42B in the substrate 10 (fig. 8; ¶36),
wherein the gate dielectric layer 22 is used as an implantation mask (¶36).
In re claim 28, Tsai discloses in fig. 8, the method of claim 27, wherein the second portion of the gate dielectric layer (left edge portion 22A) extends laterally outward past a first end of the gate structure 30A, wherein the third portion of the gate dielectric layer (right edge portion 22A) extends laterally outward past a second end of the gate structure 30A, and wherein the first end is opposite to the second end.
In re claim 29, Tsai discloses in fig. 8, the method of claim 27, wherein a first source/drain region 42B of the plurality of source/drain regions is formed in a first doped region 12 of plurality of doped regions, and wherein a second source/drain region 42B of the plurality of source/drain regions is formed in a second doped region 12 of plurality of doped regions.
In re claim 31, Tsai discloses in figs. 9-10, the method of claim 27, further comprising depositing an inter-layer dielectric (ILD) layer 62, 64 over the gate structure 30A and the gate dielectric layer 22, wherein a portion of the ILD layer 62, 64 is formed on and in contact with top surfaces of the second portion 22A and the third portion 22A of the gate dielectric (the etch stop layer 62 and the dielectric layer 64 are formed over the gate structure 30A and the gate dielectric layer 22 and thereafter planarized through CMP, as described in ¶38. Therefore, Tsai’s method step discloses depositing an inter-layer dielectric (ILD) layer 62, 64 over the gate structure 30A before the CMP step).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10, 12, 14-15, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20220376071 A1; hereinafter “Tsai”) in view of Wang et al. (US 20190157421 A1; hereinafter “Wang”) and Oh et al. (US 20220336502 A1; hereinafter “Oh”).
In re claim 8, Tsai discloses a method (figs. 3-11), comprising:
forming a substrate 10 (¶27);
doping the substrate 10 with a second dopant type to form a second doped region 12 of the semiconductor device adjacent to the first doped region 10 (fig. 3; the lightly doped source/drain region 12 may be an n-type or p-type lightly doped region; ¶20, 31);
forming an oxide layer 20 over the substrate region 10 and over the second doped region 12 (fig. 3; ¶31);
performing an etch operation to remove material from the oxide layer 20 to form a gate oxide layer 22 of the high voltage transistor structure T1 (figs. 4-6; ¶31),
forming, over the gate oxide layer 22, a gate structure 30A of a high voltage transistor T1 structure of the semiconductor device (fig. 6; ¶32, 25; the operating voltage of the first transistor structure T1 may be higher than that of the second transistor structure T2, the first region R1 may be regarded as a relatively high voltage transistor region, and the second region R2 may be regarded as a relatively low voltage transistor region);
wherein the etch operation results in a portion of the gate oxide layer 22 extending laterally outward from the gate structure 30A; and
forming a plurality of source/drain regions 42B, 42B of the high voltage transistor structure T1 using the gate oxide layer 22 as a self-aligned pattern (fig. 8; ¶36. Tsai discloses the shape of the first source/drain doped region 42 may be mainly influenced by the edge portion 22A of the first gate oxide layer 22 and have the first portion 42A and the second portion 42B described above because the first gate oxide layer 22 is relatively thicker and the first spacer structure S1 does not cover the edge portion 22A. As can be seen in fig. 8, the deeper portions of the source/drain doped regions 42B are formed aligned with an edge of the gate oxide layer 22. Therefore, the plurality of source/drain regions 42B, 42B of the high voltage transistor structure T1 are formed by using the gate oxide layer 22 as a self-aligned pattern).
Tsai discloses depositing the gate structure 30A over the gate oxide layer 22. In other words, Tsai discloses depositing the gate structure after the oxide layer 20 has been etched.
However, Tsai does not expressly disclose depositing the gate structure 30A prior to performing the etch operation to remove the oxide material to form the gate oxide layer.
In the same field of endeavor, Wang discloses a method (figs. 1-10) comprising:
depositing a gate structure G2 (fig. 1; ¶17) prior to performing the etch operation to remove the oxide material 120 to form the gate oxide layer 120a (fig. 6; ¶21-22; “The gate dielectric layer 120 of the second area B is also etched and thus is thinned to become a gate dielectric layer 120a”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Wang and form the gate spacer prior to etching the oxide layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Tsai discloses the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other suitable semiconductor materials (¶27). However, Tsai does not expressly disclose doping the substrate 10 with a first dopant type to form a first doped region of a semiconductor device.
In the same field of endeavor, Oh discloses a method of forming a high voltage transistor (figs. 9A-9I), comprising:
doping a substrate 200 with a first dopant type (e.g., n-type) to form a first doped region 220 of a semiconductor device (¶91-92).
Oh discloses the doped second high voltage deep well HDNW 220 electrically isolates the second high voltage semiconductor element 20 from the substrate, thereby advantageously assisting in determining an operational voltage (¶92).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dope the substrate 10 of Tsai with a first dopant type to form a first doped region of a semiconductor device as taught by Oh to electrically isolate the second high voltage semiconductor element from the substrate, thereby advantageously assisting in determining an operational voltage (¶92 of Oh).
In re claim 9, Tsai, as modified by Wang and Oh, discloses the method of claim 8 outlined above.
Tsai further discloses wherein forming the plurality of source/drain regions comprises: doping the substrate 10 using the gate oxide layer 22 as a self-aligned implantation mask (fig. 8; ¶36).
In re claim 10, Tsai, as modified by Wang and Oh, discloses the method of claim 8 outlined above.
Tsai further discloses wherein performing the etch operation to remove the material from the oxide layer comprises:
performing the etch operation such that gate oxide layer 20 extends laterally outward from the gate structure 30A by a distance DS1 that satisfies a threshold distance (fig. 11, ¶40; the required distance DS1 between the first metal silicide layer 52 and the first gate structure GS1 may still exist for achieving the purpose of reducing the leakage current of the first transistor structure T1).
In re claim 12, Tsai, as modified by Wang and Oh, discloses the method of claim 10 outlined above.
Tsai further discloses in figs. 3-11, wherein the threshold distance DS1 is based on at least one of: a gate-to-drain spacing parameter for the high voltage transistor structure T1 (the required distance DS1 between the first metal silicide layer 52 and the first gate structure GS1 may still exist for achieving the purpose of reducing the leakage current of the first transistor structure T1; ¶40), a drain voltage of the high voltage transistor structure, or a gate voltage of the high voltage transistor structure.
In re claim 14, Tsai, as modified by Wang and Oh, discloses the method of claim 8 outlined above.
Tsai further discloses the method further comprising: performing a single sidewall spacer formation process to form a sidewall spacer S11 on a sidewall of the gate structure 30A (fig. 6 shows forming a sidewall spacer S11) after performing the etch operation on the oxide layer 20 (fig. 4 shows etching the oxide layer 20; ¶31). Moreover, Tsai indicates an edge portion of the gate oxide layer 22 is etched by the steps of forming the gate spacer S11 (fig. 6; ¶33) .
However, Tsai does not expressly disclose the sidewall spacer was formed prior to performing the etch operation to remove the oxide material.
In the same field of endeavor, Wang discloses a method (figs. 1-10) comprising: performing a single sidewall spacer formation process (e.g., forming spacer 142b in fig. 1; ¶17) to form a sidewall spacer 142b on a sidewall of a gate structure G2 prior to performing an etch operation to remove material from the oxide layer 120 to form a gate oxide layer 120a (fig. 6; ¶21-22; “The gate dielectric layer 120 of the second area B is also etched and thus is thinned to become a gate dielectric layer 120a”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Wang and form the gate spacer prior to etching the oxide layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
In re claim 15, Tsai, as modified by Wang and Oh, discloses the method of claim 14 outlined above.
Tsai further discloses in figs. 1-11, wherein the etch operation results in the portion of the gate oxide layer (e.g., edge portion of the gate oxide 22) extending laterally outward from the sidewall spacer S11 (see fig. 6).
In re claim 21, Tsai discloses a method (figs. 3-11), comprising:
depositing an oxide layer 20 on a substrate 10 and over a plurality of lightly doped regions 12, 12 adjacent to the substrate 10 (fig. 3; ¶31);
etching the oxide layer 20 to form a gate oxide layer 22 (fig. 4 shows etching the oxide layer 20; ¶31. Moreover, Tsai indicates an edge portion of the gate oxide layer 22 is etched by the steps of forming the gate spacer S11 (fig. 6; ¶33) of the high voltage transistor structure T1 (figs. 4-5; ¶32, 25; the operating voltage of the first transistor structure T1 may be higher than that of the second transistor structure T2, the first region R1 may be regarded as a relatively high voltage transistor region),
depositing, over the gate oxide layer 22, a gate structure 30A of a high voltage transistor structure of a semiconductor device (fig. 6; ¶32);
wherein a dimension of the gate oxide layer 22 along a surface of the substrate 10 is greater than a dimension of the gate structure 30A along the surface of the substrate 10 (e.g., by the distance DS1; ¶26); and
performing an ion implantation operation to form a plurality of source/drain regions 42B, 42B in the lightly doped regions (fig. 8; ¶36).
Tsai discloses depositing the gate structure 30A over the gate oxide layer 22. In other words, Tsai discloses depositing the gate structure after the oxide layer 20 has been etched.
However, Tsai does not expressly disclose depositing the gate structure 30A prior to performing the etch operation to remove the oxide material to form the gate oxide layer.
In the same field of endeavor, Wang discloses a method (figs. 1-10) comprising:
depositing a gate structure G2 (fig. 1; ¶17) prior to performing the etch operation to remove the oxide material 120 to form the gate oxide layer 120a (fig. 6; ¶21-22; “The gate dielectric layer 120 of the second area B is also etched and thus is thinned to become a gate dielectric layer 120a”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Wang and form the gate spacer prior to etching the oxide layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Tsai discloses the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other suitable semiconductor materials (¶27). However, Tsai, as modified by Wang, does not expressly disclose doping the substrate with a first dopant type to form a first doped region of a semiconductor device.
In the same field of endeavor, Oh discloses a method of forming a high voltage transistor (figs. 9A-9I), comprising:
doping a substrate 200 with a first dopant type (e.g., n-type) to form a first doped region 220 of a semiconductor device (¶91-92).
Oh discloses the doped second high voltage deep well HDNW 220 electrically isolates the second high voltage semiconductor element 20 from the substrate, thereby advantageously assisting in determining an operational voltage (¶92).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dope the substrate 10 of Tsai as modified by wang with a first dopant type to form a first doped region of a semiconductor device as taught by Oh to electrically isolate the second high voltage semiconductor element from the substrate, thereby advantageously assisting in determining an operational voltage (¶92 of Oh).
In re claim 22, Tsai, as modified by Wang and Oh, discloses the method of claim 21 outlined above.
Tsai further discloses in fig. 8, wherein a first source/drain region 42B of the plurality of source/drain regions is formed adjacent to a first end of the gate oxide layer (e.g., left end of 22), wherein a second source/drain region 42B of the plurality of source/drain regions is formed adjacent to a second end of the gate oxide layer (e.g., left end of 22), and wherein the first end is opposite to the second end.
In re claim 23, Tsai, as modified by Wang and Oh, discloses the method of claim 21 outlined above.
Tsai further discloses the method further comprising: performing a single sidewall spacer formation process to form a sidewall spacer S11 on a sidewall of the gate structure 30A (fig. 6 shows forming a sidewall spacer S11) after performing the etch operation on the oxide layer 20 (fig. 4 shows etching the oxide layer 20; ¶31). Moreover, Tsai indicates an edge portion of the gate oxide layer 22 is etched by the steps of forming the gate spacer S11 (fig. 6; ¶33) .
However, Tsai does not expressly disclose the sidewall spacer was formed prior to performing the etching the oxide layer.
In the same field of endeavor, Wang further discloses the method (figs. 1-10) further comprising: depositing, prior to etching the oxide layer 120, a first sidewall spacer 142B on a first sidewall (e.g., a left sidewall) of the gate structure G2 and a second sidewall spacer 142B on a second sidewall (e.g., a right sidewall) of the gate structure G2, wherein the second sidewall is opposite to the first sidewall (e.g., forming spacer 142b in fig. 1; ¶17 and fig. 6; ¶21-22; “The gate dielectric layer 120 of the second area B is also etched and thus is thinned to become a gate dielectric layer 120a”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Wang and form the gate spacer prior to etching the oxide layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
In re claim 24, Tsai, as modified by Wang and Oh, discloses the method of claim 23 outlined above.
Tsai further discloses in figs. 10-11, wherein a difference (e.g., DS1; ¶26) between the dimension of the gate oxide layer 22 along the surface of the substrate 10 and the dimension of the gate structure 30A along the surface of the substrate 10 is greater than a dimension of at least one of the first sidewall spacer S11 or the second sidewall spacer along the surface of the substrate 10.
Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Wang and Oh, as applied to claim 10 above and further in view of Cheng et al. (US 20230335641 A1; hereinafter “Cheng”).
In re claim 11, Tsai, as modified by Wang and Oh, discloses the method of claim 10 outlined above, but does not expressly disclose wherein the threshold distance is included in a range of approximately 0.014 microns to approximately 0.05 microns.
In the same field of endeavor, Cheng discloses a method of forming high voltage MOS transistor (figs. 2-6) wherein a threshold distance between an edge of a gate structure 204b (¶117) and an edge of a gate oxide 203b (¶92) is included in a range of approximately 0.03 microns to 0.08 microns (¶120; the threshold distance is same as the thickness of the spacer 308), which overlap the claimed range of approximately 0.014 microns to approximately 0.05 microns.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Cheng into the method of Tsai, as modified by Wang and Oh and extend the gate oxide layer from the edge of the gate structure by a threshold distance as claimed value of approximately 0.014 microns to approximately 0.05 microns. One would have been motivated to do so as Cheng teaches under the same drain voltage Vd, Ioff corresponding to a drain current Id decreases as the threshold distance increases and this improves GIDL problem (¶120 of Cheng).
In re claim 13, Tsai, as modified by Wang and Oh, discloses the method of claim 10, but does not expressly disclose wherein the threshold distance is based on a gate induced drain leakage parameter for the high voltage transistor structure.
In the same field of endeavor, Cheng discloses a method of forming high voltage MOS transistor (figs. 2-6), wherein a threshold distance between an edge of a gate structure 204b (¶117) and an edge of a gate oxide 203b (¶92) is based on a gate induced drain leakage parameter for the high voltage transistor structure (¶120 of Cheng).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Cheng into the method of Tsai, as modified by Wang and Oh and utilize the threshold distance to improve GIDL problem (¶120 of Cheng).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Wang and Oh, as applied to claim 14 above and further in view of Chen et al. (US 20240387523 A1; hereinafter “Chen’523”).
In re claim 16, Tsai, as modified by Wang and Oh, discloses the method of claim 14 outlined above.
Tsai further discloses in figs. 1-11, wherein performing the single sidewall spacer formation process comprises:
performing the single sidewall spacer S11 formation process to form the sidewall spacer on the sidewall of the gate structure 30A and to form another sidewall spacer S21 on another gate structure 30B of a low voltage transistor structure T2 of the semiconductor device (fig. 6; ¶33. The second region R2 may be regarded as a relatively low voltage transistor region; ¶25).
Tsai, as modified by Wang and Oh, does not expressly disclose the low voltage transistor is a fin field effect transistor (finFET).
In the same field of endeavor, Chen’523 discloses a method of forming a semiconductor device (figs. 1-3) wherein a low voltage transistor T2 is a fin field effect transistor (finFET) (¶6; A fin transistor is disposed within the low voltage region, wherein the fin transistor includes a fin structure protrudes from a second surface of the substrate.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen’523 and form the low voltage transistor of Tsai/Wang/Oh as a FinFET.
One would have been motivated to do so as Chen’523 teaches the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, which can therefore more effectively control the channel region. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate (¶3, 6 of Chen’523).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Wang and Oh, as applied to claim 21 above and further in view of Nishibe et al. (US 20050116285 A1; hereinafter “Nishibe”).
In re claim 25, Tsai, as modified by Wang and Oh, discloses the method of claim 21 outlined above.
Tsai, as modified by Wang and Oh, does not expressly disclose wherein a depletion region is formed in the well region and in at least one of the plurality of lightly doped regions.
In the same field of endeavor, Nishibe discloses a method of forming a high voltage MOS transistor (figs. 1-2) wherein a depletion region (e.g., drain depletion layer shown as an area between two dotted lines in fig. 2) is formed in the well region 1 and in at least one of the plurality of lightly doped regions 4a (¶20).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Nishibe and form a depletion layer profile in the high voltage transistor of Tsai/Wang/Oh to have reduced substrate current Isub during operation stage (¶9 of Nishibe).
In re claim 26, Tsai, as modified by Wang, Oh and Nishibe, discloses the method of claim 25 outlined above.
Nishibe further discloses in fig. 2, wherein the depletion region bends around at least one of the plurality of source/drain regions 4b (the upper dotted line of the drain depletion layer).
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai, as applied to claim 27 above and further in view of Cheng et al. (US 20230335641 A1; hereinafter “Cheng”).
In re claim 30, Tsai discloses the method of claim 27 outlined above.
Tsai further discloses wherein the required distance DS1 between the first metal silicide layer 52 and the first gate structure GS1 (i.e., a width of 22A) may still exist for achieving the purpose of reducing the leakage current of the first transistor structure T1 (¶40).
However, Tsai does not expressly disclose wherein the second portion 22A and the third portion of the gate dielectric layer 22A each have a width included a range of approximately 0.014 microns to approximately 0.05 microns.
In the same field of endeavor, Cheng discloses a method of forming high voltage MOS transistor (figs. 2-6) wherein a width of an edge portion of a gate dielectric layer 203b (¶92) which extends from a gate structure 204b (¶117) is in a range of approximately 0.03 microns to 0.08 microns (¶120; the width is same as the thickness of the spacer 308), which overlap the claimed range of approximately 0.014 microns to approximately 0.05 microns.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Cheng into the method of Tsai and extend the gate oxide layer from the edge of the gate structure by a threshold distance as claimed value of approximately 0.014 microns to approximately 0.05 microns. One would have been motivated to do so as Cheng teaches under the same drain voltage Vd, Ioff corresponding to a drain current Id decreases as the threshold distance increases and this improves GIDL problem (¶120 of Cheng).
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893