DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/19/2026. Claims 1-9 and 18-28 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 07/01/2023 is acceptable.
Election/Restrictions
Applicant’s election, of claims 1, 4-9, 18, 20-24 and 26-28, in the “Response to Election / Restriction Filed” filed on 05/19/2026 is acknowledged. This office action considers claims 1-20 are thus pending for prosecution, of which, claims 2-3, 19 and 25 are withdrawn, and claims1, 4-9, 18, 20-24 and 26-28 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vasen et al (US 2021/0119131 A1; hereafter Vasen).
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Regarding claim 1. Vasen discloses a method of forming a semiconductor device, comprising:
forming a dielectric layer (Fig 10, dielectric layer 110, Para [ 0017]) over a substrate (substrate 100, Para [ 0017]);
forming a 2D material layer (2D material 120, Para [ 0018]) over the dielectric layer (bottom dielectric layer 110);
forming an adhesion layer (layer 130, construed as adhesion layer, Para [ 0019]) over the 2D material layer (2D material 120, Para [ 0018]);
forming source/ drain electrodes (contact vias 240 and 250 acting as source/drain contacts, Para [ 0030]) on opposite sides of the adhesion layer (layer 130, construed as adhesion layer, Para [ 0019]); and
forming a first high-k gate dielectric layer (gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]) over the adhesion layer (layer 130, construed as adhesion layer, Para [ 0019]), wherein the adhesion layer (layer 130, construed as adhesion layer, Para [ 0019]) has a material different from a material of the first high-k gate dielectric layer (gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]).
Regarding claim 18. Vasen discloses a method of forming a semiconductor device, comprising:
forming a nitride layer (Fig 10, dielectric layer 110, Para [ 0017]) over a semiconductor substrate (substrate 100, Para [ 0017]);
forming a 2D semiconductor layer (2D material 120, Para [ 0018]) on the nitride layer (Fig 10, dielectric layer 110, Para [ 0017]);
forming a first metal oxide layer (gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]) over the 2D semiconductor layer (2D material 120, Para [ 0018]);
patterning the first metal oxide layer gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]);
performing a first deposition process to form a second metal oxide layer (high-k dielectric layer 160, Para [ 0022, 0033]) on the first metal oxide layer (gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]); and
forming a gate electrode (gate electrode 180, Para [ 0024]) over the second metal oxide layer (high-k dielectric layer 160, Para [ 0022, 0033]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6-8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vasen et al (US 2021/0119131 A1; hereafter Vasen) as applied claims above and further in view of YANG et al (US 2023/0061138 A1; hereafter YANG).
Regarding claim 6. Vasen discloses the method of claim 1, But, Vasen does not disclose explicitly further comprising:
forming a second high-k gate dielectric layer over the first high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a composition different from a composition of the first high-k gate dielectric layer.
In a similar field of endeavor, YANG discloses forming a second high-k gate dielectric layer over the first high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a composition different from a composition of the first high-k gate dielectric layer (Fig 6, gate dielectric layer 733, Para [0092-0095]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Vasen in light of YANG teaching “forming a second high-k gate dielectric layer over the first high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a composition different from a composition of the first high-k gate dielectric layer (Fig 6, gate dielectric layer 733, Para [0092-0095])” for further advantage such as deposition of layers of high quality as gate dielectric layers.
Regarding claim 7. Vasen in light of YANG discloses the method of claim 6, YANG further discloses wherein the second high-k gate dielectric layer has a dielectric constant greater than a dielectric constant of the first high-k gate dielectric layer (hafnium zirconium oxide (HfZrO)/ hafnium oxide (HfOx), based on the stack gate dielectric layer 733, Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Vasen in light of YANG teaching “wherein the second high-k gate dielectric layer has a dielectric constant greater than a dielectric constant of the first high-k gate dielectric layer (hafnium zirconium oxide (HfZrO)/ hafnium oxide (HfOx), based on the stack gate dielectric layer 733, Para [ 0093])” for further advantage such as deposition of layers of high quality as gate dielectric layers.
Regarding claim 8. Vasen in light of YANG discloses the method of claim 6, YANG further discloses wherein the first high-k gate dielectric layer is hafnium oxide, and the second high-k gate dielectric layer is hafnium zirconium oxide (hafnium zirconium oxide (HfZrO)/ hafnium oxide (HfOx), based on the stack gate dielectric layer 733, Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Vasen in light of YANG teaching “wherein the first high-k gate dielectric layer is hafnium oxide, and the second high-k gate dielectric layer is hafnium zirconium oxide (hafnium zirconium oxide (HfZrO)/ hafnium oxide (HfOx), based on the stack gate dielectric layer 733, Para [ 0093])” for further advantage such as deposition of layers of high quality as gate dielectric layers. The applicant is reminded, in this regard, that it has been held that a mere selection of known materials generally understood to be suitable to make a device, the selection of the particular material being on the basis of suitability for the intended use, would be entirely obvious. See In re Leshin 227 F.2d 197, 125 USPQ 416 (CCPA 1960) and also Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), (See. MPEP.2144.07).
Regarding claim 20. Vasen discloses the method of claim 18, But, Vasen does not disclose explicitly further comprising:
performing a second deposition process to form a third metal oxide layer on the second metal oxide layer, wherein the third metal oxide layer is doped with zirconium.
In a similar field of endeavor, YANG discloses performing a second deposition process to form a third metal oxide layer on the second metal oxide layer, wherein the third metal oxide layer is doped with zirconium (Fig 6, gate dielectric layer 733, Para [0092-0095]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Vasen in light of YANG teaching “performing a second deposition process to form a third metal oxide layer on the second metal oxide layer, wherein the third metal oxide layer is doped with zirconium (Fig 6, gate dielectric layer 733, Para [0092-0095])” for further advantage such as deposition of layers of high quality as gate dielectric layers.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Vasen et al (US 2021/0119131 A1; hereafter Vasen) as applied claims above and further in view of UKAI et al (US 2021/0325336 A1; hereafter UKAI).
Regarding claim 22. Vasen disclose the method of claim 18, Vasen further discloses depositing a metal layer (gate 180, Para [ 0024]) on the 2D semiconductor layer (2D material 120, Para [ 0018]).
But WANG does not disclose explicitly wherein forming the first metal oxide layer comprises: oxidizing the metal layer to form the first metal oxide layer.
In a similar field of endeavor, UKAI discloses wherein forming the first metal oxide layer comprises: oxidizing the metal layer to form the first metal oxide layer (Para [0055]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Vasen in light of UKAI teaching “wherein forming the first metal oxide layer comprises: oxidizing the metal layer to form the first metal oxide layer (Para [0055])” for further advantage such as simplify and cost-effective manufacturing process to produce semiconductor device.
Claim 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2021/0193801 A1; hereafter WANG) in view of Chung et al (US 2022/0165871 A1; hereafter Chung).
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Regarding claim 23. WANG discloses a method comprising:
forming a dielectric layer (bottom dielectric layer 180, Para [ 0060] discloses “bottom barrier layer 180 may be the same or similar to the material of the top barrier layer 130” and Para [ 0033] discloses barrier layer 130 made with Hfo, which is high-k dielectric material) over a substrate (substrate 110);
forming a two-dimensional (2D) material layer (2D material 120, Para [ 0034) over the dielectric layer (bottom dielectric layer 180);
forming an adhesion layer (spacer layer 160, construed as adhesion layer, Para [ 0043]) over the 2D material layer (2D material 120, Para [ 0034]);
forming source/drain electrodes (source/drain contacts 140, Para [ 0045]) on opposite sides of the adhesion layer (spacer layer 160, construed as adhesion layer, Para [ 0043]);
forming a first high-k gate dielectric layer (gate dielectric 150, such as a high-k gate dielectric, Para [ 0021]) over the adhesion layer (spacer layer 160, construed as adhesion layer, Para [ 0043]) and the source/drain electrodes (source/drain contacts 140, Para [ 0045]).
But WANG does not disclose explicitly forming a second high-k gate dielectric layer over the first high-k gate dielectric layer; and forming a gate electrode over the second high-k gate dielectric layer.
In a similar field of endeavor, Chung discloses forming a second high-k gate dielectric layer over the first high-k gate dielectric layer (Fig 1, Para [ 0055] discloses “top gate dielectric layer 116 comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the top gate dielectric layer 116 include a high-k dielectric material”); and forming a gate electrode (gate electrode 118) over the second high-k gate dielectric layer (gate dielectric layer 116).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG in light of Chung teaching “forming a second high-k gate dielectric layer over the first high-k gate dielectric layer (Fig 1, Para [ 0055] discloses “top gate dielectric layer 116 comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the top gate dielectric layer 116 include a high-k dielectric material”); and forming a gate electrode (gate electrode 118) over the second high-k gate dielectric layer (gate dielectric layer 116)” for further advantage such as improve the integration density of various electronic components and increased gate capacitance with limited or no leakage during normal memory operation.
Regarding claim 24. WANG in light of Chung discloses the method of claim 23, But WANG does not disclose explicitly wherein the 2D material layer comprises a transition metal dichalcogenide (TMD).
In a similar field of endeavor, Chung discloses wherein the 2D material layer comprises a transition metal dichalcogenide (TMD) (Para [ 0013]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG in light of Chung teaching “wherein the 2D material layer comprises a transition metal dichalcogenide (TMD) (Para [ 0013])” for further advantage such as TMDs may allow for the fabrication of material stacks with low densities of interface defects.
Claim 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2021/0193801 A1; hereafter WANG) in view of Chung et al (US 2022/0165871 A1; hereafter Chung) as applied claims above and further in view of YANG et al (US 2023/0061138 A1; hereafter YANG).
Regarding claim 26. WANG in light of Chung discloses the method of claim 23, But WANG and Chung do not disclose explicitly wherein the first high-k gate dielectric layer comprises hafnium oxide, and wherein the second high-k gate dielectric layer comprises hafnium zirconium oxide.
In a similar field of endeavor, YANG discloses wherein the first high-k gate dielectric layer comprises hafnium oxide, and wherein the second high-k gate dielectric layer comprises hafnium zirconium oxide (Fig 6, gate dielectric layer 733, Para [0092-0095]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Chung in light of YANG teaching “wherein the first high-k gate dielectric layer comprises hafnium oxide, and wherein the second high-k gate dielectric layer comprises hafnium zirconium oxide (Fig 6, gate dielectric layer 733, Para [0092-0095])” for further advantage such as deposition of layers of high quality as gate dielectric layers.
Regarding claim 27. WANG and Chung in light of YANG discloses the method of claim 23, But WANG and Chung does not disclose explicitly wherein the second high-k gate dielectric layer has a dielectric constant greater than a dielectric constant of the first high-k gate dielectric layer.
In a similar field of endeavor, YANG discloses wherein the second high-k gate dielectric layer has a dielectric constant greater than a dielectric constant of the first high-k gate dielectric layer (Fig 6, gate dielectric layer 733, Para [0092-0095], based on the same material as discloses instant application such as first high-k gate dielectric layer comprises hafnium oxide, and wherein the second high-k gate dielectric layer comprises hafnium zirconium oxide).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Chung in light of YANG teaching “(Fig 6, gate dielectric layer 733, Para [0092-0095], based on the same material as discloses instant application such as first high-k gate dielectric layer comprises hafnium oxide, and wherein the second high-k gate dielectric layer comprises hafnium zirconium oxide)” for further advantage such as deposition of layers of high quality as gate dielectric layers.
ALTERNATE REJECTION:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MAXEY et al (US 2022/0149192 A1; hereafter MAXEY).
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Regarding claim 1. MAXEY discloses a method of forming a semiconductor device, comprising:
forming a dielectric layer (bottom dielectric layer 104) over a substrate (substrate 102);
forming a 2D material layer (2D material 110, Para [ 0029]) over the dielectric layer (bottom dielectric layer 104);
forming an adhesion layer (dielectric spacers 114, such as low-k dielectric spacers, construed as adhesion layer) over the 2D material layer (2D material 110, Para [ 0029]);
forming source/ drain electrodes (source or drain contact metal 112) on opposite sides of the adhesion layer (dielectric spacers 114, such as low-k dielectric spacers, construed as adhesion layer); and
forming a first high-k gate dielectric layer (gate dielectric 122, such as a high-k gate dielectric) over the adhesion layer (dielectric spacers 114, such as low-k dielectric spacers, construed as adhesion layer), wherein the adhesion layer (dielectric spacers 114, such as low-k dielectric spacers, construed as adhesion layer) has a material different from a material of the first high-k gate dielectric layer (gate dielectric 122, such as a high-k gate dielectric).
Regarding claim 4. MAXEY discloses the method of claim 1, MAXEY further discloses wherein the adhesion layer has a dielectric constant lower (dielectric spacers 114, such as low-k dielectric spacers, construed as adhesion layer) than a dielectric constant of the first high-k gate dielectric layer (gate dielectric 122, such as a high-k gate dielectric).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over MAXEY et al (US 2022/0149192 A1; hereafter MAXEY) as applied claims above and further in view of Gortzen et al (US 2015/0086729 A1; hereafter Gortzen).
Regarding claim 5. MAXEY discloses the method of claim 1, But, MAXEY does not disclose explicitly wherein the adhesion layer is aluminum oxide.
In a similar field of endeavor, Gortzen discloses wherein the adhesion layer is aluminum oxide (Para [0087] discloses “atomic layer deposition is for example suitable for deposition of low-k Aluminum Oxide (Al.sub.2O.sub.3) layers of high quality”).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine MAXEY in light of Gortzen teaching “wherein the adhesion layer is aluminum oxide (Para [0087] discloses “atomic layer deposition is for example suitable for deposition of low-k Aluminum Oxide (Al.sub.2O.sub.3) layers of high quality”)” for further advantage such as deposition of layers of high quality.
Allowable Subject Matter
Claims 9, 21 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 9. The method of claim 6, wherein forming the adhesion layer on the 2D material layer comprises:
forming a metal layer on the 2D material layer; and oxidizing the metal layer to form the adhesion layer.
Regarding claim 21. The method of claim 18, wherein forming the 2D semiconductor layer comprises: forming the 2D semiconductor layer on another substrate; and transferring the 2D semiconductor layer from the another substrate to the nitride layer.
Regarding claim 28. The method of claim 27, wherein the adhesion layer has a dielectric constant lower than a dielectric constant of the first high-k gate dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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