DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, at a second level higher than the first level of the semiconductor device must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The figures do not show this instead figures 2A 3A and 4A appears to be a layout or plan view with the first and second pin being at the same metallization level in the traditional definition of metallization levels.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-13 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The appropriate Wands factor are:
(A) The breadth of the claims; The claim requires the system to provide a physical change specifically re configured to cause the system to perform: placing a first pin and a second pin, wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device, and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device; generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device; selecting a first set of the plurality of first conductive patterns; placing a plurality of interconnection patterns to connect the first pin, the first set of the plurality of first conductive patterns, and the second pin, wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer; and placing first cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin
(B) The nature of the invention The claim is drawn to arranging pattern in a semiconductor device which require semiconductor fabrication tools. Computer processors and memories cannot affect the outside world by themselves.
(C) The state of the prior art for placing pins forming/generating conductive patterns all require semiconductor manufacturing tools
(D) The level of one of ordinary skill; One skill in the art could not make a processor and memory and programs by themselves could not place a pin or form/generate conductive patterns
Based on these factors the claim 8 drawn a system for arranging patterns of a semiconductor device, comprising: at least one processing unit; and at least one memory including computer program code for one or more programs; wherein the at least one memory, the computer program code and the at least one processing unit could not preform the physical outcomes of placing a first pin and a second pin, wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device, and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device; generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device; selecting a first set of the plurality of first conductive patterns; placing a plurality of interconnection patterns to connect the first pin, the first set of the plurality of first conductive patterns, and the second pin, wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer; and placing first cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin.
Claim 8-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As set forth in MPEP 2161.01
When examining computer-implemented functional claims, examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. An algorithm is defined, for example, as “a finite sequence of steps for solving a logical or mathematical problem or performing a task.” Microsoft Computer Dictionary (5th ed., 2002). Applicant may “express that algorithm in any understandable terms including as a mathematical formula, in prose, or as a flow chart, or in any other manner that provides sufficient structure.” Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323, 1340, 86 USPQ2d 1609, 1623 (Fed. Cir. 2008) (internal citation omitted). It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015) (reversing and remanding the district court’s grant of summary judgment of invalidity for lack of adequate written description where there were genuine issues of material fact regarding “whether the specification show[ed] possession by the inventor of how accessing disparate databases is achieved”). If the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention a rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, for lack of written description must be made. For more information regarding the written description requirement, see MPEP § 2162- § 2163.07(b). If the specification does not provide a disclosure of sufficient corresponding structure, materials, or acts that perform the entire claimed function of a means- (or step-) plus- function limitation in a claim under 35 U.S.C. 112(f) or the sixth paragraph of pre-AIA 35 U.S.C. 112, "the applicant has in effect failed to particularly point out and distinctly claim the invention" as required by the 35 U.S.C. 112(b) [or the second paragraph of pre-AIA 35 U.S.C. 112]. In re Donaldson Co., 16 F.3d 1189, 1195, 29 USPQ2d 1845, 1850 (Fed. Cir. 1994) (en banc). A rejection under 35 U.S.C. 112(b) or the second paragraph of pre-AIA 35 U.S.C. 112 must be made in addition to the written description rejection. See also MPEP § 2181, subsection II.B.2(a).
It appears based on figure 7, that this maybe design too and the generation occurs in the memory. However, even at that point there is no algorithm disclosed Applicant merely set forth a desired outcome with no discussion of what would be sufficient to implement the algorithm.
As the claim stands now the claim requires physical transformation of:
placing a first pin and a second pin, wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device, and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device; generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device; selecting a first set of the plurality of first conductive patterns; placing a plurality of interconnection patterns to connect the first pin, the first set of the plurality of first conductive patterns, and the second pin, wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer; and placing first cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin.
As to claims 1 and 8 Applicant has not taught how to method comprising: placing a first pin and a second pin, wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device, and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device; and then generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device
And
For claim 14
wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device, and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device; generating a plurality of first conductive patterns and a plurality of second conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device
A metallization interconnect is formed by laminating sequentially multiple metallization patterns. Thus, a first is formed a second intervening and then the layer above the intervening is formed. Applicant appears to be claims the bottom and the top layer then forming an intervening layer. Applicant has not shown how to form a first and a second and then form a metallization layer that intervenes after forming the layer above the intervening.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1 8 and 14 recitations of: at a second level higher than the first level of the semiconductor device is unclear since there is not fixed reference point as to how higher is being defined.
As to claims 1, 8 and 14 recitation of corresponds to a first metallization layer and a second metallization layer and corresponds to a third metallization layer is not claiming the entire metallization layers applicant is only claiming a first and second pin and ; generating a plurality of first conductive patterns thus recitation of wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer; and placing cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin is unclear since the first metallization on has the first pin and the second metallization only has the second pin thus it is unclear how one placing cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin. Since they are already isolated since there is nothing else to be isolated from. In fact, the only positively required elements are the first pin, the first set of the plurality of first conductive patterns (first set does not limit it to being smaller than all), and the second pin. Thus, there is nothing indicating that they need to be isolated from something else.
It appears applicant wants to have the first and second metallization to be greater than the first pin. Regardless it is unclear what is to be isolated from what and which step interconnects the pins with other element that then requires that requires isolation step. Thus, it is unclear what pins are being isolated from and if a cut pattern is even required if the pins are not connected to anything other than first set of conductive patterns.
Further it is unclear when the cut occurs Applicant claims 1,8 and 14 seem to be staggered over multiple instances in time with step that need to occur before other steps appear to be after the step.
b. As to claim 3 and 10, recitation of and separating the second pin from the plurality of second conductive patterns is unclear if they are removed from the device or if they are cut to isolate the elements.
c. As to claim 4 and 11, claim 4 is unclear, claim 3 and 10 previously recited generating a plurality of second conductive patterns, wherein each of the plurality of second conductive patterns corresponds to the second metallization layer of the semiconductor device; and separating the second pin from the plurality of second conductive patterns.
Claims 4 and 11then requires : selecting one of the plurality of second conductive patterns, wherein a set of the plurality of interconnection patterns overlaps the one of the plurality of second conductive patterns and the set of the plurality of first conductive patterns; and connecting the one of the plurality of second conductive patterns and the second pin. This contradicts claims 3 which required them to be separated or isolated. Further the claim does not set forth how they are connected. Further it is unclear how the isolation step relates to the connecting.
D. As to claim 5 12 and 16, recitation of placing a predetermined pattern overlapping the plurality of first conductive patterns, wherein the predetermined pattern corresponds to a set of routed conductive layers at the third level of the semiconductor device; and placing second cut patterns to isolate the predetermined pattern from the plurality of first conductive patterns.
The claim is unclear since it does not set forth when the step occurs relative to the others steps. Also, recitation of at a third level lack antecedent basis. Further predetermined pattern is unclear applicant if they are the routing conductive layer (routing conductive layers lacks antecedent basis) or are part of the third metallization at all. Applicant has not even established the predetermined patterns are conductive thus placing second cut patterns to isolate the predetermined pattern from the plurality of first conductive patterns.
e. As to claims 7 13 17 and 20, recitation of wherein the isolated pattern corresponds to a non-functional conductive structure of the semiconductor device or functional in clam 20.
Applicant has not claimed enough structure to even define a functional part. Further non-functional under what circumstances. If there is not power the entire device is not functional. If the device wears out it is not functional. This is indefinite since applicant has not set forth the condition or structure that defines functional and non-functional.
d. As to claim 18, Claim 18 is unclear when the cutting occurs
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wang 20230046911.
As to claim 1, the term pin has no specific meaning and will be treated a metallization line, Wang teaches A method of arranging patterns of a semiconductor device, the method comprising: placing a first pin (figure 1 one of the lines in m1) and a second pin (figure 3 one of the lines in m3 that is connected to m2 by a via), wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device (figure 1 m1), and the second pin corresponds to a second metallization layer ( figure 1 m3) located at a second level higher than the first level of the semiconductor device (see figure 1 relative heights) ; generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device (layer m2); selecting a first set of the plurality of first conductive patterns (some of the m2 are connected to m1 and m3 by vias); placing a plurality of interconnection patterns to connect the first pin (the vias between layers), the first set of the plurality of first conductive patterns, and the second pin, wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer (the vias between associated m levels); and placing cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin (there are cuts between the layer that isolate portions of M1 M2 and M3 with other m1-m3 portions).
b. As to claim 2, Wang teaches wherein placing the cut patterns overlapping the first set of the plurality of first conductive patterns comprises: selecting locations, based on locations of the plurality of interconnection patterns, of the cut patterns ( the cut locations were selected to provide the outcome).
c. As to claim 3, Wang teaches generating a plurality of second conductive patterns, wherein each of the plurality of second conductive patterns corresponds to the second metallization layer of the semiconductor device (item 3 other portions); and isolating the second pin from the plurality of second conductive patterns (figure 1 they are no directly connected thus isolated and separated.
d. As to claim 4 Wang teaches selecting one of the plurality of second conductive patterns (one of the m3 that overlaps with m2), wherein a set of the plurality of interconnection patterns overlaps the one of the plurality of second conductive patterns and the set of the plurality of first conductive patterns (the vias); and connecting the one of the plurality of second conductive patterns and the second pin (It is and IC everything is electrically connected to some degree.
e. As to claim 5, Wang teaches placing a predetermined pattern overlapping the plurality of first conductive patterns (paragraph 40 indicates photolithography is used to form each layer so a mask was used which is above the mentalizations when they are formed), wherein the predetermined pattern corresponds to a set of routed conductive layers at the third level of the semiconductor device (the mask patterns define the metallization by definition); and placing second cut patterns to isolate the predetermined pattern from the plurality of first conductive patterns ( the mask provide cut regions or spaces between the portions m2 thus part of m2 is separated or cut from other portions of m2 figure 1).
f. As to claim 6, Wang teaches wherein the first set of the plurality of first conductive patterns at least overlap either the first pin or the second pin (see m2 overlap with m1 and m3).
g. As to claim 7, none the device is function if it is not connected to voltages thus it reads on the claim.
g. As to claim 8-13, , the term pin has no specific meaning and will be treated a metallization line, Wang teaches A method of arranging patterns of a semiconductor device, the method comprising: placing a first pin (figure 1 one of the lines in m1) and a second pin (figure 3 one of the lines in m3 that is connected to m2 by a via), wherein the first pin corresponds to a first metallization layer located at a first level of the semiconductor device (figure 1 m1), and the second pin corresponds to a second metallization layer ( figure 1 m3) located at a second level higher than the first level of the semiconductor device (see figure 1 relative heights) ; generating a plurality of first conductive patterns, wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device (layer m2); selecting a first set of the plurality of first conductive patterns (some of the m2 are connected to m1 and m3 by vias); placing a plurality of interconnection patterns to connect the first pin (the vias between layers), the first set of the plurality of first conductive patterns, and the second pin, wherein the plurality of interconnection patterns corresponds to vias between the first metallization layer and the third metallization layer as well as between the second metallization layer and the third metallization layer (the vias between associated m levels); and placing cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, and the second pin (there are cuts between the layer that isolate portions of M1 M2 and M3 with other m1-m3 portions).
Wang teaches figure 8 at least one processing unit; and at least one memory including computer program code for one or more programs; wherein the at least one memory, the computer program code and the at least one processing unit are configured to cause the system to perform the steps above.
It is noted the claims do not actively require anything other than a processor and a memory.
Moreover, Wang teaches the steps of claim 2-7, which correspond to claims 9-13.
h. As to claims 14 and 18, the term pin has no specific meaning and will be treated a metallization line, Wang teaches A method of arranging patterns of a semiconductor device, the method comprising: placing a first pin ( a line in m1 figure 1) and a second pin ( a line in m4 figure 1, wherein the first pin corresponds to a first metallization layer (m1) located at a first level of the semiconductor device (figure 1), and the second pin corresponds to a second metallization layer located at a second level higher than the first level of the semiconductor device (figure 1 m4 relative height to m1); generating a plurality of first conductive patterns and a plurality of second conductive patterns (item m2), wherein each of the plurality of first conductive patterns corresponds to a third metallization layer located at a third level between the first level and the second level of the semiconductor device (m2 is between m1 and m4), and each of the plurality of second conductive patterns corresponds to a fourth metallization layer located at a fourth level between the second level and the third level of the semiconductor device ( m3 between m2 and m4); selecting a first set of the plurality of first conductive patterns and a first set of the plurality of second conductive patterns; connecting the first pin, the first set of the plurality of first conductive patterns (vias connecting m2 to m1), the first set of the plurality of second conductive patterns , and the second pin m(3 connected via m4 through the vias); and cutting the first set of the plurality of first conductive patterns and the first set of the plurality of second conductive patterns to form an isolated pattern comprising the first pin, the first set of the plurality of first conductive patterns, the first set of the plurality of second conductive patterns, and the second pin (there are cut that are formed between each set of lines to provide isolation).
Claim 18 further requires or defines cutting as
wherein cutting the first set of the plurality of first conductive patterns comprises: placing first interconnection patterns to connect the first pin and the first set of the plurality of first conductive patterns, wherein each of the first interconnection patterns corresponds to a first via between the first metallization layer and the third metallization layer, and wherein cutting the first set of the plurality of first conductive patterns comprises: placing first cut patterns (thus cutting is equivalent to forming patterns), based on locations of the first interconnection patterns, overlapping the first set of the plurality of first conductive patterns ( the cut locations were selected to provide the outcome)..
i. As to claim 15, Wang teaches wherein connecting the first pin, the first set of the plurality of first conductive patterns, the first set of the plurality of second conductive patterns, and the second pin comprises: placing first interconnection patterns to connect the first pin and the first set of the plurality of first conductive patterns (the vias), wherein each of the first interconnection patterns corresponds to a first via between the first metallization layer and the third metallization layer(see the vias corresponding to layer in figure 1); and placing second interconnection patterns to connect the first set of the plurality of first conductive patterns and the first set of the plurality of second conductive patterns, wherein each of the second interconnection patterns corresponds to a second via between the third metallization layer and the fourth metallization layer (the vias in figure 1 corresponding the layers); and placing third interconnection patterns to connect the first set of the plurality of second conductive patterns and the second pin, wherein each of the third interconnection patterns corresponds to a third via between the second metallization layer and the fourth metallization layer (see the vias).
j. As to claim 16, Wang teaches placing a predetermined pattern overlapping the plurality of first conductive patterns (paragraph 40 indicates photolithography is used to form each layer so a mask was used which is above the mentalizations when they are formed), wherein the predetermined pattern corresponds to a set of routed conductive layers at the third level of the semiconductor device (the mask patterns define the metallization by definition); and placing second cut patterns to isolate the predetermined pattern from the plurality of first conductive patterns ( the mask provide cut regions or spaces between the portions m2 thus part of m2 is separated or cut from other portions of m2 figure 1).
k. As to claim 17, none the device is function if it is not connected to voltages thus it reads on the claim.
l. As to claim 19, Wang teaches wherein cutting the first set of the plurality of first conductive patterns further comprises: placing second interconnection patterns to connect the first set of the plurality of first conductive patterns and the first set of the plurality of second conductive patterns (vias connect M2 to M3), wherein each of the second interconnection patterns corresponds to a second via between the third metallization layer and the fourth metallization layer ( the vias between m2 and m3); placing second cut patterns ( there are cut patterns thus cutting is the same as forming a cut pattern), based on locations of the second interconnection patterns, overlapping the first set of the plurality of first conductive patterns ( the cuts are defined to separate the devices.
m. As to claim 20, Wang teaches connecting the isolated pattern to a circuit pattern, wherein the circuit pattern corresponds to a functional conductive structure of the semiconductor device ( when the devices is connected a bias at the pads 105 it becomes functional).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights