DETAILED ACTION
This office action is in response to the application filed on December 10, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's arguments filed on December 10, 2025, in response to the office action mailed on September 11, 2025 are acknowledged. The present office action is made with all the suggested arguments being fully considered. Accordingly, claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 28, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 12, 14, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2015/0171024) in view of Shih (US 2021/0090985).
With respect to Claim 1, Choi shows (Fig. 4L) most aspects of the current invention including a package module, comprising:
an interposer (178) including a dummy via formation region having dummy vias (Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL)
a plurality of semiconductor dies (124) on the interposer, wherein a sidewall of a semiconductor die in the plurality of semiconductor dies is over the dummy via formation region
a molding material layer (190) on the interposer encapsulating the plurality of semiconductor dies, wherein an interface between the sidewall of the semiconductor die and the molding material layer is over the at least one dummy via
Furthermore, Choi shows dummy vias (e.g. Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL). However, Choi does not explicitly state they are dummy vias.
On the other hand, and in the same field of endeavor, Shih teaches (Fig. 13) a package module, comprising an interposer (100) including a dummy via formation region (501a) having at least one dummy via (510a), and a plurality of semiconductor dies (11,12) on the interposer and disposed over the dummy via formation region. Shih teaches the dummy via is used for the purposes of stress relief or warpage control (par 31).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a dummy via formation region having at least one dummy via in the device of Choi, as taught by Shih for the purposes of stress relief or warpage control.
With respect to Claim 2, Choi shows (Fig. 4L) a bonding layer (184) on the interposer, wherein the molding material layer and the semiconductor die contact bonding layer over the at least one dummy via.
With respect to Claim 3, Choi shows (Fig. 4L) wherein the sidewall of the semiconductor die is located over the dummy via formation region. With respect to the sidewall of the semiconductor die is located over a center of the dummy via formation region, it is noted that the specification fails to provide teachings about the criticality of having the sidewall of the semiconductor die is located over a center of the dummy via formation region, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy via formation region disclosed by Choi in view of Shih, as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular dummy via formation region claimed by applicant is nothing more than one of numerous dummy via formation region shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With respect to Claim 4, Choi shows (Fig. 4L) wherein the sidewall of the semiconductor die is located over the at least one dummy via. With respect to the sidewall of the semiconductor die is located over a center of the at least one dummy via, it is noted that the specification fails to provide teachings about the criticality of having the sidewall of the semiconductor die is located over a center of the at least one dummy via, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy via disclosed by Choi in view of Shih, as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular dummy via claimed by applicant is nothing more than one of numerous dummy via shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With respect to Claim 5, Choi shows (Fig. 4L) wherein the dummy via formation region is located under a periphery of the semiconductor die.
With respect to Claim 6, Choi shows (Fig. 4L) wherein the molding material layer is located over the dummy via formation region.
With respect to Claim 7, Choi shows (Fig. 4L) wherein the interposer (178) comprises a semiconductor material layer (170) and the at least one dummy via is located in one of: an uppermost portion of the semiconductor material layer; or a lowermost portion of the semiconductor material layer (par 47)
With respect to Claim 8, Shih shows (Fig. 21) wherein a thickness of the at least one dummy via is substantially equal to a total thickness of the interposer.
With respect to Claim 9, Choi shows (Fig. 4L) wherein the at least one dummy via comprises a plurality of dummy vias having a dummy via pattern.
With respect to Claim 12, Choi shows (Fig. 4L) wherein the plurality of semiconductor dies is connected to the interposer by hybrid bonding.
With respect to Claim 14, Choi shows (Fig. 4L) wherein an overlap distance between the sidewall of the semiconductor die and a sidewall of the dummy via formation region is in a range of 0 to 2mm.
With respect to Claim 16, Choi shows (Fig. 4a-41) most aspects of the current invention including a method of making a package module, the method comprising:
Forming an interposer (178) including a dummy via formation region having dummy vias (Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL)
attaching a plurality of semiconductor dies (124) on the interposer, wherein a sidewall of a semiconductor die in the plurality of semiconductor dies is over the dummy via formation region
forming a molding material layer (190) on the interposer to encapsulate the plurality of semiconductor dies, wherein an interface between the sidewall of the semiconductor die and the molding material layer is over the at least one dummy via
Furthermore, Choi shows dummy vias (e.g. Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL). However, Choi does not explicitly state they are dummy vias.
On the other hand, and in the same field of endeavor, Shih teaches (Fig. 13) a method of making a package module, comprising an interposer (100) including a dummy via formation region (501a) having at least one dummy via (510a), and a plurality of semiconductor dies (11,12) on the interposer and disposed over the dummy via formation region. Shih teaches the dummy via is used for the purposes of stress relief or warpage control (par 31).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a dummy via formation region having at least one dummy via in the device of Choi, as taught by Shih for the purposes of stress relief or warpage control.
With respect to Claim 17, Choi shows (Fig. 4L) forming a bonding layer (184) on the interposer, wherein the attaching of the plurality of semiconductor dies comprises attaching the plurality of semiconductor dies to the interposer with the bonding layer, and the forming of the molding material layer comprises forming the molding material layer such that the molding material layer and the semiconductor die contact the bonding layer over the at least one dummy die.
With respect to Claim 18, Shih teaches (Fig. 13) wherein the attaching of the plurality of semiconductor dies comprises attaching the plurality of semiconductor dies such that the sidewall of the semiconductor die is located over the dummy via formation region.
With respect to the attaching the plurality of semiconductor dies such that the sidewall of the semiconductor die is located over a center of the dummy via formation region, it is noted that the specification fails to provide teachings about the criticality of having the attaching of the plurality of semiconductor dies comprises attaching the plurality of semiconductor dies such that a sidewall of the semiconductor die is located over the dummy via formation region, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy via formation region disclosed by Choi in view of Shih, as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular dummy via formation region claimed by applicant is nothing more than one of numerous dummy via formation region shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Claims 10-11, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2015/0171024) in view of Shih (US 2021/0090985) and in further view of Chen (US 2016/0093572).
With respect to Claim 10, Choi in view of Shih shows most aspects of the present invention. However, the combination of references do not show wherein the plurality of dummy vias comprises a plurality of rows of dummy vias substantially aligned in a direction perpendicular to the sidewall of the semiconductor die.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 8-9) a package module, comprising an interposer (600) including a dummy via formation region having at least one dummy via (304), and a plurality of semiconductor dies (804) on the interposer and disposed over the dummy via formation region, wherein the plurality of dummy vias comprises a plurality of rows of dummy vias substantially aligned in a direction perpendicular to the sidewall of the semiconductor die (see fig 9). Chen teaches the dummy vias raise the metal density in the spaces between the active via regions and the substrate region, preventing dishing or overgrinding of the molding compound layer in the spaces between the substrate and active vias (par 34).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the plurality of dummy vias comprises a plurality of rows of dummy vias substantially aligned in a direction perpendicular to the sidewall of the semiconductor die in the device of Choi in view of Shih, as taught by Chen because the dummy vias raise the metal density in the spaces between the active via regions and the substrate region, preventing dishing or overgrinding of the molding compound layer in the spaces between the substrate and active vias.
With respect to Claim 11, Choi in view of Shih shows most aspects of the present invention. However, the combination of references do not show wherein the plurality of dummy vias comprises a column of dummy vias substantially aligned with the sidewall of the semiconductor die.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 8-9) a package module, comprising an interposer (600) including a dummy via formation region having at least one dummy via (304), and a plurality of semiconductor dies (804) on the interposer and disposed over the dummy via formation region, wherein the plurality of dummy vias comprises a column of dummy vias substantially aligned with the sidewall of the semiconductor die (see fig 9). Chen teaches the dummy vias raise the metal density in the spaces between the active via regions and the substrate region, preventing dishing or overgrinding of the molding compound layer in the spaces between the substrate and active vias (par 34).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the plurality of dummy vias comprises a column of dummy vias substantially aligned with the sidewall of the semiconductor die in the device of Choi in view of Shih, as taught by Chen because the dummy vias raise the metal density in the spaces between the active via regions and the substrate region, preventing dishing or overgrinding of the molding compound layer in the spaces between the substrate and active vias.
With respect to Claim 13, Choi in view of Shih shows most aspects of the present invention. However, the combination of references do not show wherein a thickness of the at least one dummy via is greater than 1µm and less than or equal to a thickness of the interposer.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 8-9) a package module, comprising an interposer (600) including a dummy via formation region having at least one dummy via (304), and a plurality of semiconductor dies (804) on the interposer and disposed over the dummy via formation region, wherein a thickness of the at least one dummy via is greater than 1µm and less than or equal to a thickness of the interposer (par 34).
Regarding claim 13, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Chen), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Choi in view of Shih.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 15, Choi in view of Shih shows most aspects of the present invention. However, the combination of references do not show wherein the at least one dummy via comprises a plurality of dummy vias and an area ratio of a total area of a plurality of dummy dies to an area of the dummy via formation region is in range from 0.1 to 0.99.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 8-9) a package module, comprising an interposer (600) including a dummy via formation region having at least one dummy via (304), and a plurality of semiconductor dies (804) on the interposer and disposed over the dummy via formation region, wherein the at least one dummy via comprises a plurality of dummy vias and an area ratio of a total area of a plurality of dummy dies to an area of the dummy via formation region is in range from 0.1 to 0.99 (par 34).
Regarding claim 15, the courts have held that differences in the area ratio will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such area ratios are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the area ratios and similar area ratios are known in the art (see e.g. Chen), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Choi in view of Shih.
Criticality: The specification contains no disclosure of either the critical nature of the claimed area ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2015/0171024) in view of Shih (US 2021/0090985) and in further view of Kim (US 2022/0013487).
With respect to Claim 19, Choi shows (Fig. 4L) most aspects of the current invention including a package module, comprising:
an interposer (178) including a dummy via formation region having dummy vias (Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL)
a plurality of semiconductor dies (124) on the interposer, wherein a sidewall of a semiconductor die in the plurality of semiconductor dies is over the dummy via formation region
a molding material layer (190) on the interposer encapsulating the plurality of semiconductor dies, wherein an interface between the sidewall of the semiconductor die and the molding material layer is over the at least one dummy via
Additionally, Choi shows dummy vias (e.g. Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL). However, Choi does not show a package substrate; the package module on the package substrate, a stiffener ring on the package substrate around the package module and further does not explicitly state they are dummy vias.
On the other hand, and in the same field of endeavor, Shih teaches (Fig. 12-13) a package substrate (302); a package module on the package substrate, comprising an interposer (100) including a dummy via formation region (501a) having at least one dummy via (510a), and a plurality of semiconductor dies (11,12) on the interposer and disposed over the dummy via formation region. Shih teaches the dummy via is used for the purposes of stress relief or warpage control (par 31).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have a package substrate; the package module on the package substrate and wherein a dummy via formation region having at least one dummy via in the device of Choi, as taught by Shih for the purposes of stress relief or warpage control.
However, Shih does not show a stiffener ring on the package substrate around the package module.
On the other hand, and in the same field of endeavor, Kim teaches (Fig. 1a-1b) a package substrate (100); a package module on the package substrate, comprising an interposer (200) on the package substrate, a plurality of semiconductor dies (310,320) on the interposer, and further a stiffener ring (500) on the package substrate around the package module. Kim teaches the stiffener ring helps to prevent warpage of the package substrate or the interposer (par 41) and the stiffener ring is used to reduce the stress applied to the package substrate and to increase reliability of the semiconductor package (par 43).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have a stiffener ring on the package substrate around the package module in the device of Choi in view of Shih, as taught by Kim because the stiffener ring helps to prevent warpage of the package substrate or the interposer and the stiffener ring is used to reduce the stress applied to the package substrate and to increase reliability of the semiconductor package.
With respect to Claim 20, Choi shows (Fig. 4L) the dummy via formation region (Middle TSVs 176 between the two dies that are not electrically connected to the dies or RDL) are formed in a middle are of the interposer. Additionally, Kim teaches (Fig. 1a-1b) the interposer (200) on the package substrate is formed in a region R1 that is positioned in the middle of the package substrate and the stiffener ring (500) is positioned on a region R2 of the package substrate which is on an outer edge of the package substrate. Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a distance between the dummy via formation region and an outer sidewall of the interposer, is greater than a distance between the outer sidewall of the interposer and an inner edge of the stiffener ring.
Additionally, it has been held by the court that a prima facie case of obviousness exists in the case where all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. See in re KSR Int’l Co. v. Teleflex Inc, 550 U.S. at 416, 82 USPQ2d at 1395.
Response to Arguments
Applicant's arguments filed on December 10, 2025 have been fully considered but they are not persuasive.
Applicant argues: Independent claim 1 is amended to recite, inter alia, a molding material layer on the interposer encapsulating the plurality of semiconductor dies, wherein an interface between the sidewall of the semiconductor die and the molding material layer is over the at least one dummy via. Independent claims 16 and 19 are amended to recite analogous elements. Support for the amendment may be found in the originally-filed specification, for example, at paragraphs [0062]-[0064] and [0070]-[0071] and FIGS. 1A, 1C and 1D.
Examiner responds: The examiner respectfully disagrees. In response to applicant's arguments that the primary references fail to show a feature of Applicant’s invention, it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In particular, the limitations as recited in the body of claim 1 do not preclude the examiner's interpretation of the claimed limitation reciting “an interface between the sidewall of the semiconductor die and the molding material layer is over the at least one dummy via” feature as reading on the arrangement disclosed by Choi.
Additionally, the examiner does not understand the limitation to require the interface to completely overlap the at least one dummy via, as argued, as an interface between the sidewall of the semiconductor die and the molding material layer that is disposed above the at least one dummy via would satisfy the limitation as recited in the body of claims 1, 16 and 19. The examiner has interpreted Choi consistently with the applicant’s disclosure, and has made a proper rejection of the currently presented claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814