Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Currently, claims 1-11 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 6-8 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pub. No. US 2009/0159953 A1) in view of Du et al. (Pub. No. US 2016/0218041 A1, herein Du).
Regarding claims 1 and 8, Kim discloses a method of forming a semiconductor device, comprising: forming an isolation structure 160 between a plurality of active areas (Kim: Figs. 4-7 and paragraphs [0015]-[0017]); forming semiconductor structures 210 over the active areas, wherein a portion of each of the semiconductor structures is embedded in the isolation structure (Kim: Figs. 8-10 and paragraphs [0021]-[0023]); forming sacrificial structures on the semiconductor structures; performing an ion implantation process to form implanted regions 230-240 between portions of the semiconductor structures embedded in the isolation structure; removing the sacrificial structures (Kim: Figs. 10-11 and paragraphs [0023]-[0026]; Kim inherently discloses the presence of a photoresist or hard mask as the “sacrificial structures” over the layers 210-220 to remove the patterns 210-220 in the cell area B.) to form patterned semiconductor structures 210-215; forming a dielectric structure 225 on the patterned semiconductor structure; and forming a control structure 265a-265b on the dielectric structure (Kim: Figs. 12-13 and paragraphs [0028]-[0029]).
Kim does not specifically show wherein the implanted regions are disposed within an upper portion of the isolation structure.
However, in the same field of endeavor, Du states “while the shallow trench isolation 103 is annealed, the distribution of the implanted ions (e.g., carbon ions) may be adjusted in the shallow trench isolation 103, thereby further adjusting the etch rate of the shallow trench isolation 103. In the present embodiment, by performing ion implantation (step A5) and annealing (step A7) to the shallow trench isolation 103, the etch rate to the shallow trench isolation 103 can be reduced in the subsequent etching to remove the portion of the isolation material layer 1030 located in the regions between adjacent fins of the fin-type structure 1001. That is, by improving the etching selectivity, the improper etching of the shallow trench isolation 103 during the subsequent etching is reduced, thereby improving the performance and reliability of the resulting semiconductor device” (Du: paragraph [0048]).
Therefore, given the teachings of Du, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Kim in view of Du by employing the implanted regions within an upper portion of the isolation structure.
Regarding claims 7 and 10, Kim in view of Du teaches the method of forming the semiconductor device as claimed in claim 1, wherein the steps of forming the dielectric structure comprises: performing multiple atomic layer deposition processes to sequentially form a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the second dielectric layer comprises a different material than a material of the first dielectric layer and the third dielectric layer (Kim: Figs. 12-15 and paragraph [0022]).
Regarding claims 2, 6 and 9, Kim does not specifically state the ion implantation process comprises carbon ion implantation, and performing an annealing process after performing the ion implantation process.
However, in the same field of endeavor, Du teaches a method of manufacturing a semiconductor device, including: the ion implantation process comprises carbon ion implantation, and performing an annealing process after performing the ion implantation process to activate the dopant material (Du: paragraph [0048]).
Therefore, given the teachings of Du, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Kim in view of Du by employing the carbon ion implantation and annealing.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Du, as applied above, and further in view of Jeong (Pub. No. US 2010/0112799 A1).
Regarding claims 4 and 5, the previous combination does not specifically state the steps of forming the sacrificial structures comprises: performing a wet oxidation process on the semiconductor structures to form the sacrificial structures on other portions of the semiconductor structures not embedded in the isolation structure, wherein the wet oxidation process comprises in-situ steam oxidation.
However, in the same field of endeavor, Jeong teaches performing a wet oxidation process on the semiconductor structures to form the sacrificial structures on other portions of the semiconductor structures not embedded in the isolation structure, wherein the wet oxidation process comprises in-situ steam oxidation (Jeong: paragraph [0030] and Figs. 6-13) to deliver a processing technique with no need for extra chemicals, while providing high growth rate and lower costs. Performing in-situ wet oxidation is well-known in the art and it offers cleaner interface, better repeatability, reduced defects and contamination, shorter process flow and integration with other steps.
Therefore, given the teachings of Jeong, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Jeong by employing the in-situ wet oxidation.
Allowable Subject Matter
Claims 3 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 3, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the step of forming the semiconductor structures comprises: forming a plurality of first trenches in the isolation structure, wherein the first trenches correspond to the active areas; forming a semiconductor material in the first trenches and over the isolation structure; removing a portion of the semiconductor material to form the semiconductor structures, wherein top surfaces of the semiconductor structures and top surfaces of the isolation structures are coplanar; and removing a portion of the isolation structure to form a plurality of second trenches between the semiconductor structures.
With respect to claim 11, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a ratio of a thickness of the first dielectric layer to a shortest distance from a bottommost section of each of the patterned semiconductor structures to a bottommost section of the second dielectric layer in a normal direction of the isolation structure is 1/5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-2 and 4-10 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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January 13, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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