DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 1/5/2026 "Reply" elects without traverse and identifies claims 16-35 as being drawn to Invention II, Species B. The Reply cancels claims 1-15.
The 12/1/2025 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17, 21-22, and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wan US Pub. No. 2014/0042298.
Regarding claim 16, in FIGs. 1-9, Wan discloses a method of forming an image sensor integrated chip structure, comprising: bonding (paragraph [0011]) a first-side (top) of a first substrate (202) to a second-side (bottom) of a second substrate (102), so that a first interconnect structure (134, paragraph [0019]) is between the first substrate and the second substrate; forming a plurality of pixel support devices (126/128/130, paragraph [0017]) onto a first-side of the second substrate facing away from the first substrate; forming a second interconnect structure (138/140/142) onto the first-side of the second substrate; forming a plurality of image sensing elements (24, paragraph [0012]) in a third substrate (22); forming a transfer gate (28, paragraph [0013]) onto a first-side of the third substrate; forming a third interconnect structure (38/40/42/48), including interconnect wires and interconnect vias, on the first-side of the third substrate; and bonding the first-side (bottom) of the third substrate to the first-side (top) of the second substrate.
Regarding claim 17, in FIGs. 1-9, Wan discloses forming a through-substrate-via (TSV) (146, paragraph [0025]) extending through the second substrate, the TSV being configured to electrically couple the first interconnect structure to the second interconnect structure.
Regarding claim 21, in FIGs. 1-9, Wan discloses a method of forming an image sensor integrated chip structure, comprising: forming one or more logic devices (204, paragraph [0027]) within a first substrate (202); bonding a second substrate (102) to the first substrate along a first bonding interface having a first plurality of metal regions (146, paragraph [0026]) and a first plurality of dielectric regions (regions of 144, paragraph [0025]); forming a plurality of pixel support devices (126/128/130, paragraph [0017]) along a surface of the second substrate that faces away from the first substrate; forming a plurality of image sensing elements (24, paragraph [0012]) within pixel regions of a third substrate (22), the pixel regions respectively comprising two or more of the plurality of image sensing elements; forming a plurality of transfer gates (28, paragraph [0013]) within the pixel regions of the third substrate; and bonding the second substrate to the third substrate along a second bonding interface having a second plurality of metal regions (42/142, paragraphs [0016] and [0020]) and a second plurality of dielectric regions (regions of 36, paragraph [0015]).
Regarding claim 22, in FIGs. 1-9, Wan discloses forming a first interconnect structure (134, paragraph [0019]) on the first substrate, a second interconnect structure (138/140/142) on the second substrate, and a third interconnect structure (38/40/42/48) on the third substrate; and wherein the third interconnect structure comprises interconnect wires and interconnect vias confined between the second substrate and the third substrate.
Regarding claim 28, in FIGs. 1-9, Wan discloses that the plurality of pixel support devices comprise a reset transistor, a source-follower transistor, and a row-select transistor (paragraph [0017]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-20, 30-31, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Wan US Pub. No. 2014/0042298 in view of Takizawa (US Pub. No. 2022/0037388).
Regarding claim 18, Wan appears not to explicitly disclose forming an isolation structure to vertically extend completely through the third substrate, wherein the isolation structure is configured to be laterally between adjacent ones of the plurality of image sensing elements.
However in FIG. 3, Takizawa discloses a similar method of forming an image sensor wherein an isolation structure (144, paragraph [0109]) is formed to vertically extend completely through a third substrate (141, paragraph [0112]), wherein the isolation structure is configured to be laterally between adjacent ones of a plurality of image sensing elements (142, paragraph [0107]). Takizawa discloses that the isolation structure prevents crosstalk between the image sensing elements (paragraph [0109]).
To prevent crosstalk between the image sensing elements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form an isolation structure to vertically extend completely through the third substrate, wherein the isolation structure is configured to be laterally between adjacent ones of the plurality of image sensing elements.
Regarding claim 19, the combination of Wan and Takizawa discloses (see Wan FIGs. 1-9) that the first-side of the third substrate comprises a surface (e.g. surface with elements 28) that continuously extends through an opening in the isolation structure from over a first image sensing element of the plurality of image sensing elements to over a second image sensing element of the plurality of image sensing elements.
Regarding claim 20, the combination of Wan and Takizawa discloses (see Wan FIGs. 1-9) forming a first doped well region (32, paragraph [0013]) to be arranged along the first-side of the third substrate and within the opening.
Regarding claim 30, in FIGs. 1-9, Wan discloses a method of forming an image sensor integrated chip structure, comprising: forming a plurality of pixel support devices (126/128/130, paragraph [0017]) onto a first-side of a first substrate (102), wherein the plurality of pixel support devices comprise a reset transistor (130), a source-follower transistor (128), and a row-select transistor (126); forming a first interconnect structure (138/140/142) onto the first-side of the first substrate; forming a plurality of image sensing elements (24) in a second substrate (22); forming a plurality of transfer gates (28, paragraph [0013]) onto a first-side of the second substrate; forming a second interconnect structure (38/40/42/48), including interconnect wires and interconnect vias, on the first-side of the second substrate; and bonding (paragraph [0011]) the first-side of the first substrate to the first-side of the second substrate.
Wan appears not to explicitly disclose forming an isolation structure within the second substrate and wrapping around a pixel region comprising a plurality of image sensor regions, the plurality of image sensor regions respectively comprising one of the plurality of image sensing elements and one of the plurality of transfer gates.
However in FIGs. 3-4, Takizawa discloses a similar method of forming an image sensor comprising forming an isolation structure (144, paragraph [0109]) within a substrate (141) and wrapping around a pixel region comprising a plurality of image sensor regions, the plurality of image sensor regions respectively comprising one of a plurality of image sensing elements (142) and one of a plurality of transfer gates (1023). Takizawa discloses that the isolation structure prevents crosstalk between the image sensing elements (paragraph [0109]).
To prevent crosstalk between the image sensing elements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form an isolation structure within the second substrate and wrapping around a pixel region comprising a plurality of image sensor regions, the plurality of image sensor regions respectively comprising one of the plurality of image sensing elements and one of the plurality of transfer gates.
Regarding claim 31, the combination of Wan and Takizawa discloses that the isolation structure extends between two or more of the plurality of image sensor regions within the pixel region.
Regarding claim 35, the combination of Wan and Takizawa discloses (see Wan, FIG. 9) performing an implantation process (Wan paragraph [0013]) to form a first doped well region arranged between neighboring ones of the plurality of image sensor regions along a first direction, and between sidewalls of the isolation structure along a second direction that is perpendicular to the first direction in a plan-view (see Takizawa, FIG. 3).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Wan US Pub. No. 2014/0042298 in view of Yanagita (US Pub. No. 2015/0179691).
Regarding claim 23, Wan appears not to explicitly disclose forming a floating diffusion node within the third substrate, wherein the floating diffusion node is shared between a first image sensing element and a second image sensing element of the plurality of image sensing elements.
The art however well recognized a floating diffusion node within a substrate, wherein the floating diffusion node is shared between a first image sensing element and a second image sensing element of a plurality of image sensing elements to be suitable for use as floating diffusion node configuration in an imaging device. See, for example, Yanagita, paragraph [0041].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the floating diffusion node within the third substrate, wherein the floating diffusion node is shared between a first image sensing element and a second image sensing element of the plurality of image sensing elements for its recognized suitability as floating diffusion node configuration in an imaging device.
Regarding claim 24, the combination of Wan and Yanagita discloses (see FIG. 9 of Wan) that the third interconnect structure (38/40/42) is configured to connect the floating diffusion node (32) to the plurality of pixel support devices by way of the second interconnect structure.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Wan US Pub. No. 2014/0042298 in view of Yanagita (US Pub. No. 2015/0179691) as applied to claim 23, and further in view of Zang (US Pub. No. 2023/0282671).
Regarding claim 25, the combination of Wan and Yanagita appears not to explicitly disclose etching the third substrate to form one or more trenches laterally between adjacent ones of the plurality of image sensing elements and over the floating diffusion node, wherein the one or more trenches have a height over the floating diffusion node that is less than a thickness of the third substrate; and depositing a dielectric material within the one or more trenches.
In FIGs. 1-4E, Zang discloses a similar method of forming an image sensor wherein a substrate is etched to form one or more trenches (430T/132, paragraph [0042]) laterally between adjacent ones of the plurality of image sensing elements (408/410/412/422) and over the floating diffusion node (104, paragraph [0022]), wherein the one or more trenches have a height over the floating diffusion node that is less than a of the substrate; and depositing a dielectric material (438, paragraph [0046]) within the one or more trenches to prevent crosstalk between adjacent image sensing elements (paragraph [0038]).
To prevent crosstalk between adjacent image sensing elements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to etch the third substrate to form one or more trenches laterally between adjacent ones of the plurality of image sensing elements and over the floating diffusion node, wherein the one or more trenches have a height over the floating diffusion node that is less than a thickness of the third substrate; and deposit a dielectric material within the one or more trenches.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Wan US Pub. No. 2014/0042298 in view of Zang (US Pub. No. 2023/0282671).
Regarding claim 29, in FIGs. 1-9, Wan discloses forming one or more floating diffusion regions (32, paragraph [0013]) within the third substrate, the one or more floating diffusion regions being operably coupled to the plurality of transfer gates within the adjacent image sensor regions.
Wan appears not to explicitly disclose etching the third substrate to form one or more trenches surrounding the pixel regions and laterally separating adjacent image sensor regions that respectively comprise a transfer gate of the plurality of transfer gates and an image sensing element of the plurality of image sensing elements; depositing a dielectric (438, paragraph [0046]) within the one or more trenches.
In FIGs. 4A-4E, Zang discloses a similar method of forming an image sensor wherein a substrate (402) is etched to form one or more trenches (430T, paragraph [0042]) surrounding pixel regions (408/410/412/422) and laterally separating adjacent image sensor regions that respectively comprise a transfer gate (422) of a plurality of transfer gates and an image sensing element (408/410/412) of a plurality of image sensing elements; depositing a dielectric (438, paragraph [0046]) within the one or more trenches to prevent crosstalk between adjacent image sensing elements (paragraph [0038]).
To prevent crosstalk between adjacent image sensing elements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to etch the third substrate to form one or more trenches surrounding the pixel regions and laterally separating adjacent image sensor regions that respectively comprise a transfer gate of the plurality of transfer gates and an image sensing element of the plurality of image sensing elements; deposit a dielectric within the one or more trenches.
Allowable Subject Matter
Claims 26-27 and 32-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 26-27, the prior art failed to disclose or reasonably suggest the claimed a method of forming an image sensor integrated chip structure particularly characterized by forming a first doped well region within the third substrate, wherein a first-side of the third substrate, which faces the second substrate, comprises a surface that continuously extends through an opening in the dielectric material from over the first image sensing element, to over the first doped well region, and to over the second image sensing element.
Regarding claims 32-33, the prior art failed to disclose or reasonably suggest the claimed a method of forming an image sensor integrated chip structure particularly characterized by an opening that laterally extends through the isolation structure, the opening being located at corners of four of the plurality of image sensor regions and the floating diffusion region being located within the opening.
Regarding claim 34, the prior art failed to disclose or reasonably suggest the claimed a method of forming an image sensor integrated chip structure particularly characterized by a height of the isolation structure varies at different lateral locations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891