DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 11/21/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-34 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2018/0233528) by Na et al (“Na”).
Regarding claim 15, Na discloses in FIGs. 1-4B & 9A-C and related text, e.g., A method, comprising:
providing a semiconductor substrate (FIG. 1, 108 is the closest match; that whole layer is the substrate);
implanting (meaning, “putting dopants into substrate”; inherent, since FIG. 4A, shows multiple regions being formed in substrate), via a first surface of the semiconductor substrate (FIG. 4A, surface that has 416 on it), a first dopant to create a plurality of first light-absorption regions (regions 412; first dopant is “n-type dopant”; plurality is shown in FIGs. 1 & 2) in the semiconductor substrate for a first light wavelength band (it is a “visible light” pixel);
etching, via the first surface of the semiconductor substrate, a plurality of cavities in the semiconductor substrate (“plurality” of regions are taught in FIGs. 1 & 2; not shown in embodiment of FIG. 4A; its equivalent regions (431/433) are formed on top the surface of substrate instead, and they are on second surface too; the first deficiency is fixed in the embodiments of FIGs. 9A-C; Na explicitly shows that while regions can be formed on top of substrate (FIG. 9A, 906 formed on top of 902), they can also be formed inside the substrate (FIG. 9C, 906 is formed inside 902); the second deficiency is fixed in the embodiments of FIG. 5; while FIG. 4A has the regions of “visible light” and “NIR light” on opposite surfaces of substrate, embodiment of FIG. 5 shows them on the same side (first surface); lastly, in par. 278, Na specifically states that the various embodiments may be combined, features can be added or omitted; hence, per Na’s explicit instructions: “etching” is shown in embodiment of FIG. 9B, and the process steps are shown in FIGs. 18A-D; the same side regions being on the same side of substrate (first side) are shown in FIG. 5; the obviousness of such combinations is explicitly authorized by Na in par. 278);
filling the plurality of cavities with a semiconductor material different from the semiconductor substrate (see par. 80; the entire point of Na’s invention is creating Germanium or Silicon-Germanium regions in combination with Silicon substrate; thus meeting limitations); and
implanting (meaning, “putting dopants into substrate”; inherent, since FIG. 4A, shows multiple regions being formed in substrate), in each of the plurality of cavities filled with the semiconductor material, a second dopant to create a plurality of second light-absorption regions in the semiconductor substrate for a second light wavelength band different from the first light wavelength band (FIG. 4A, 431; second dopant being “p-type”; the “second … band” being “NIR” [Wingdings font/0xE0] near infrared light).
Na does not disclose all the limitations in a single embodiment (he teaches them across multiple embodiments).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Na with all the limitations in a single embodiment, since Na explicitly authorizes combination of embodiments in par. 278 of his specification).
Regarding claim 16, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., substantially the entire claimed structure as recited in above claims, including further comprising:
forming, over the first surface of the semiconductor substrate, each of a plurality of gate structures (416 & 426) proximate a corresponding one of the plurality of first light-absorption regions.
Na does not explicitly state “forming, … after implanting the first dopant”.
In fact, Na is silent on the order in which regions and gates are formed.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Na with “forming, … after implanting the first dopant”, since both method of forming the regions and gates (first regions, and then gates, OR first gates, and then regions) are notoriously well-known in the art, and a POSITA would have chosen whichever they considered more advantageous for their specific manufacturing process.
Regarding claim 17, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
forming, over the first surface of the semiconductor substrate after implanting the second dopant, an insulating structure (inherent; one does not leave the surface of substrate where the gates are uncovered; hence, “an insulating structure” is inherent, especially, in light of the further limitations); and forming a plurality of connections through the insulating structure to the plurality of gate structures (see FIG. 4A; connections 417 & 427 are shown; hence, there is wiring; hence, there is an “insulating structure” which contains said wiring), a plurality of locations on the semiconductor substrate proximate the plurality of gate structures (see FIGs. 24A-C for the full list of all the connections between various objects in as single local circuit; also, see 418 & 428), and the plurality of second light-absorption regions (see FIGs. 24A-C).
Regarding claim 18, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein:
each of the plurality of second light-absorption regions is configured as one of a plurality of second photodiodes for the second light wavelength band (specifically, NIR); and for each of the plurality of second photodiodes: at least a first one of the plurality of connections is configured as an anode; and at least a second one of the plurality of connections is configured as a cathode (see FIGs. 24A-C; photodiode is shown to have an anode and cathode connections).
Regarding claim 19, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein:
each of the plurality of first light-absorption regions, in connection with the semiconductor substrate, is configured as one of a plurality of first photodiodes for the first light wavelength band (specifically, visible light).
Regarding claim 20, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
coupling, to a second surface of the semiconductor substrate opposite the first surface, a plurality of micro-lenses (see FIG. 1; “interconnect 106” is on one side of “sensors 108” – “first side” in FIG. 4A; the “lens 112” is on the second side of “sensors 108”; thus meeting limitations), each of the plurality of micro-lenses being aligned, in a plan view of the semiconductor substrate, with a corresponding one of the plurality of first light-absorption regions or a corresponding one of the plurality of second light- absorption regions (see FIG. 1; “visible light” regions (B/G/R) are aligned; also, “near infrared (NIR) is also aligned).
Regarding claim 21, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., substantially the entire claimed structure as recited in above claims, including a method of forming an integrated circuit light sensor device, the method comprising:
performing a first implantation process to form a first doped region in a semiconductor substrate (see claim 15), the semiconductor substrate comprising a first semiconductor (see claim 15; “silicon”), the first doped region and the semiconductor substrate forming a first p-n junction for sensing visible light photons (the 413 part of substrate forms p-n junction with “first doped region” 412; thus meeting limitations); and
etching the semiconductor substrate beside the first doped region to form a first recess in the semiconductor substrate (see claim 15);
depositing a semiconductor layer comprising a second semiconductor, different than the first semiconductor, in the first recess (see claim 15); and
performing a second implantation process to form a second doped region (see claim 15) in the semiconductor layer, the second doped region and the semiconductor layer forming a second p-n junction for sensing infrared photons (a junction is formed and the photodiode is present).
Na does not disclose a “p-n junction”. Na instead teaches a “p-i-n junction”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Na with “p-n junction”, since both types of junctions (p-n and p-i-n) are notoriously well-known to be useful in creation of NIR photodiodes, each with their own advantages and disadvantages, thus allowing POSITA to choose which is more important in a particular design.
Examiner’s Note: as support of Examiner’s assertion above, a quick and NOT in-depth search of prior art for p-n and p-i-n junctions in NIR, resulted in over 200 results (hence, “notoriously well known”), with the following one being a typical result. As a matter of a state of prior art, see US-2002/0089729, dated 2002 (old; hence, “notoriously well known”), pars. 16 & 18. They make clear that each type of junction is known to have its advantages. One is easier to manufacture, and the other is higher performance. Hence, choosing one over the other, is a matter of preference, as far which one a particular designer finds more important in a given semiconductor design.
Regarding claim 22, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
forming a third doped region in the semiconductor substrate, the third doped region and the semiconductor substrate forming a third p-n junction for sensing visible light photons, wherein the second doped region is directly between the first doped region and the third doped region (see FIG. 1; if one considers the “R” pixel to be related to “first region”, and “NIR” pixel to be “second region”, then the equivalent of “first region” for the “B” pixel would be the “third region”; thus meeting limitations).
Regarding claim 23, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
forming a first filter structure (“filters 110”; the “R” portion, for example) directly over the first doped region;
forming a second filter structure (“filters 110”; the “NIR” portion) directly over the second doped region; and
forming a third filter structure (“filters 110”; the “B” portion, for example) directly over the third doped region,
wherein the first filter structure is configured to pass photons of a first color of visible light (“red” for example) and block photons of a second color of visible light, different than the first color (it passes only red; hence, blocks every other light; hence, meeting limitations), wherein the third filter structure is configured to pass photons of the second color of visible light (“blue” for example) and block photons of the first color of visible light (it passes only blue; hence, blocks every other light; hence, meeting limitations), and wherein the second filter structure is configured to pass infrared photons (“NIR”; thus meeting limitations).
Regarding claim 24, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
etching the semiconductor substrate beside the third doped region to form a second recess in the semiconductor substrate; depositing the semiconductor layer in the first recess; and forming a fourth doped region in the semiconductor layer, the fourth doped region and the semiconductor layer forming a fourth p-n junction for sensing infrared light photons (all the same as in claims above, but for a different NIR pixel), wherein the third doped region is directly between the second doped region and the fourth doped region (see FIG. 2; it shows each of “R/G/B” being between 2 different NIR pixels; thus meeting limitations).
Regarding claim 25, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein a bottom of the first doped region (FIG. 4A, deep region 412) is below a bottom of the second doped region (FIG. 4A, shallow region 431; in a combined device, where the regions are all on the same side, the limitations are met).
Regarding claim 26, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein the bottom of the second doped region is spaced over a bottom of the semiconductor layer (431 is over substrate; see FIG. 10D for better visual example, with the region being on “first side”; 1031 is over bottom of 902).
Regarding claim 27, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
forming a gate electrode over the first doped region (see claim 16);
forming a first contact contacting the gate electrode; forming a second contacting the second doped region (note: something is wrong with wording here; please correct); and forming a third contact contacting the semiconductor layer (note: “the semiconductor layer” appears to be wrong; as far as various contacts, best seen in FIG. 5, which shows electrical connections to various elements and also see FIGs. 24A-C).
Regarding claim 28, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein the semiconductor substrate comprises silicon, and wherein the semiconductor layer comprises germanium (see claim 15).
Regarding claim 29, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., a method of forming an integrated circuit light sensor device, the method comprising:
forming a first doped region having a first doping type in a semiconductor substrate (see claim 15), the semiconductor substrate comprising a first semiconductor and having a second doping type, different than the first doping type (see claim 15, and FIG. 4A), the first doped region and the semiconductor substrate forming a first photodetector for detecting photons in a first wavelength band (see claims 15 and 21); and
depositing a semiconductor layer comprising a second semiconductor, different than the first semiconductor, beside the first doped region, the semiconductor layer having the second doping type (see claim 15); and
forming a second doped region having the first doping type in the semiconductor layer, the second doped region and the semiconductor layer forming a second photodetector for detecting photons in a second wavelength band (see claims 15 & 21).
Regarding claim 30, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
etching the semiconductor substrate to form a first trench in the semiconductor substrate on a first side of the first doped region, wherein a first portion of the semiconductor layer is deposited in the first trench (first NIR being formed, as shown in FIG. 2).
Regarding claim 31, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., further comprising:
etching the semiconductor substrate to form a second trench in the semiconductor substrate on a second side of the first doped region; and depositing a second portion of the semiconductor layer in the second trench (second NIR being formed, as shown in FIG. 2), wherein the first doped region is directly between the first portion and the second portion of the semiconductor layer (see claim 24).
Regarding claim 32, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein, in a plan view, the first photodetector is one photodetector of a two-by-two array of photodetectors for detecting photons the first wavelength band (see FIG. 2; there are 4 “R” pixels in 2-by-2 array), and wherein the second photodetector is disposed in a center of the two-by-two array (see FIG. 2; there is an “NIR” pixel in the middle of 2-by-2 “R” array).
Regarding claim 33, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein a width of the semiconductor layer is greater than a width of the first doped region (such arrangement of parts is shown in FIG. 5; 531/533 is wider than 512; hence, such arrangement of parts is at least obvious in light of Na’s explicit teachings).
Regarding claim 34, Na disclose in FIGs. 1-4B & 9A-C and related text, e.g., wherein the first wavelength band comprises a visible light wavelength band, and wherein the second wavelength band comprises an infrared light wavelength band (as discussed in various claims above).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
03/06/26
/Mounir S Amer/Primary Examiner, Art Unit 2818