DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-23, 25-33 & 35-36 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2018/0233528) by Na et al (“Na”) in view of (US-2022/0165779) by Hsieh et al (“Hsieh”).
Regarding claim 15, Na discloses in FIGs. 1-4B & 9A-C and related text, e.g., A method, comprising:
providing a semiconductor substrate (FIG. 1, 108 is the closest match; that whole layer is the substrate);
implanting (meaning, “putting dopants into substrate”; inherent, since FIG. 4A, shows multiple regions being formed in substrate), via a first surface of the semiconductor substrate (FIG. 4A, surface that has 416 on it), a first dopant to create a plurality of first light-absorption regions (regions 412; first dopant is “n-type dopant”; plurality is shown in FIGs. 1 & 2) in the semiconductor substrate for sensing light in a visible light wavelength band (it is a “visible light” pixel);
etching, via the first surface of the semiconductor substrate, a plurality of cavities in the semiconductor substrate (“plurality” of regions are taught in FIGs. 1 & 2; not shown in embodiment of FIG. 4A; its equivalent regions (431/433) are formed on top the surface of substrate instead, and they are on second surface too; the first deficiency is fixed in the embodiments of FIGs. 9A-C; Na explicitly shows that while regions can be formed on top of substrate (FIG. 9A, 906 formed on top of 902), they can also be formed inside the substrate (FIG. 9C, 906 is formed inside 902); the second deficiency is fixed in the embodiments of FIG. 5; while FIG. 4A has the regions of “visible light” and “NIR light” on opposite surfaces of substrate, embodiment of FIG. 5 shows them on the same side (first surface); lastly, in par. 278, Na specifically states that the various embodiments may be combined, features can be added or omitted; hence, per Na’s explicit instructions: “etching” is shown in embodiment of FIG. 9B, and the process steps are shown in FIGs. 18A-D; the same side regions being on the same side of substrate (first side) are shown in FIG. 5; the obviousness of such combinations is explicitly authorized by Na in par. 278);
filling the plurality of cavities with a semiconductor material different from the semiconductor substrate (see par. 80; the entire point of Na’s invention is creating Germanium or Silicon-Germanium regions in combination with Silicon substrate; thus meeting limitations); and
implanting (meaning, “putting dopants into substrate”; inherent, since FIG. 4A, shows multiple regions being formed in substrate), in each of the plurality of cavities filled with the semiconductor material, a second dopant to create a plurality of second light-absorption regions in the semiconductor substrate for sensing light in an infrared light wavelength band (FIG. 4A, 431; second dopant being “p-type”; the “second … band” being “NIR” [Wingdings font/0xE0] near infrared light).
Na does not disclose all the above limitations in a single embodiment (he teaches them across multiple embodiments).
Na also does not disclose “wherein a plurality of the second light-absorption regions collectively surround one of the first light-absorption regions in a closed and contiguous path”.
Hsieh discloses in FIG. 3 and related text, e.g., “wherein a plurality of the second light-absorption regions (see arrangement 305, pixel 202; “NIR Pixel Sensor”) collectively surround one of the first light-absorption regions (nine different 204’s are shown (visible light Pixel Sensors of various colors); each and every one of them is meeting the limitations) in a closed and contiguous path (see FIG. 3, arrangement 305)”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Na with all the limitations being in a single embodiment as taught by Na and with “wherein a plurality of the second light-absorption regions collectively surround one of the first light-absorption regions in a closed and contiguous path” as taught by Hsieh, since Na explicitly authorizes combination of embodiments in par. 278 of his specification and in order to allow for an arrangement of pixels that allows for “NIR pixel sensors to provide high contour sharpness and high low-light performance, and … red pixel sensors, green pixel sensors, and blue pixel sensors to provide a small amount of color saturation”, respectively.
Regarding claim 16, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., substantially the entire claimed structure as recited in above claims, including further comprising:
forming, over the first surface of the semiconductor substrate, each of a plurality of gate structures (416 & 426) proximate a corresponding one of the plurality of first light-absorption regions.
Na and Hsieh do not explicitly state “forming, … after implanting the first dopant”.
In fact, Na and Hsieh are silent on the order in which regions and gates are formed.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Na and Hsieh with “forming, … after implanting the first dopant”, since both method of forming the regions and gates (first regions, and then gates, OR first gates, and then regions) are notoriously well-known in the art, and a POSITA would have chosen whichever they considered more advantageous for their specific manufacturing process.
Regarding claim 17, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming, over the first surface of the semiconductor substrate after implanting the second dopant, an insulating structure (inherent; one does not leave the surface of substrate where the gates are uncovered; hence, “an insulating structure” is inherent, especially, in light of the further limitations); and forming a plurality of connections through the insulating structure to the plurality of gate structures (see FIG. 4A; connections 417 & 427 are shown; hence, there is wiring; hence, there is an “insulating structure” which contains said wiring), a plurality of locations on the semiconductor substrate proximate the plurality of gate structures (see FIGs. 24A-C for the full list of all the connections between various objects in as single local circuit; also, see 418 & 428), and the plurality of second light-absorption regions (see FIGs. 24A-C).
Regarding claim 18, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein:
each of the plurality of second light-absorption regions is configured as one of a plurality of second photodiodes for sensing light in the infrared light wavelength band (specifically, NIR); and
for each of the plurality of second photodiodes:
at least a first one of the plurality of connections is configured as an anode; and
at least a second one of the plurality of connections is configured as a cathode (see FIGs. 24A-C; photodiode is shown to have an anode and cathode connections).
Regarding claim 19, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein:
each of the plurality of first light-absorption regions, in connection with the semiconductor substrate, is configured as one of a plurality of first photodiodes for sensing light in the visible light wavelength band (as discussed above).
Regarding claim 20, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
coupling, to a second surface of the semiconductor substrate opposite the first surface, a plurality of micro-lenses (see FIG. 1; “interconnect 106” is on one side of “sensors 108” – “first side” in FIG. 4A; the “lens 112” is on the second side of “sensors 108”; thus meeting limitations), each of the plurality of micro-lenses being aligned, in a plan view of the semiconductor substrate, with a corresponding one of the plurality of first light-absorption regions or a corresponding one of the plurality of second light- absorption regions (see FIG. 1; “visible light” regions (B/G/R) are aligned; also, “near infrared (NIR) is also aligned).
Regarding claim 21, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., substantially the entire claimed structure as recited in above claims, including a method of forming an integrated circuit light sensor device, the method comprising:
performing a first implantation process to form a first doped region in a semiconductor substrate (see claim 15), the semiconductor substrate comprising a first semiconductor (see claim 15; “silicon”), the first doped region and the semiconductor substrate forming a photodiode of a first pixel for sensing visible light photons (the 413 part of substrate forms photodiode with “first doped region” 412; thus meeting limitations); and
etching the semiconductor substrate beside the first doped region to form a first recess and a second recess in the semiconductor substrate (see claim 15; “second recess” [Wingdings font/0xE0] same region, just in a different pixel, since Na teaches a repeating pattern), wherein the second recess is beside the first recess (in a combined device/method; since Hsieh explicitly teaches that the NIR regions are to be next to each other, as was discussed in above claims; thus meeting limitations);
depositing a first portion of a semiconductor layer comprising a second semiconductor, different than the first semiconductor, in the first recess (see claim 15);
depositing a second portion of a semiconductor layer comprising a second semiconductor in the second recess (same as “first portion”, since Na teaches a repeating pattern); and
performing a second implantation process to form a second doped region (see claim 15) in the first portion of the semiconductor layer and to form a third doped region in the second portion of the semiconductor layer (same logic applied as for the “second doped region”, and as was already discussed above), the second doped region and the semiconductor layer forming a photodiode of a second pixel for sensing infrared photons (a junction is formed and the photodiode is present),
the third doped region and the semiconductor layer forming a photodiode of a third pixel for sensing infrared photons (as was already discussed above [Wingdings font/0xE0] another 202, per Hsieh’s teachings), the third pixel for sensing infrared photons abutting the second pixel for sensing infrared photons and the first pixel for sensing visible light photons (see FIG. 3 of Hsieh, arrangement 305; there are multiple pairs of 202 that abut each other and also abut a 204, thus meeting all limitations).
Na does not disclose a “p-n junction type photodiode” for infrared pixel. Na instead teaches a “p-i-n junction type photodiode” for infrared pixel.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Na with “p-n junction type photodiode”, since both types of photodiodes (p-n and p-i-n) are notoriously well-known to be useful in creation of NIR photodiodes, each with their own advantages and disadvantages, thus allowing POSITA to choose which is more important in a particular design.
Examiner’s Note: as support of Examiner’s assertion above, a quick and NOT in-depth search of prior art for p-n and p-i-n junctions in NIR, resulted in over 200 results (hence, “notoriously well known”), with the following one being a typical result. As a matter of a state of prior art, see US-2002/0089729, dated 2002 (old; hence, “notoriously well known”), pars. 16 & 18. They make clear that each type of junction is known to have its advantages. One is easier to manufacture, and the other is higher performance. Hence, choosing one over the other, is a matter of preference, as far which one a particular designer finds more important in a given semiconductor design.
Regarding claim 22, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming a fourth doped region in the semiconductor substrate, the fourth doped region and the semiconductor substrate forming a photodiode of a fourth pixel for sensing visible light photons, wherein the second doped region is directly between the first doped region and the fourth doped region (see FIG. 3 of Hsieh, arrangement 305; there are multiple examples of such an arrangement).
Regarding claim 23, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming a first filter structure over and aligned with the first doped region and configured to pass visible light photons of a first color of visible light (first of all, see discussion in claim 35, below [Wingdings font/0xE0] same logic applies; for purposes of rejection, this is a filter over “Red Pixel Sensor” of Hsieh);
forming a second filter structure over and aligned with the second doped region and configured to pass infrared photons (same thing as above, but a filter over “NIR Pixel Sensor” of Hsieh); and
forming a third filter structure over and aligned with the third doped region and configured to pass infrared photons, wherein the third filter structure contacts the second filter structure (same thing as above, but a filter is over yet another “NIR Pixel Sensor” of Hsieh; specifically one that directly contacts the previous one).
Regarding claim 25, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein a bottom of the first doped region (FIG. 4A, deep region 412) is below a bottom of the second doped region (FIG. 4A, shallow region 431; in a combined device, where the regions are all on the same side, the limitations are met).
Regarding claim 26, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein the bottom of the second doped region is spaced over a bottom of the semiconductor layer (431 is over substrate; see FIG. 10D for better visual example, with the region being on “first side”; 1031 is over bottom of 902).
Regarding claim 27, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming a gate electrode over (“above”; FIG. 4A, 416 read on it) the first doped region (see claim 16);
forming a first contact contacting the gate electrode (417 connection to “Control Signal” read on “first contact”);
forming a second contact contacting the second doped region (428 reads on “second contact”, since it is electrically contacting the cited region, and participates in “Readout” of the signal from it); and
forming a third contact (427 connection to “Control Signal” reads on “third contact”) contacting (electrically) the first portion of the semiconductor layer and spaced from the second doped region (see FIG. 4A).
Regarding claim 28, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein the semiconductor substrate comprises silicon, and wherein the semiconductor layer comprises germanium (see claim 15).
Regarding claim 29, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., a method of forming an integrated circuit light sensor device, the method comprising:
forming a first doped region having a first doping type in a semiconductor substrate (see claim 15), the semiconductor substrate comprising a first semiconductor and having a second doping type, different than the first doping type (see claim 15, and FIG. 4A), the first doped region and the semiconductor substrate forming a photodetector of a first pixel for detecting visible light photons (see claims 15 and 21); and
depositing a semiconductor layer comprising a second semiconductor, different than the first semiconductor, beside the first doped region, the semiconductor layer having the second doping type (see claim 15); and
forming a second doped region having the first doping type in the semiconductor layer, the second doped region and the semiconductor layer forming a photodetector of a second pixel for detecting infrared photons (see claims 15 & 21), wherein, in a plan view, an area of the second pixel for detecting infrared photons is greater than an area of the first pixel for detecting visible light photons (same logic applies as in claim 15; 202 area is greater than 204 area).
Regarding claim 30, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
etching the semiconductor substrate to form a first trench in the semiconductor substrate on a first side of the first doped region, wherein a first portion of the semiconductor layer is deposited in the first trench (first NIR being formed, as shown in FIG. 2).
Regarding claim 31, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
etching the semiconductor substrate to form a second trench in the semiconductor substrate on a second side of the first doped region; and depositing a second portion of the semiconductor layer in the second trench (second NIR being formed, as shown in FIG. 2), wherein the first doped region is directly between the first portion and the second portion of the semiconductor layer (see claim 24).
Regarding claim 32, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein, in the plan view, the first pixel is one pixel of a two-by-two array of pixels for detecting visible light photons (see FIG. 3of Hsieh, arrangement 305; any 4 of the adjacent 204’s form a two-by-two array), and wherein the second pixel is disposed in a center of the two-by-two array (a 202 that is in the middle of the above two-by-two array).
Regarding claim 33, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., wherein a ratio of a width of the second pixel to a width of the first pixel is at least 1.5:1 (see FIG. 3 of Hsieh, arrangement 305; the ratio of width of 202 to the width of 204 is mathematically necessarily meets the limitations).
Regarding claim 35, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming a first filter structure over and aligned with the first doped region and configured to pass visible light photons of a first color of visible light (par. 92; “the optical signal 408 may be filtered by a wavelength filter not shown in this figure, such as a filter in the filter layer 110 as described in reference to FIG. 1”); and
forming a second filter structure over and aligned with the second doped region and configured to pass infrared photons (par. 96; “the optical signal 406 may be filtered by a wavelength filter not shown in this figure, such as an NIR filter in the filter layer 110 as described in reference to FIG. 1”), wherein, in the plan view, an area of the second filter structure is greater than an area of the first filter structure (by definition, per Hsieh’s teachings in FIG. 3, arrangement 305 (which shows the relative sizes of pixels, and therefore of filters), and related text in pars. 223-225 that also discusses the details of filter implementation).
Regarding claim 36, the combined device of Na and Hsieh disclose in cited figures and related text, e.g., further comprising:
forming a third doped region having the first doping type in the semiconductor layer, the third doped region and the semiconductor layer forming a photodetector of a third pixel for detecting infrared photons (same type of doped region, as in claim 29, for “second doped region”, since Na teaches a repeating pattern of pixels), wherein, in the plan view, a perimeter of the third pixel for detecting infrared photons adjoins a perimeter of the second pixel for detecting infrared photons (this is shown in FIG. 3 of Hsieh, arrangement 305; various 202’s adjoin their perimeters, just as claim requires).
Response to Arguments
Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/29/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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