DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8,21-32 in the reply filed on 11/10/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear at all what applicant is implying by the first end, and how it is related to the two SID regions?
Claims 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. the limitations “the low-resistance section is formed to extend from a first end to a second end in a direction from the first transistor to the second transistor; and the low-resistance section is formed at a distance (Di) between the first end and the two SID regions along the second direction, and a ratio of Di to Wo (Di/Wo) is at least 3” it is not clear what applicant is talking about here and how all theses elements are related to each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,5-8, 21-23,25-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sue et al (US Pub No. 20170346490), in view of Wu et al (US Pub No. 20200135579).
With respect to claim 1, Sue et al discloses ; a first circuit region (AB left,Fig.3) and a second circuit region (AB right) and extending in a first direction (in the x direction); a first transistor located in the first circuit region (A,Fig.2-3), the first transistor comprising a first gate electrode extending in a second direction (Fig.2, by default in y direction), the second direction being substantially perpendicular to the first direction ( x and y directions are perpendicular to each other); a second transistor located in the second circuit region (Fig.2,3), the second transistor comprising a second gate electrode (Fig.2,3) extending in the second direction ( by default in the y direction) and aligned with the first gate electrode in the second direction (since they are paralleled with each other they are aligned with each other); interconnecting the first and the second gate electrodes (Fig.2-3). However, Sue et al does not explicitly disclose substrate, and a low-resistance section extending in the second direction, wherein the low-resistance section is substantially aligned with the first and second gate electrodes in the second direction, wherein the first and second gate electrodes have a first width (Wo) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to Wo (W/Wo) is at least 1.1. On the other hand, Wu et al discloses a substrate (50,Fig.6A) and the circuitry formed on the substrate (74,80,78), a low-resistance section (78,Fig.6A,7A) extending in the second direction (in the y direction,Fig.7A), wherein the low-resistance section is substantially aligned with the first and second gate electrodes in the second direction (for example 78 on the right is aligned with both 74 which is under it and the nearest 74 to the left,Fig.7A), wherein the first and second gate electrodes have a first width (Wo) along the first direction (Fig.7A), the low-resistance section has a second width (W) along the first direction (78,Fig.7A), and a ratio of W to Wo (W/Wo) is at least 1.1(since 78 is wider than 74,Fig.7A). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 2, wherein the ratio of W to Wo (W/Wo) is from 1.1 to 5. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 3, wherein the low-resistance section has a length (L) along the second direction, and a ratio of L to Wo (L/Wo) is at least 10. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it would have been obvious to do so as a design choice.
With respect to claim 5, Sue et al does not explicitly disclose wherein: the first and second gate electrodes comprise a first material having a first resistivity; and the low-resistance section comprises a second material having a second resistivity, wherein the second resistivity is less than the first resistivity. On the other hand, Wu et al discloses that the gate electrode can be made from TiN (Para 29), and the contact can be made from copper (Para 32). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Sue et al according to the teachings of the Wu et al such that the gate electrode is made from TiN and the contact is made from copper (copper’s resistivity is way lesser than TiN resistivity),
With respect to claim 6, Sue et al in view of Wu et al discloses wherein each of the first and second gate electrodes further comprises: a gate dielectric layer (70) disposed on and in contact with a channel region (Fig.6b, para 29) of the corresponding transistor; and a gate metal layer disposed on the gate dielectric layer (Fig.6A-B).
With respect to claim 7, Sue et al discloses wherein the first circuit region is located in a first active region (left of 13,Fig.4), the second circuit region is located in a second active region (right of 13), and the low-resistance section extends across a boundary between the first active region and the second active region (Fig.3,4).
With respect to claim 8, Sue et al does not explicitly disclose the limitations of the claims 8. On the other hand, Wu et al discloses, further comprising: a first ILD structure (66) comprising a first dielectric material (Para 26), wherein the first and second gate electrodes are surrounded by the first ILD structure (Fig.6A); and a second ILD structure (76) comprising a second dielectric material (Para 31), wherein the low- resistance section is surrounded by the second ILD structure (Fig.6A), and wherein the second dielectric material is different from the first dielectric material (the first is BPSG, and the second is USG). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Suet al according to the teachings of the Wu et al such that a first ILD and the second ILD are formed, in order to protect the transistor and the contact during fabrication process.
With respect to claim 21, Sue et al discloses ; forming a first circuit region (AB left,Fig.3) and a second circuit region (AB right) and extending in a first direction (in the x direction); forming a first transistor located in the first circuit region (A,Fig.2-3), the first transistor comprising a first gate electrode extending in a second direction (Fig.2, by default in y direction), the second direction being substantially perpendicular to the first direction ( x and y directions are perpendicular to each other); a second transistor located in the second circuit region (Fig.2,3), forming the second transistor comprising a second gate electrode (Fig.2,3) extending in the second direction ( by default in the y direction) and aligned with the first gate electrode in the second direction (since they are paralleled with each other they are aligned with each other); interconnecting the first and the second gate electrodes (Fig.2-3). However, Sue et al does not explicitly disclose forming a low-resistance section extending in the second direction, wherein the forming is controlled such that the first and second gate electrodes have a first width (Wo) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to Wo (W/Wo) is at least 1.1.. On the other hand, Wu et al discloses forming a low-resistance section extending in the second direction, wherein the forming is controlled such that the first and second gate electrodes have a first width (Wo) along the first direction (Fig.7A), the low-resistance section has a second width (W) along the first direction (Fig.7A), and a ratio of W to Wo (W/Wo) is at least 1.1 (Fig.7A). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 22, wherein the ratio of W to Wo (W/Wo) is from 1.1 to 5. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 23, wherein the low-resistance section has a length (L) along the second direction, and a ratio of L to Wo (L/Wo) is at least 10. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it would have been obvious to do so as a design choice.
With respect to claim 25, Sue et al does not explicitly disclose the limitations of the claims 25. On the other hand, Wu et al discloses, further comprising: forming a first ILD structure (66) comprising a first dielectric material (Para 26), wherein the first and second gate electrodes are surrounded by the first ILD structure (Fig.6A); and forming a second ILD structure (76) comprising a second dielectric material (Para 31), wherein the low- resistance section is surrounded by the second ILD structure (Fig.6A), and wherein the second dielectric material is different from the first dielectric material (the first is BPSG, and the second is USG). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Suet al according to the teachings of the Wu et al such that a first ILD and the second ILD are formed, in order to protect the transistor and the contact during fabrication process.
With respect to claim 26, Wu et al discloses, wherein the second dielectric material has a second dielectric constant (dielectric constant for USG) and the first dielectric material has a first dielectric constant (dielectric constant for BPSG), and the second dielectric constant is lower than the first dielectric constant (for most scenarios USG has a lower dielectric constant than the first dielectric constant).
With respect to claim 27, Sue et al discloses: a substrate; a first circuit region (AB on the left,Fig.3) and a second circuit region (AB on the right,Fig.3); first gate electrode in the first circuit region ( the gate electrode for A on left) and second gate electrode in the second region (the gate electrode for A on right), and interconnection connecting the first and the second gate (31). However, the Sue et al does not explicitly disclose a substrate and the circuitry formed on the substrate, a gate structure extending in a second direction, the gate structure comprising: a first gate electrode located in the first circuit region; a second gate electrode located in the second circuit region; and a low-resistance section interconnecting the first and second gate electrodes, wherein the first and second gate electrodes have a first width (Wo) along a first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to Wo (W/Wo) is at least 1.1. On the other hand, Wu et al discloses a substrate (50,Fig.6A) and the circuitry formed on the substrate (74,80,78), a gate structure (74) extending in a second direction (in the y direction from top view, Fig.7A); the first and second gate electrodes (78 left is the first gate, and the gate is in middle), and a low-resistance section (78) connected to the first and second electrode (Fig.6A); wherein the first and second gate electrodes have a first width (Wo) along a first direction (in the x direction from the top view,Fig.7A), the low-resistance section has a second width (W) along the first direction (Fig.6A, Fig.7A) , and a ratio of W to Wo (W/Wo) is at least 1.1 (because the low resistance section has a longer width). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 28,Sue et al does not explicitly disclose the limitations of the claims 28 the limitations of the claims 28. On the other hand, Wu et al discloses, further comprising: a first ILD structure (66) comprising a first dielectric material (Para 26), wherein the first and second gate electrodes are surrounded by the first ILD structure (Fig.6A); and a second ILD structure (76) comprising a second dielectric material (Para 31), wherein the low- resistance section is surrounded by the second ILD structure (Fig.6A), and wherein the second dielectric material is different from the first dielectric material (the first is BPSG, and the second is USG). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Suet al according to the teachings of the Wu et al such that a first ILD and the second ILD are formed, in order to protect the transistor and the contact during fabrication process.
With respect to claim 29, Wu et al discloses, wherein the second dielectric material has a second dielectric constant (dielectric constant for USG) and the first dielectric material has a first dielectric constant (dielectric constant for BPSG), and the second dielectric constant is lower than the first dielectric constant (for most scenarios USG has a lower dielectric constant than the first dielectric constant).
With respect to claim 30, wherein the ratio of W to Wo (W/Wo) is from 1.1 to 5. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a wider low resistance contact than the gate electrode, in order to increase the contact area, thereby avoiding manufacturing defect.
With respect to claim 31, wherein the low-resistance section has a length (L) along the second direction, and a ratio of L to Wo (L/Wo) is at least 10. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it would have been obvious to do so as a design choice.
With respect to claim 32, Sue et al does not explicitly disclose wherein: the first and second gate electrodes comprise a first material having a first resistivity; and the low-resistance section comprises a second material having a second resistivity, wherein the second resistivity is less than the first resistivity. On the other hand, Wu et al discloses that the gate electrode can be made from TiN (Para 29), and the contact can be made from copper (Para 32). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Sue et al according to the teachings of the Wu et al such that the gate electrode is made from TiN and the contact is made from copper (copper’s resistivity is way lesser than TiN resistivity), because they are common material used in the industry and no new equipment or training is required for the manufacturing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALI NARAGHI/Primary Examiner, Art Unit 2817