DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 11-13, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US Pub. 2021/0399137 A1).
In re claim 1, Wang et al. discloses (figs. 1A-8B) a method of forming a device structure, the method comprising: forming a layer stack comprising a continuous bottom electrode material layer (58), a continuous dielectric layer (54L), and a continuous metal layer (51L); converting [0047-0051] the continuous metal layer into a continuous dielectric metal oxide layer (51L); depositing a continuous semiconductor layer (30; fig. 5) over the continuous dielectric metal oxide layer; and patterning (fig. 6, 7; [0053], the continuous semiconductor layer and the layer stack to form a patterned layer stack including a bottom electrode (58), a dielectric layer (54), a dielectric metal oxide layer (51L), and a semiconductor layer (30).
In re claim 2, Wang et al. discloses (figs. 7A-8B) forming a pair of metallic contact structures (82, 88) to the semiconductor layer such that the pair of metallic contact structures are laterally spaced from each other by a portion of the semiconductor layer.
In re claim 3, Wang et al. discloses (figs. 1A-8; [0047]) converting the continuous metal layer into the continuous dielectric metal oxide layer comprises performing a thermal anneal in an oxidizing ambient.
In re claim 6, Wang et al. discloses (figs. 1A-8B; [0073]) the continuous dielectric layer comprises a doped hafnium oxide layer that is doped with at least one dopant species that is selected from Al, In, Si, Ge, alkaline earth metals, transition metals, and rare-earth metals.
In re claim 9, Wang et al. discloses (figs. 8B) depositing a continuous dielectric capping layer (70) over the continuous semiconductor layer; and patterning the continuous dielectric capping layer into a dielectric capping layer.
In re claim 11, Wang et al. discloses (figs. 1A-8B) a method of forming a device structure, the method comprising: forming a continuous dielectric layer (54L; fig. 2) over a substrate; forming a continuous metal layer (51L; fig. 3) by performing a physical vapor deposition process [0046]; converting the continuous metal layer into a continuous dielectric metal oxide layer [0047]; depositing a continuous semiconductor layer (30; fig. 5) over the continuous dielectric metal oxide layer; and patterning (figs. 6, 7; [0053] the continuous semiconductor layer, the continuous dielectric metal oxide layer, and the continuous dielectric layer to form a patterned layer stack including a dielectric layer (54L), a dielectric metal oxide layer (51L), and a semiconductor layer (30).
In re claim 12, Wang et al. discloses (figs. 7A-8B) forming a pair of metallic contact structures (82, 88) through the semiconductor layer such that the pair of metallic contact structures are laterally spaced from each other by a portion of the semiconductor layer.
In re claim 13, Wang et al. discloses (figs. 1A-8; [0047]) converting the continuous metal layer into the continuous dielectric metal oxide layer comprises performing a thermal anneal in an oxidizing ambient.
In re claim 16, Wang et al. discloses (figs. 1A-8B) method of forming a device structure, the method comprising: forming a layer stack comprising a continuous bottom electrode material layer (58), a continuous dielectric layer (54L), and a continuous metal layer (51L; [0047)]; converting the continuous metal layer into a continuous dielectric metal oxide layer (51L); depositing a continuous semiconductor layer (30; fig. 5) over the continuous dielectric metal oxide layer; patterning (fig. 6, 7; [0053], the continuous semiconductor layer and the layer stack to form a patterned layer stack including a bottom electrode (58), a dielectric layer (54), a dielectric metal oxide layer (51L), and a semiconductor layer (30), forming a pair of metallic contact structures (82,88; fig. 7A-8B) on the dielectric metal oxide layer such that the pair of metallic contact structures are laterally spaced apart by a portion of the dielectric metal oxide layer.
In re claim 17, Wang et al. discloses (figs. 1A-8B) forming a memory-level dielectric layer (70) around the patterned layer stack; and forming via-level dielectric layer over the patterned layer stack and the memory-level dielectric layer, wherein the pair of metallic contact structures are formed through the via-level dielectric layer.
In re claim 18, Wang et al. discloses ([0056-58]) forming a pair of via cavities through the via-level dielectric layer and the semiconductor layer; and depositing at least one metallic material in the pair of via cavities and removing excess portions of the at least one metallic material from outside the pair of via cavities, wherein remaining portions of the at least one metallic material filling the pair of via cavities constitute the pair of metallic contact structures.
In re claim 20, Wang et al. discloses (figs. 1A-8B; [0051]) depositing at least one continuous interfacial dielectric metal oxide layer (52L) over the continuous dielectric layer prior to, or after, formation of the continuous dielectric metal oxide layer; and increasing an oxygen-to-metal ratio in the at least one continuous interfacial
dielectric metal oxide layer by incorporating additional oxygen atoms into the at least one continuous interfacial dielectric meal oxide layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 7, 10, 14, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Pub. 2021/0399137 A1) as applied to claims 1, 11, and 16 above, and further in view of Wu et al. (US Pub. 2021/0376164 A1).
In re claims 4, 5, 7, 14, and 15, Wang shows all of the elements of the claims except processes for converting the metal layer. However, these are well known processes used in the art of semiconductor devices for provide oxide layers.
In re claim 10, Wang does not specifically disclose forming field effect transistors over a substrate; forming first metal interconnect structures embedded in first dielectric material layers and electrically connected to a respective node of the field effect transistors; forming a connection-via-level dielectric layer over the first metal interconnect structures; and forming a connection via structure contacting a top surface of one of the first metal interconnect structures in the connection-via-level dielectric layer, wherein the bottom electrode is formed on a top surface of the connection via structure. Wu discloses (figs. 1-7) the method of forming a complete device comprising forming field effect transistors (750) over a substrate; forming first metal interconnect structures (628, 638, 648, etc.) embedded in first dielectric material layers (620, 630, etc,) and electrically connected to a respective node (732, 738) of the field effect transistors; forming a connection-via-level dielectric layer (102, 190) over the first metal interconnect structures; and forming a connection via structure contacting a top surface of one of the first metal interconnect structures in the connection-via-level dielectric layer, wherein the bottom electrode (120) is formed on a top surface of the connection via structure. With this configuration, a complete semiconductor device is formed. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the semiconductor device of Wang by forming interconnections between the semiconductor device and lower transistors as taught by Wu to form a complete semiconductor device.
Allowable Subject Matter
Claims 8 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin (US Pub. 2022/0352379 A1), Naylor (US Pub. 2021/0083122 A1), Fukase (US Pub. 2015/0048359 A1), Huang (US 12,089,415 B2), Yamazaki (WO-2021090116-A1), and Xu (CN-115360233-A) also show various elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW E WARREN/Primary Examiner, Art Unit 2815
Prosecution Insights