DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 21 July 2026 has been entered.
Response to Amendment
The Office acknowledges receipt on 21 July 2026 of Applicants’ amendments in which claims 1, 9, and 21 are amended, claims 2, 6, and 7 are cancelled, and claims 27-29 are newly added.
Response to Arguments
Applicants’ arguments with respect to independent claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue in the first and third paragraphs of page 11 and with respect to independent claim 9 that Cai and Furukawa do not teach the subject matter newly added to claim 9 of: “the patterned dielectric layer … covering and interfacing the upper portion of the gate structure which is protruded upwardly from the spacer.” Claim 9 is rejected over the combined teachings of Cai and Furukawa. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Applicants acknowledge Cai teaches in Fig. 2C the recited subject matter of “the patterned dielectric layer [(118)] … covering and interfacing the upper portion of the gate structure [(108, 110)]” {see Applicants’ Arguments on page 11, third paragraph}. Regarding the remaining subject matter of “the gate structure which is protruded upwardly from the spacer,” Furukawa teaches in Fig. 10 a gate structure (730, 1240) which is protruded upwardly from a spacer (1550) {col. 6, ll. 36-52}. The motivation for modifying Cai’s method based on the teachings of Furukawa is identified below with respect to the rejection of claim 9.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 29 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 29 recites “a bottommost of the dielectric contact spacer directly contacts a lateral surface of the patterned dielectric layer,” which is indefinite because its meaning is indiscernible. Specifically, the claim lacks the noun-phrase intended to be modified by “bottommost.” Bottommost cannot modify the “dielectric contact spacer” because only one “dielectric contact spacer” is recited. Additionally, bottommost cannot be intended to modify a surface of the “dielectric contact spacer” because the application lacks support for the recited subject matter using this interpretation. Still further, “the dielectric contact spacer” lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claims, this will be interpreted as “the dielectric contact spacer layer directly contacts a lateral surface of the patterned dielectric layer.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al. (US20150249036A1) in view of Furukawa et al. (US6531724B1), Lim et al. (US6399451B1) and Zhu et al. (US20080173941A1).
Regarding claim 1, Cai teaches a method for manufacturing a semiconductor device, comprising:
forming a transistor (104) on a semiconductor substrate (102), the transistor (104) including a gate structure (108/[108, 110]) and a source/drain structure (114) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102), the patterned dielectric layer (118) including an opening (120) extending from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114) {Figs. 2B, 2C; [0036-0037]};
forming a dielectric contact spacer (122) to cover a sidewall of the opening (120) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108/[108, 110]) by the dielectric contact spacer (122) and the patterned dielectric layer (118) {Fig. 2F; [0041]}.
Cai does not teach over-etching the spacer material such that a spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer.
In an analogous art, Furukawa teaches in Fig. 10 over-etching the spacer material such that a spacer (1550) partially covers a lateral surface of a gate structure (1240) to expose an upper portion of the gate structure (1240) from the spacer (1550) {col. 6, ll. 36-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa – such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52. Paragraph [0029] of the instant PG-Pub discloses that over-etching removes the spacer material from a portion (e.g., upper portion) of the side surfaces of the gate structures. Furukawa illustrates this feature in Fig. 10.
Cai does not teach the spacer is formed by depositing a spacer material layer to cover the gate structure and the semiconductor substrate, such that the spacer partially covers the lateral surface of the gate structure to expose the upper portion of the gate structure from the spacer, wherein exposure of the upper portion of the gate structure from the spacer occurs before formation of the source/drain structure.
Lim teaches in Figs. 2, 3, and 7 a spacer (108’) is formed by depositing a spacer material layer (108) to cover a gate structure (102, 104) and a semiconductor substrate (100), such that the spacer (108’) partially covers a lateral surface of the gate structure (102, 104) to expose an upper portion of the gate structure (102, 104) from the spacer (108’), wherein exposure of the upper portion of the gate structure (102, 104) from the spacer (108’) occurs before formation of a source/drain structure (114) {col. 2, l. 52, through col. 3, l. 37}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the teachings of Lim, to achieve the above-identified subject matter, because applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E). Furthermore, the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Cai does not teach the etching is an anisotropic etching process.
In an analogous art, Zhu teaches in paragraph [0008] that isotropic (non-directional) and anisotropic (directional) etching are alternatives in which the former achieves uniform etching in all directions to provide rounded geometries after etching and the latter achieves directional etching to provide sharp/precise geometries after etching. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa and Lim based on the teachings of Zhu, to achieve, the above-identified subject matter, to acquire a more precise geometry of the etched spacer. Moreover, applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 3, Cai as modified by Furukawa, Lim, and Zhu teaches the method as claimed in claim 1, and Cai further teaches wherein the upper portion of the gate structure (108/[108, 110]) is isolated from the conductive contact (124) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 4, Cai as modified by Furukawa, Lim, and Zhu teaches the method as claimed in claim 1, and Cai further teaches wherein the dielectric contact spacer (122) has a thickness which decreases gradually along a direction from the top surface of the source/drain structure (114) to the top surface of the patterned dielectric layer (118) {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 5, Cai as modified by Furukawa, Lim, and Zhu teaches the method as claimed in claim 4, and Cai further teaches wherein the dielectric contact spacer (122) includes an upper portion proximate to the top surface of the patterned dielectric layer (118), a lower portion proximate to the top surface of the source/drain structure (114), and an intermediate portion disposed between the upper portion and the lower portion, the lower portion having a thickness, the intermediate portion having a thickness less than the thickness of the lower portion, the upper portion having a thickness less than the thickness of the intermediate portion {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 8, Cai as modified by Furukawa, Lim, and Zhu teaches the method as claimed in claim 1, and Cai further teaches wherein the dielectric contact spacer (122) is formed from a dielectric contact spacer layer which is made of a low-k dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbide, an extreme low-k dielectric material, or combinations thereof {Fig. 2E; [0040], dielectric contact spacer (122) is a low-k material made of silicon-carbon-nitride (SiCN)}.
Claim(s) 9-14 and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Furukawa.
Regarding claim 9, Cai as modified by Furukawa teaches a method for manufacturing a semiconductor device, comprising:
forming a transistor (104) on a semiconductor substrate (102), the transistor (104) including a gate structure (108, 110), a spacer (112) covering a lateral surface of the gate structure (108, 110), and a source/drain structure (114) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102), the patterned dielectric layer (118) including an opening (120) that extends from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114), and [the patterned dielectric layer] covering and interfacing the upper portion of the gate structure (108, 110) {Figs. 2B, 2C; [0036-0037]};
conformally depositing a dielectric contact spacer layer (layer of 122) on the patterned dielectric layer (118) and the source/drain structure (114) {Fig. 2E; [0040]};
anisotropically etching the dielectric contact spacer layer (layer of 122) to form a dielectric contact spacer (122) covering a sidewall of the opening (120) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108, 110) by the dielectric contact spacer (122) and the patterned dielectric layer (118) {Fig. 2F; [0041]}.
Cai does not teach the spacer partially covering a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer, wherein the gate structure which is protruded upwardly from the spacer.
In an analogous art, Furukawa teaches in Fig. 10 a spacer (1550) partially covering a lateral surface of a gate structure (730, 1240) to expose an upper portion of the gate structure (730, 1240) from the spacer (1550) , wherein the gate structure (730, 1240) which is protruded upwardly from the spacer (1550) {col. 6, ll. 36-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa, to achieve the above-identified subject matter, to allow a dielectric layer to form around the corners of a gate conductor for better encapsulation. Furukawa col. 6, ll. 36-52.
Regarding claim 10, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the upper portion of the gate structure (108, 110) exposed from the spacer (Cai’s 112 as modified by Furukawa) is covered by the patterned dielectric layer (118) after formation of the patterned dielectric layer (118) {Figs. 2A, 2B; [0034]}.
Regarding claim 11, Cai as modified by Furukawa teaches the method as claimed in claim 10, and Cai further teaches wherein the upper portion of the gate structure (108, 110) is isolated from the conductive contact (124) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 12, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer layer (layer of 122) is made of a low-k dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbide, an extreme low-k dielectric material, or combinations thereof {Fig. 2E; [0040], dielectric contact spacer layer (layer of 122) is a low-k material made of silicon-carbon-nitride (SiCN)}.
Regarding claim 13, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer layer (layer of 122) has a thickness ranging from 2 nm to 300 nm {Fig. 2E; [0040], thickness … of about 3-10 nm}.
Regarding claim 14, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer (122) has a thickness which decreases gradually along a direction from the top surface of the source/drain structure (114) to the top surface of the patterned dielectric layer (118) {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 27, Cai as modified by Furukawa teaches the method as claimed in claim 9, but Cai does not teach wherein the patterned dielectric layer laterally covers the upper portion of the gate structure and directly contacts a lateral surface of the upper portion of the gate structure.
Furukawa teaches in Fig. 10 a patterned dielectric layer (1560) laterally covers an upper portion of a gate structure (730, 1240) and directly contacts a lateral surface of the upper portion of the gate structure (730, 1240) {col. 6, ll. 36-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the further teachings of Furukawa, to achieve the above-identified subject matter, to allow a dielectric layer to form around the corners of a gate conductor for better encapsulation. Furukawa col. 6, ll. 36-52.
Regarding claim 28, Cai as modified by Furukawa teaches the method as claimed in claim 9, but Cai does not teach wherein the gate structure includes a poly gate or a metal gate, and the upper portion of the gate structure protruded upwardly from the spacer is an upper portion of one of the poly gate and the metal gate.
Furukawa teaches in Fig. 10 a gate structure (730, 1240) includes a poly gate or a metal gate, and the upper portion of the gate structure (730, 1240) protruded upwardly from the spacer (1550) is an upper portion of one of the poly gate and the metal gate {col. 5, ll. 26-50; col. 6, ll. 37-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the further teachings of Furukawa, to achieve the above-identified subject matter, because only the polysilicon will heat sufficiently to grow a dielectric film … to isolate [the] gate conductor. Furukawa col. 5, ll. 11-25. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 29, as interpreted in view of the indefiniteness rejection, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer layer (layer of 122) directly contacts a lateral surface of the patterned dielectric layer (118) {Fig. 2E; [0040]).
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Furukawa, Chang et al. (US20200395320A1), Lim, and Zhu.
Regarding claim 21, Cai teaches a method for manufacturing a semiconductor device, comprising:
forming a gate structure (108/[108, 110]) on a semiconductor substrate (102) {Fig. 2A; [0033-0034]};
forming a spacer (112) partially covering a lateral surface of the gate structure (108/[108, 110]) {Figs. 2A, 2B; [0034]};
forming a source/drain structure (114) on the semiconductor substrate (102), the source/drain structure (114) being spaced apart from the gate structure (108/[108, 110]) by the spacer (112) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102) to cover the gate structure (108/[108, 110]) and the spacer (112), the patterned dielectric layer (118) being formed with an opening (120) extending from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114) {Figs. 2B, 2C; [0036-0037]};
forming a dielectric contact spacer (122) to cover a sidewall of the opening (120), the dielectric contact spacer (122) extending from the top surface of the patterned dielectric layer (118) to the top surface of the source/drain structure (114) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108/[108, 110]) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F; [0041]},
wherein the portion of the patterned dielectric layer (118) includes a first lateral surface interfacing the dielectric contact spacer (122) {Fig. 2F; [0041]}.
Cai does not teach over-etching the spacer material such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer, wherein the portion of the patterned dielectric layer includes a second lateral surface interfacing the upper portion of the gate structure and the spacer.
Furukawa teaches in Figs. 10 and 16 over-etching the spacer material such that a spacer (1550) partially covers a lateral surface of a gate structure (1240) to expose an upper portion of the gate structure (1240) from the spacer (1550) {col. 6, ll. 36-52}, wherein a portion of a patterned layer (1830) includes a lateral surface interfacing an upper portion of the gate structure (1240) and the spacer (1550). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa – such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer, wherein the portion of the patterned layer includes a second lateral surface interfacing the upper portion of the gate structure and the spacer – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52. Paragraph [0029] of the instant PG-Pub discloses that over-etching removes the spacer material from a portion (e.g., upper portion) of the side surfaces of the gate structures. Furukawa illustrates this feature in Fig. 10.
Cai and Furukawa do not teach expressly that the patterned layer is a dielectric layer; however, Furukawa teaches this layer (1830) is a passivation layer. In an analogous art, Chang teaches in paragraph [0019] that silicon oxide and silicon nitride are both passivation layers and dielectrics (similar to Applicants’ disclosure in paragraph [0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the teachings of Chang – such that Furukawa’s passivation patterned layer is a dielectric (as is Cai’s patterned layer (118)) – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Cai does not teach the spacer is formed before formation of the source/drain structure by depositing a spacer material layer to cover the gate structure and the semiconductor substrate.
Lim teaches in Figs. 2, 3, and 7 a spacer (108’) is formed before formation of a source/drain structure (114) by depositing a spacer material layer (108) to cover a gate structure (102, 104) and a semiconductor substrate (100) {col. 2, l. 52, through col. 3, l. 37}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa and Chang based on the teachings of Lim, to achieve the above-identified subject matter, because applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E). Furthermore, the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Cai does not teach the etching is an anisotropic etching process.
Zhu teaches in paragraph [0008] that isotropic (non-directional) and anisotropic (directional) etching are alternatives in which the former achieves uniform etching in all directions to provide rounded geometries after etching and the latter achieves directional etching to provide sharp/precise geometries after etching. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa, Chang, and Lim based on the teachings of Zhu, to achieve, the above-identified subject matter, to acquire a more precise geometry of the etched spacer. Moreover, applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 22, Cai as modified by Furukawa, Chang, Lim, and Zhu teaches the method as claimed in claim 21, and Cai further teaches wherein formation of the dielectric contact spacer (122) includes:
conformally depositing a dielectric contact spacer layer (layer of 122) on the patterned dielectric layer (118) and the source/drain structure (114) {Fig. 2E; [0040]}; and
etching away horizontal portions of the dielectric contact spacer layer (layer of 122) disposed on the top surface of the patterned dielectric layer (118) and the top surface of the source/drain structure (114) {Fig. 2E; [0040]}.
Regarding claim 23, Cai as modified by Furukawa, Chang, Lim, and Zhu teaches the method as claimed in claim 22, and Cai further teaches wherein the source/drain structure (114) includes a lower portion recessed into the semiconductor substrate (102), and an upper portion interfacing the dielectric contact spacer (122) {Fig. 2F}.
Regarding claim 24, Cai as modified by Furukawa, Chang, Lim, and Zhu teaches the method as claimed in claim 23, and Cai further teaches wherein the spacer (112) is spaced apart from the dielectric contact spacer (122) by the portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 25, Cai as modified by Furukawa, Chang, Lim, and Zhu teaches the method as claimed in claim 24, and Cai further teaches wherein the spacer (112) includes:
a lower portion interfacing the upper portion of the source/drain structure (114) {Fig. 2F}; and
an upper portion spaced apart from the conductive contact (124) by the portion of the patterned dielectric layer (118) and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 26, Cai as modified by Furukawa, Chang, Lim, and Zhu teaches the method as claimed in claim 25, and Cai further teaches wherein
the gate structure (108/[108, 110]) further includes a lower portion disposed below the upper portion of the gate structure (108/[108, 110]) {Fig. 2F};
the lower portion of the gate structure (108/[108, 110]) is spaced apart from the conductive contact (124) by the spacer (112), the portion of the patterned dielectric layer (118), and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}; and
the upper portion of the gate structure (108/[108, 110]) is spaced apart from the conductive contact (124) by the portion of the patterned dielectric layer (118) and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US9076816B2) teaches a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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