DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 7 April 2026 of Applicants’ amendments in which claims 1-3, 9, 10, 21, and 24 are amended.
Response to Arguments
Applicants’ arguments with respect to independent claim(s) 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue in the fourth and fifth paragraphs of page 10 and with respect to independent claim 21 that Cai and Furukawa do not teach the subject matter newly added to the claim whereby “the portion of the patterned dielectric layer includes a first lateral surface interfacing the dielectric contact spacer and a second lateral surface interfacing the upper portion of the gate structure and the spacer.” Amended claim 21 is rejected over the combined teachings of Cai, Furukawa, and Chang. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance: (1) Cai teaches in Fig. 2F and paragraph [0041] a portion of a patterned dielectric layer (118) includes a first lateral surface interfacing a dielectric contact spacer (122) and (2) Furukawa teaches in Figs. 10 and 16 a portion of a patterned layer (1830) includes a second lateral surface interfacing an upper portion of a gate structure (1240) and a spacer (1550). The motivation for modifying Cai’s method based on the teachings of Furukawa is identified below with respect to the rejection of claim 21. Furukawa does not teach expressly that the patterned layer is a dielectric layer; however, Furukawa teaches this layer (1830) is a passivation layer. In an analogous art, Chang teaches in paragraph [0019] that silicon oxide and silicon nitride are both passivation layers and dielectrics (similar to Applicants’ disclosure in paragraph [0020]). And the motivation for modifying Cai’s method as modified by Furukawa based on the teachings of Chang is identified below with respect to the rejection of claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al. (US20150249036A1) in view of Furukawa et al. (US6531724B1).
Regarding claim 1, Cai teaches a method for manufacturing a semiconductor device, comprising:
forming a transistor (104) on a semiconductor substrate (102), the transistor (104) including a gate structure (108/[108, 110]) and a source/drain structure (114) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102), the patterned dielectric layer (118) including an opening (120) extending from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114) {Figs. 2B, 2C; [0036-0037]};
forming a dielectric contact spacer (122) to cover a sidewall of the opening (120) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108/[108, 110]) by the dielectric contact spacer (122) and the patterned dielectric layer (118) {Fig. 2F; [0041]}.
Cai does not teach a spacer partially covering a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer.
In an analogous art, Furukawa teaches in Fig. 10 a spacer (1550) partially covering a lateral surface of a gate structure (1240) to expose an upper portion of the gate structure (1240) from the spacer (1550) {col. 6, ll. 36-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa – such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52.
Cai as modified by Furukawa does not teach wherein exposure of the upper portion of the gate structure from the spacer occurs before formation of the source/drain structure.
However, the: (1) selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result {MPEP 2144.04(IV)(C)} and (2) instant application does not disclose a new or unexpected result achieved by the claimed sequence of performing the process steps.
Regarding claim 3, Cai as modified by Furukawa teaches the method as claimed in claim 1, and Cai further teaches wherein the upper portion of the gate structure (108/[108, 110]) is isolated from the conductive contact (124) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 4, Cai as modified by Furukawa teaches the method as claimed in claim 1, and Cai further teaches wherein the dielectric contact spacer (122) has a thickness which decreases gradually along a direction from the top surface of the source/drain structure (114) to the top surface of the patterned dielectric layer (118) {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 5, Cai as modified by Furukawa teaches the method as claimed in claim 4, and Cai further teaches wherein the dielectric contact spacer (122) includes an upper portion proximate to the top surface of the patterned dielectric layer (118), a lower portion proximate to the top surface of the source/drain structure (114), and an intermediate portion disposed between the upper portion and the lower portion, the lower portion having a thickness, the intermediate portion having a thickness less than the thickness of the lower portion, the upper portion having a thickness less than the thickness of the intermediate portion {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 6, Cai as modified by Furukawa teaches the method as claimed in claim 5, and Cai further teaches wherein a difference between the thickness of the lower portion and the thickness of the intermediate portion ranges from 0.1 nm to 10 nm {Fig. 2E; [0040]}.
Examiner’s Note: Cai teaches in paragraph [0040] the low-k sidewall spacers 122A and 122B may have a thickness at its base of about 3-10 nm. And Cai’s Fig. 2E illustrates that the thickness of each spacer (122) is both continuous and decreases with distance from its base (i.e., bottom) to a zero thickness at its furthest location from the base. Because the thickness: (1) is continuous, (2) diminishes with upward distance from its base to an ultimate value of zero, and (3) is no greater than 10 nm at its base, it necessarily follows that a difference between the thickness of a lower portion and a thickness of an intermediate portion (e.g. selected along the continuum of thicknesses that diminish to an ultimate thickness of zero) ranges from 0.1 nm to 10 nm.
Regarding claim 7, Cai as modified by Furukawa teaches the method as claimed in claim 5, and Cai further teaches wherein a difference between the thickness of the intermediate portion and the thickness of the upper portion ranges from 0.1 nm to 10 nm {Fig. 2E; [0040]}.
Examiner’s Note: Cai teaches in paragraph [0040] the low-k sidewall spacers 122A and 122B may have a thickness at its base of about 3-10 nm. And Cai’s Fig. 2E illustrates that the thickness of each spacer (122) is both continuous and decreases with distance from its base (i.e., bottom) to a zero thickness at its furthest location from the base. Because the thickness: (1) is continuous, (2) diminishes with upward distance from its base to an ultimate value of zero, and (3) is no greater than 10 nm at its base, it necessarily follows that a difference between the thickness of an intermediate portion and a thickness of an upper portion (e.g. selected along the continuum of thicknesses that diminish to an ultimate thickness of zero) ranges from 0.1 nm to 10 nm.
Regarding claim 8, Cai as modified by Furukawa teaches the method as claimed in claim 1, and Cai further teaches wherein the dielectric contact spacer (122) is formed from a dielectric contact spacer layer which is made of a low-k dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbide, an extreme low-k dielectric material, or combinations thereof {Fig. 2E; [0040], dielectric contact spacer (122) is a low-k material made of silicon-carbon-nitride (SiCN)}.
Regarding claim 9, Cai as modified by Furukawa teaches a method for manufacturing a semiconductor device, comprising:
forming a transistor (104) on a semiconductor substrate (102), the transistor (104) including a gate structure (108, 110), a spacer (112) covering a lateral surface of the gate structure (108, 110), and a source/drain structure (114) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102), the patterned dielectric layer (118) including an opening (120) that extends from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114), and [the patterned dielectric layer] covering and interfacing the upper portion of the gate structure (108, 110) {Figs. 2B, 2C; [0036-0037]};
conformally depositing a dielectric contact spacer layer (layer of 122) on the patterned dielectric layer (118) and the source/drain structure (114) {Fig. 2E; [0040]};
anisotropically etching the dielectric contact spacer layer (layer of 122) to form a dielectric contact spacer (122) covering a sidewall of the opening (120) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108, 110) by the dielectric contact spacer (122) and the patterned dielectric layer (118) {Fig. 2F; [0041]}.
Cai does not teach the spacer partially covering a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer.
In an analogous art, Furukawa teaches in Fig. 10 a spacer (1550) partially covering a lateral surface of a gate structure (1240) to expose an upper portion of the gate structure (1240) from the spacer (1550) {col. 6, ll. 36-52}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa – such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52.
Regarding claim 10, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the upper portion of the gate structure (108, 110) exposed from the spacer (Cai’s 112 as modified by Furukawa) is covered by the patterned dielectric layer (118) after formation of the patterned dielectric layer (118) {Figs. 2A, 2B; [0034]}.
Regarding claim 11, Cai as modified by Furukawa teaches the method as claimed in claim 10, and Cai further teaches wherein the upper portion of the gate structure (108, 110) is isolated from the conductive contact (124) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 12, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer layer (layer of 122) is made of a low-k dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbide, an extreme low-k dielectric material, or combinations thereof {Fig. 2E; [0040], dielectric contact spacer layer (layer of 122) is a low-k material made of silicon-carbon-nitride (SiCN)}.
Regarding claim 13, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer layer (layer of 122) has a thickness ranging from 2 nm to 300 nm {Fig. 2E; [0040], thickness … of about 3-10 nm}.
Regarding claim 14, Cai as modified by Furukawa teaches the method as claimed in claim 9, and Cai further teaches wherein the dielectric contact spacer (122) has a thickness which decreases gradually along a direction from the top surface of the source/drain structure (114) to the top surface of the patterned dielectric layer (118) {Fig. 2E; [0040]}.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Furukawa as applied to claim 1 and further in view of Zhu et al. (US20080173941A1).
Regarding claim 2, Cai as modified by Furukawa teaches the method as claimed in claim 1, but Cai does not teach wherein exposure of the upper portion of the gate structure from the spacer occurs by depositing a spacer material layer to cover the gate structure and over-etching the spacer material layer by an anisotropic etching process.
Furukawa teaches in Fig. 10 and lines 36-52 of col. 6 that exposure of an upper portion of a gate structure (1240) from a spacer (1550) occurs by depositing a spacer material layer (layer of 1550) to cover the gate structure (1240) and over-etching the spacer material layer (layer of 1550) by an etching process. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the further teachings of Furukawa – such that exposure of the upper portion of the gate structure from the spacer occurs by depositing a spacer material layer to cover the gate structure and over-etching the spacer material layer by an etching process – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52.
Cai as modified by Furukawa does not teach the etching process is an anisotropic etching process.
In an analogous art, Zhu teaches in paragraph [0008] that isotropic (non-directional) and anisotropic (directional) etching are alternatives in which the former achieves uniform etching in all directions to provide rounded geometries after etching and the latter achieves directional etching to provide sharp/precise geometries after etching. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the teachings of Zhu – such that Furukawa’s etching process is anisotropic – to acquire a more precise geometry of the etched spacer. Moreover, applying a known technique (e.g., as taught by Zhu) in the same way to enhance another known technique (e.g., as taught by Cai and Furukawa) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Furukawa and Chang et al. (US20200395320A1).
Regarding claim 21, Cai teaches a method for manufacturing a semiconductor device, comprising:
forming a gate structure (108/[108, 110]) on a semiconductor substrate (102) {Fig. 2A; [0033-0034]};
forming a spacer (112) partially covering a lateral surface of the gate structure (108/[108, 110]) {Figs. 2A, 2B; [0034]};
forming a source/drain structure (114) on the semiconductor substrate (102), the source/drain structure (114) being spaced apart from the gate structure (108/[108, 110]) by the spacer (112) {Fig. 2A; [0033-0034]};
forming a patterned dielectric layer (118) on the semiconductor substrate (102) to cover the gate structure (108/[108, 110]) and the spacer (112), the patterned dielectric layer (118) being formed with an opening (120) extending from a top surface of the patterned dielectric layer (118) to a top surface of the source/drain structure (114) {Figs. 2B, 2C; [0036-0037]};
forming a dielectric contact spacer (122) to cover a sidewall of the opening (120), the dielectric contact spacer (122) extending from the top surface of the patterned dielectric layer (118) to the top surface of the source/drain structure (114) {Fig. 2E; [0040]}; and
forming a conductive contact (124) in the opening (120) such that the conductive contact (124) is connected to the source/drain structure (114) and is isolated from the gate structure (108/[108, 110]) by the dielectric contact spacer (122) and a portion of the patterned dielectric layer (118) {Fig. 2F; [0041]},
wherein the portion of the patterned dielectric layer (118) includes a first lateral surface interfacing the dielectric contact spacer (122) {Fig. 2F; [0041]}.
Cai does not teach the spacer partially covering a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer, wherein the portion of the patterned dielectric layer includes a second lateral surface interfacing the upper portion of the gate structure and the spacer.
Furukawa teaches in Figs. 10 and 16 a spacer (1550) partially covering a lateral surface of a gate structure (1240) to expose an upper portion of the gate structure (1240) from the spacer (1550) {col. 6, ll. 36-52}, wherein a portion of a patterned layer (1830) includes a lateral surface interfacing an upper portion of the gate structure (1240) and the spacer (1550). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method based on the teachings of Furukawa – such that the spacer partially covers a lateral surface of the gate structure to expose an upper portion of the gate structure from the spacer, wherein the portion of the patterned layer includes a second lateral surface interfacing the upper portion of the gate structure and the spacer – to allow a dielectric layer to form around the corners of gate conductor 1240 for better encapsulation. Furukawa col. 6, ll. 36-52.
Furukawa does not teach expressly that the patterned layer is a dielectric layer; however, Furukawa teaches this layer (1830) is a passivation layer. In an analogous art, Chang teaches in paragraph [0019] that silicon oxide and silicon nitride are both passivation layers and dielectrics (similar to Applicants’ disclosure in paragraph [0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s method as modified by Furukawa based on the teachings of Chang – such that Furukawa’s passivation patterned layer is a dielectric (as is Cai’s patterned layer (118)) – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 22, Cai as modified by Furukawa and Chang teaches the method as claimed in claim 21, and Cai further teaches wherein formation of the dielectric contact spacer (122) includes:
conformally depositing a dielectric contact spacer layer (layer of 122) on the patterned dielectric layer (118) and the source/drain structure (114) {Fig. 2E; [0040]}; and
etching away horizontal portions of the dielectric contact spacer layer (layer of 122) disposed on the top surface of the patterned dielectric layer (118) and the top surface of the source/drain structure (114) {Fig. 2E; [0040]}.
Regarding claim 23, Cai as modified by Furukawa and Chang teaches the method as claimed in claim 22, and Cai further teaches wherein the source/drain structure (114) includes a lower portion recessed into the semiconductor substrate (102), and an upper portion interfacing the dielectric contact spacer (122) {Fig. 2F}.
Regarding claim 24, Cai as modified by Furukawa and Chang teaches the method as claimed in claim 23, and Cai further teaches wherein the spacer (112) is spaced apart from the dielectric contact spacer (122) by the portion of the patterned dielectric layer (118) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 25, Cai as modified by Furukawa and Chang teaches the method as claimed in claim 24, and Cai further teaches wherein the spacer (112) includes:
a lower portion interfacing the upper portion of the source/drain structure (114) {Fig. 2F}; and
an upper portion spaced apart from the conductive contact (124) by the portion of the patterned dielectric layer (118) and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}.
Regarding claim 26, Cai as modified by Furukawa and Chang teaches the method as claimed in claim 25, and Cai further teaches wherein
the gate structure (108/[108, 110]) further includes a lower portion disposed below the upper portion of the gate structure (108/[108, 110]) {Fig. 2F};
the lower portion of the gate structure (108/[108, 110]) is spaced apart from the conductive contact (124) by the spacer (112), the portion of the patterned dielectric layer (118), and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}; and
the upper portion of the gate structure (108/[108, 110]) is spaced apart from the conductive contact (124) by the portion of the patterned dielectric layer (118) and the dielectric contact spacer (122) {Fig. 2F, using a line drawn diagonally}.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights