DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, claims 1-15, without traverse is acknowledged. Claims 16-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 102 / 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-3, 4, 5, 8, 10, 12 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Avery et al. (US 6,501,632), (hereinafter, Avery) or on the alternative Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Avery et al. (US 6,501,632), (hereinafter, Avery) in view of Brennan et al. (US 6,399,990), (hereinafter, Brennan).
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RE Claim 1, Avery discloses an electrostatic discharge protection device having an nMOS transistor with bias simultaneously applied to the gate and the p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback. Avery discloses in FIGS. 3 and 4 shown combined and annotated above, a semiconductor device, comprising:
an n-buried layer 402;
a p-well region 406 over the n-buried layer 402, refer;
an n-channel metal-oxide semiconductor field-effect transistor that includes an n- drain region 426; and
a vertical NPN bipolar junction transistor having a collector that is the n-drain region 426 and a base that is the p-well region 406, wherein the p-well 406 region is floating. It is the examiner position that the p-well 406 region is floating since it is not connected to a fixed electrical potential such as Ground or any specific bias voltage. However, if applicant proves otherwise, it would have been obvious for one ordinary skill in the art, prior to the effective filing date of the instant application to have the p-well of Avery disclosure floating similar to Brennan discloses invention [column 4, lines 25-35], in order to maximize the ESD performance of Avery’s NMOS, as disclosed by Brennan [column 4, lines 25-35].
RE Claim 2, Avery discloses device, wherein the vertical NPN bipolar junction transistor has an emitter that is the n-buried layer 402, referring to FIG. 4 as annotated above [column 4, lines 39-65].
RE Claim 3, Avery discloses device, wherein the n-buried layer 402 is electrically connected to a reference voltage Vss “positive supply voltage” [column 4, lines 45-50].
RE Claim 4, Avery discloses device, wherein the n-drain region 426 is electrically connected to an input/output pad 302, referring to FIG. 4 [column 4, lines 35-37].
RE Claim 5, Avery discloses device, wherein the n-drain region 326 includes an n+ region, referring to FIG. 4.
RE Claim 8, Avery discloses device, wherein the n-buried layer 402 is electrically connected to the reference voltage Vss “positive high voltage” [column 4, lines 45-50].
RE Claim 10, Avery discloses device, semiconductor device, comprising:
an n-buried layer 402 that is electrically connected to a reference voltage Vss or a power voltage Vdd “positive high voltage” [column 4, lines 45-50];
a p-well region 406 over the n-buried layer 402;
an n-channel metal-oxide semiconductor field-effect transistor “NMOS” that includes an n-drain region 426 electrically connected to an input/output pad 302, referring to FIG. 4; and
a vertical NPN bipolar junction transistor having a collector that is the n-drain region 426, an emitter that is the n-buried layer 402; and
a base that is the p-well region 406, wherein the p-well region is floating. It is the examiner position that the p-well 406 region is floating since it is not connected to a fixed electrical potential such as Ground or any specific bias voltage. However, if applicant proves otherwise, it would have been obvious for one ordinary skill in the art, prior to the effective filing date of the instant application to have the p-well of Avery disclosure floating similar to Brennan discloses invention [column 4, lines 25-35], in order to maximize the ESD performance of Avery’s NMOS, as disclosed by Brennan [column 4, lines 25-35].
RE Claim 12, Avery discloses device, wherein the n-buried layer 402 is electrically connected to the reference voltage Vss “ground” [column 4, lines 45-50].
RE Claim 14, Avery discloses device, wherein the n-buried layer 402 is electrically connected to the power voltage Vdd “positive high voltage” [column 4, lines 45-50].
Allowable Subject Matter
Claims 6, 7, 9, 11, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case:
Chi (US 6,255,713) discloses a current source formed in a p-type substrate is disclose. First, a deep n-well is formed within the p-type substrate and a buried n+ layer is formed within the deep n-well. Next, a p-well is formed within the deep n-well and atop the buried n+ layer. The p-well and deep n-well are then surrounded by an isolation structure that extends from the surface of the substrate to below the level of the p-well. A n+ reference structure is formed within the p-well and a gate is formed above the p-well, the gate separated from the substrate by a thin oxide layer, the gate extending over at least a portion of the n+ reference structure. Finally, a n+ output structure is formed within the p-well. An input reference current is provided to the n+ reference structure and an output current is provided by the n+ output structure.
Lee et al. (US 6,756,642) disclose a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.
Schneider et al. (US 2009/0050970) disclose an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898