Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-7, 9-14, and 21-27 are pending.
-Claims 8 and 15-20 are cancelled.
-Claims 1, 7, 9, 14, and 21 are amended.
-Claim 27 is new.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Internet Communications
Examiner notes that according to MPEP 502.03, The internet communication authorization “must be submitted on a separate paper to be entitled to acceptance in accordance with 37 CFR 1.4(c).” and therefore the statement in the Remarks July 7, 2026 is not considered sufficient for Examiner to utilize email communications.
Response to Amendment
The amendment to the claims (specifically Claim 1) filed on July 7, 2026 does not comply with the requirements of 37 CFR 1.121(c)(2) because not all added limitations were underlined and previously present limitations were underlined. Amendments to the claims filed on or after July 30, 2003 must comply with 37 CFR 1.121(c)(2) which states:
(2) When claim text with markings is required. All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of “currently amended,” and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. Only claims having the status of “currently amended,” or “withdrawn” if also being amended, shall include markings. If a withdrawn claim is currently amended, its status in the claim listing may be identified as “withdrawn—currently amended.”
The properly marked amended Claim 1 is made of record and presented below:
1. (Currently Amended) A method for forming a semiconductor structure, comprising:
forming an active region over a substrate;
etching the active region to form a recess;
forming a dummy gate structure over the active region;
forming a gate spacer layer alongside the dummy gate structure;
forming a sacrificial layer in the recess;
forming a source/drain feature over the sacrificial layer in the recess;
removing the substrate;
forming a patterned mask layer having an opening pattern corresponding to the source/drain feature, wherein an extension line of a sidewall of the opening pattern passes through the gate spacer layer;
etching the active region and the sacrificial layer using the patterned mask layer to form an opening exposing a backside surface of the source/drain feature;
and forming a first contact plug in the opening.
Response to Arguments
Applicant's arguments over the amended limitations filed July 7, 2026 have been fully considered.
Regarding Claim 1 and its dependents, the argument is considered persuasive and the rejection has been updated to address the newly amended limitations by now incorporating the teachings of .
Regarding Claims 9 and 21 and their dependents, the arguments are considered persuasive in regards to the previous interpretations of the prior art and the rejections have been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Pub. 2024/0204067), hereinafter Xie I, in view of Yoo (U.S. Pub. 2024/0282708), hereinafter Yoo.
Regarding Claim 1, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]), comprising:
-forming an active region (consisting of regions (16) and (12); Fig. 1, Paragraph [0071]) over a substrate ((102); Fig. 2, Paragraph [0074]);
-etching the active region to form a recess ((810); Figs. 9A and 9C, Paragraph [0107]);
-forming a dummy gate structure ((410); Fig. 4C, Paragraph [0092]) over the active region (regions (12) and (16), See also X and Y cross sections);
-forming a gate spacer layer ((610); Fig. 6C, Paragraph [0098]) alongside the dummy gate structure (410);
-forming a sacrificial layer in the recess ((1020); Figs. 10A and 10C, Paragraph [0113]);
-forming a source/drain feature ((1220); Figs. 12A and 12C, Paragraph [0119]) over the sacrificial layer in the recess (1020);
-removing the substrate ((102); Fig. 14C, Paragraph [0133]);
-etching the active region and the sacrificial layer (1020) to form an opening ((1820); Figs. 18A and 18C, Paragraph [0142]) exposing a backside surface of the source/drain feature (1220); and
-forming a first contact plug in the opening ((1930); Figs. 19A and Fig. 19C, Paragraph [0145]).
Xie I further teaches:
-extension lines of the side walls (vertically) of the opening (1820) pass through the gate spacer layer (610) (Figs. 18A and 18C)
-using dry HCL etching (Paragraph [0142]) to form the opening (1820), which is known to one of ordinary skill in the art as an anisotropic etch which utilizes masks
Xie I does not explicitly disclose:
-forming a patterned mask layer having an opening pattern corresponding to the source/drain feature, wherein an extension line of a sidewall of the opening pattern passes through the gate spacer layer;
-using the patterned mask layer to form an opening
Yoo teaches a method (Figs. 6A-19) for forming a semiconductor structure (Figs. 4-5D, Paragraph [0030]) including back-side contacts ((BSC1); Fig. 5A, Paragraph [0077]) comprising:
-forming a patterned mask layer ((MAP); Fig. 16, Paragraph [0139]) having an opening pattern corresponding to the source/drain feature ((SD1); Fig. 16, Paragraph [0036]), wherein an extension line of a sidewall of the opening pattern (vertically) passes through the gate spacer layer ((GS); Figs. 13B and 16, Paragraph [0049]);
-using the patterned mask layer to form an opening ((BCH1); Fig. 16, Paragraph [0139])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yoo into the device of Xie I such that it further comprised forming a patterned mask layer having an opening pattern corresponding to the source/drain feature, wherein an extension line of a sidewall of the opening pattern passes through the gate spacer layer; and using the patterned mask layer to form an opening. This would be due to the fact that doing so would produce the expected result of incorporating elements to perform an etch to form an opening.
Regarding Claim 2, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a second contact plug (Xie I, (1320), specifically the contact element, below the line; Fig. 13A, Paragraph [0130]) on a frontside surface (above in the Y cross sections) of the source/drain feature (Xie I, (1220)).
Regarding Claim 3, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 2 wherein:
-in a direction parallel to a longitudinal axis of the active region (along X-Y plane), the second contact plug (Xie I, (1320), See Fig. 19A) is narrower than the first contact plug (Xie I, (1930), See Fig. 19C).
Regarding Claim 4, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 2 wherein:
-in a direction perpendicular to a longitudinal axis of the active region (along Z-Y plane), the second contact plug is longer (Xie I, (1320), See Fig. 19A) than the first contact plug (Xie I, (1930), See Fig. 19A).
Regarding Claim 5, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a power supply line (Xie I, (1920); Figs. 19A and 19C, Paragraph [0146]) below and in direct contact with the first contact plug (Xie I, (1930)).
Regarding Claim 6, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming an insulating layer (Xie I, (620); Fig. 6A, Paragraph [0098]) between the sacrificial layer (1020) and the source/drain feature (1220). (See Fig. 12A)
Regarding Claim 7, Xie I as modified by Yoo teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a stack (Xie I, (10); Fig. 4A, Paragraph [0080]) over the substrate (Xie I, (102)), wherein the stack (Xie I, (10)) includes first semiconductor layers (Xie I, (110); Fig. 4A, Paragraph [0080]) and second semiconductor layers (Xie I, (112); Fig. 4A, Paragraph [0080]) alternately stacked;
-patterning the stack (Xie I, (10)) and the substrate (Xie I, (102)) into the active region (Xie I, regions (12) and (16), See also X and Y cross sections);
-removing the dummy gate structure (Xie I, (410)) and the first semiconductor layers (110) (Xie I, Paragraph [0124]); and
-forming a gate stack (Xie I, (1310); Figs. 13B and 13C, Paragraph [0124]) surrounding the second semiconductor layers (Xie 1, (112), See also Fig. 13B).
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Pub. 2023/0093101), hereinafter Xie II.
Regarding Claim 9, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]), comprising:
-forming an active region (e.g. area where nanosheets and gates present within the substrate, such as region of assembly (300), hereinafter (AR); Figs. 1 and 4A, Paragraph [0040]) including a fin element ((100); Fig. 3A) and a plurality of nanostructures (‘nanosheets’ (305), specifically the Si layers (315); Figs. 1 and 3A);
-etching the active region to form a source/drain recess (e.g. (505-1); Fig. 5A, Paragraph [0049])
-forming a first sacrificial layer (e.g. (605-1); Fig. 6A, Paragraph [0051]) in the source/drain recess (505-1) over the fin element (100); ((1215); Fig. 12)
-forming a semiconductor layer (e.g. (630-1); Fig. 6A, Paragraph [0053]) in the source/drain recess (505-1) over the first sacrificial layer (605-1)
-forming a first source/drain (e.g. (620-1); Fig. 6A, Paragraph [0051]) in the source/drain recess over the semiconductor layer (630-1)
-forming a gate stack (e.g. (715-1); Fig. 7A, Paragraph [0055]) surrounding the plurality of nanostructures ((315) of (350));
-flipping the semiconductor structure upside down (Fig. 8A, Paragraph [0061]); ((1250); Fig. 12)
-etching the fin element (100) to form a first portion of an opening ((905); Fig. 9A, Paragraph [0063]); (As part of (1255); Fig. 12)
-etching the first sacrificial layer (605-1) and the semiconductor layer (630) to form a second portion of the opening ((1005); Fig. 10A, Paragraph [0065]), wherein the first portion (905) of the opening is wider than the second portion (1005) of the opening; (As part of (1255); Fig. 12)
-and forming a first contact plug to fill the opening ((1105); Fig. 11A, Paragraph [0066]). ((1270) of Fig. 12)
Xie II does not explicitly state the semiconductor layer (630-1) is a dielectric layer.
Xie II further states the semiconductor layer may be made of other types of semiconductor materials (Paragraph [0053]) and that in some embodiments the source/drain regions may be deposited over a dielectric material (e.g. SiC; Paragraph [0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Xie II into the present embodiment of Xie II such that the semiconductor layer used is a dielectric layer. This would be due to the fact that doing so would produce the expected result of including a viable barrier layer between the first sacrificial layer and the first source/drain.
Regarding Claim 10, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, wherein:
-the first portion of the opening (905) has a first width (‘W1’ necessarily, Fig. 10A)
- the second portion of the opening (1005) has a second width (‘W2’ necessarily, Fig. 10A)
-the first width (W1) is greater than the second width (W2)
Xie does not explicitly state:
-a ratio of the first width to the second width is in a range from about 1.15 to about 5.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie II such that a ratio of the first width to the second width is in a range from about 1.15 to about 5. This would be due to the fact that doing so would fall under optimization or routine experimentation within prior art conditions (See MPEP 2144.05). In this case, Xie II already teaches the relative width conditions (W1 > W2). Furthermore, the width ratio is a result effective variable portions: the second width is restricted by the available area above the source/drain feature (for self-alignment (Xie II, Paragraph [0066]) and safety of other device elements), while the first width is dependent on desired etchant methods, ease of deposition during metallization and latter connections, etc.
Furthermore, Applicant has provided no evidence in the disclosure as to either the critical nature of the width ratio or unexpected results arising therefrom. Patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 11, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, further comprising:
-forming a silicide layer on a surface of the fin element (100) exposed from the opening and on a surface of the first source/drain feature (605-1) exposed from the opening. (Paragraph [0066] specifies deposition of (1105) includes a silicide liner, necessarily it would be formed on the exposed surfaces)
Regarding Claim 12, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, further comprising:
-forming a second sacrificial layer (e.g. (605-2); Fig. 6A, Paragraph [0051]) in the fin element;
-forming a second source/drain feature (e.g. (620-2); Fig. 6A, Paragraph [0051]) over the second sacrificial layer (605-2) and adjoining the plurality of nanostructures ((315) of (305));
-forming an interlayer dielectric layer ((720); Fig. 7A, Paragraph [0059]) covering the first source/drain feature (620-1) and the second source/drain feature (620-2); and
-forming a second contact plug ((725); Fig. 7A, Paragraph [0059]) through the interlayer dielectric layer (720) (explicitly stated “forming an electrical contact 725 (that is, a frontside contact) through the ILD layer 720”, Paragraph [0059]) and on the second source/drain feature (620-2) before flipping the semiconductor structure upside down (as in Fig. 8A, also step (1250) of Fig. 12, Paragraph [0061]). ((1240) of Fig. 12)
Regarding Claim 13, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 12, further comprising:
-forming a metal line on (‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]) and electrically connected (by ‘via’ (1115); Paragraph [0067]) to the first contact plug (1105), wherein the metal line (1125) is electrically isolated from the second source/drain feature (605-2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Xie II in view of Lu et al. (U.S. Pub. 2023/0114191), hereinafter Lu.
Regarding Claim 14, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 13, further comprising:
-forming a first dummy gate structure and a second dummy gate structure (e.g. (405-2) and (405-1); Fig. 4A, Paragraph [0047]) over the active region (AR);
-patterning the active region into the plurality of nanostructures and the fin element (Fig. 5A, Paragraph [0049]); ((1220) of Fig. 12) and
-replacing the second dummy gate structure with the gate stack ((715-1); Fig. 7A, Paragraph [0055])
Xie II does not disclose:
-replacing the first dummy gate structure with a isolation structure;
-wherein the isolation structure extends into the fin element and is spaced apart from the metal line by the fin element.
Lu teaches a method for forming a semiconductor structure ((200); Fig. 22, Paragraphs [0012] and [0015]) comprising forming dummy gate structures (including (34) and (32); Fig. 3, Paragraph [0016]) on fin elements ((24)/(24’) of (20); Fig. 3, Paragraph [0015], and further comprising:
-replacing the first dummy gate structure ((34) and (32) of e.g. leftmost structure of 8C) with a isolation structure ((72); Figs. 9-11, Paragraphs [0031] and [0034]);
- wherein the isolation structure (72) extends into the fin element ((24)/(24’))
The limitation “and is spaced apart from the metal line by the fin element” is necessarily fulfilled by the incorporation of the teachings of Lu into Xie II.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lu into the method of Xie II such that it further comprises replacing the first dummy gate structure with a isolation structure, wherein the isolation structure extends into the fin element and is spaced apart from the metal line by the fin element. This would be due to the fact that doing so would reduce parasitic capacitance and leakage current between features (Lu, Paragraph [0011] and [0064]).
Claims 21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Pub. 2024/0297167), hereinafter Xie III, in view of Xie II (U.S. Pub. 2023/0093101).
Regarding Claim 21, Xie III teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]), comprising:
forming an active region (‘nanosheet region’ (20); Fig. 1, Paragraph [0069]) over a substrate ((102); Fig. Figs. 2A-2C, Paragraph [0072]), wherein the substrate includes a first cell region (Corresponding to NFET (12); Fig. 1, Paragraph [0069]- later identified as right three stacks of Fig. 8C) and a second cell region (Corresponding to PFET (16); Fig. 1, Paragraph [0069]- later identified as left three stacks of Fig. 8C), and the active region includes alternating first and second semiconductor layers ((110) and (112); Figs. 3A-3C, Paragraph [0079]) over a fin element ((106); Figs. 3A-3C, Paragraph [0072]);
etching the active region to form a first recess in the first cell region and the second recess in the second cell region (corresponding to right of center (840) and left of center (840), respectively; Fig. 8C, Paragraph [0107]);
forming a first sacrificial layer in the first recess and a second sacrificial layer in the second recess (corresponding to right of center (920) and left of center (920), respectively; Fig. 9C, Paragraph [0110]);
forming a first source/drain feature over the first sacrificial layer and a second source/drain feature over the second sacrificial layer (corresponding to right of center (930) and left of center (930), respectively; Fig. 9C, Paragraph [0110]);
forming an isolation structure along a boundary between the first cell region and the second cell region ((1040); Fig. 10C, Paragraph [0122]);
removing the first semiconductor layers (with formation of gate structure (1010); Fig. 10C, Paragraph [0120]), wherein the second semiconductor layers in the first cell region ((112) in three right stacks, corresponding to (12)) form first nanostructures (necessarily, removal of (110) and deposition of gate (1010) creates GAA transistors) and the second semiconductor layers in the second cell region ((112) in three left stacks, corresponding to (16)) form second nanostructures (necessarily, removal of (110) and deposition of gate (1010) creates GAA transistors);
removing the substrate ((Fig. 12C, Paragraph [0129]);
forming a first contact plug ((1710) on the right; Fig. 17C, Paragraph [0141]) through the first sacrificial layer (via opening (1602) on the right; Paragraph [0141]) and on the first source/drain feature (right (930));
forming a second contact plug ((1710) on the left; Fig. 17C, Paragraph [0141]) through the second sacrificial layer (via opening (1602) on the left) and on the second source/drain feature (left (930)); and
forming a conducting line ((1830); Fig. 18C, Paragraph [0147]) on the first contact plug and the second contact plug ((1710) on right and left, respectively),
wherein the conducting line (1830) continuously extends under the first contact plug (right (1710)), the isolation (1040) structure, and the second contact plug (left (1710)).
Xie III does not explicitly state the conducting line (1830) is a metal.
Xie III further states the conducting line may be made of according to known techniques (Paragraph [0149]) and that known materials for conducting structures include metals (e.g. Cu; Paragraph [0145])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Xie III into the present embodiment of Xie III such that the conducting line used is a metal line. This would be due to the fact that doing so would produce the expected result of including a viable conducting material to for the backside power delivery network.
Xie III does not explicitly teach:
- forming a first contact plug through the fin element
-forming a second contact plug through the fin element
Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]), comprising:
-forming a contact plug ((1105); Fig. 11A, Paragraph [0066]). ((1270) of Fig. 12)
through a fin element ((100); Fig. 9A-11A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Xie II into the device of Xie III such that the method further comprised forming a first contact plug through the fin element and forming a second contact plug through the fin element. Futhermore, the incorporation would be done such that a bottom portion of the first contact plug is wider than an upper portion of the first contact plug in a cross-sectional view (Xie II, (1105) corresponding to the top contacting the via (1115) and the bottom contacting the source/drain (605); Fig. 11A). This would be due to the fact that doing so would produce the expected result of self-aligned contacts while also offering a lower resistance of buried power rails (Xie II, Paragraph [0033]).
Regarding Claim 23, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-the isolation structure (Xie III, (1040)) is separated from the metal line (Xie II, ‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]) by the fin element (Xie II, (100)). (Necessarily by incorporation of Xie II).
Regarding Claim 24, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-the first sacrificial layer (Xie III, right (930)) is made of a different material (Xie III, e.g. AlOx, Paragraph [0112]) than the fin element (Xie II, (100) is silicon; Paragraph [0037]), and the second sacrificial layer (Xie III, left (930)) is made of a different material (Xie III, e.g. AlOx, Paragraph [0112]) than the fin element (Xie II, (100) is silicon; Paragraph [0037]).
Regarding Claim 25, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-a bottom portion of the first contact plug is wider than an upper portion of the first contact plug in a cross-sectional view (Xie II, (1105) corresponding to the top contacting the via (1115) and the bottom contacting the source/drain (605); Fig. 11A).
Regarding Claim 26, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-a top surface of the isolation structure (Xie III, top of (1040), Fig. 10C) is higher than a top of the first source/drain feature (Xie III, top of right (930), Fig. 10C), and a bottom surface of the isolation structure(Xie III, bottom of (1040), Fig. 10C) is lower than a bottom of the first source/drain feature (Xie III, top of right (930), Fig. 10C).
Claims 22 and 27 is rejected under 35 U.S.C. 103 as being unpatentable over Xie III and Xie II as supported by Lu.
Regarding Claim 22, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, but after modification the method does not teach:
- the isolation structure (Xie III, (1040)) is interfaced with the metal line (Xie II, ‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]). As the incorporation of the teachings of Xie II expands the fin element and changes the connection structure.
Xie III originally teaches:
-the isolation structure (Xie III, (1040)) is interfaced (understood as in direct contact with, sharing an interface) with the metal line (Xie III, (1720)) See Fig. 17C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reincorporate the teachings of Xie III into the Xie III as modified by Xie II such that the isolation structure is interfaced with the metal line. This would be due to the fact that doing so would provide for a separation of NFET and PFET cells and flexibility in cell height (Xie III, Paragraphs [0142] and [0146]). Furthermore, it is known that the deeper (longer) an isolation feature is through a semiconducting portion, the more effective it is at reducing leakage current (Lu, Paragraphs [0039] and [0040]). One of ordinary skill of the art would recognize, therefore, that the length of the isolation structure is a result effective variable in relation to leakage current, and to expand the isolation structure such that it is interfaced with the metal line would be under length considerations.
Regarding Claim 27, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, further comprising:
-forming a dummy gate structure (Xie III, (810); Fig. 8C, Paragraph [0101]) over the active region (Xie III, (20);
-recessing the first semiconductor layers (Xie III, (110)) of the active region to form notches (Xie III, ‘indented cavity’; Paragraph [0108]);
-forming inner spacer layers (Xie III, (808); Fig. 8C, Paragraph [0108]) in the notches; and
Xie III further teaches:
-removing the dummy gate structure and the alternating first and second semiconductor layers and the fin element of the active region to form a trench (i.e. before replacement metal gate when forming ‘isolation gate structures’; Paragraph [0122]), wherein the trench exposes the inner spacer layers (necessarily, if formed equivalently to (1040) which extends below (104); Paragraph [0122]),
-wherein the isolation structure is formed in the trench (‘isolating gate structures’ filled with dielectric materials; Paragraph [0122]).
Examiner notes that in the prior claim rejections that the specific element (1040) was identified as the “isolation structure”. This was for simplicity of demonstrating the claim limitations as the gate cut region is not shown in figures. However, it is recognized that as Xie III explicitly states that (1040) is made in a similar process (Paragraph [0122]), so one of ordinary skill in the art would recognize their equivalency. The differences would simply be in trench positioning (cutting through the gate and stacked layers rather than the source/drain region) and the first and second cell regions would be interpreted as first and second CMOS cells (Paragraph [0122]) rather than the utilized NMOS and PMOS.
Xie III nor Xie II explicitly state the formation of the trench is completed using etching.
Lu teaches a method for forming a semiconductor structure ((200); Fig. 22, Paragraphs [0012] and [0015]) comprising the formation of a gate cut isolation structure ((72); Fig. 10, Paragraph [0034]) comprising a trench ((60); Fig. 10, Paragraph [0032]) filled with a dielectric material ((68); Fig. 10, Paragraph [0034]), wherein:
-the trench (60) is formed by etching (Paragraph [0031]) through dummy gate structure (including (34) and (32); Fig. 3, Paragraph [0016]) and subsequent elements.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lu into the method of Xie III as modified by Xie II such that the formation of the trench is completed using etching. This would be due to the fact that doing so would produce the predictable result of utilizing known methods of selective material removal (Lu, e.g. in conjunction with using an etching mask; Paragraph [0031])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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