Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 5, 2023 was filed with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention Group I, Claims 1-14, in the reply filed on February 8, 2026 is acknowledged. Following Applicant’s amendment to the claims, Claims 15-20 are cancelled, Claims 10 and 12 are amended, and Claims 21-26 have been added. Upon review, Examiner finds no new matter has been introduced by the amendment and the new claims fall within the scope of the elected Invention Group I. Therefore, an examination on the merits of Claims 1-14 and 21-26 follows.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Method Of Forming Gate-All-Around Transistors Including Backside Contact Plugs For Source and Drain Features And Isolation Structures--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (U.S. Pub. 2024/0204067), hereinafter Xie I.
Regarding Claim 1, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]), comprising:
-forming an active region (consisting of regions (16) and (12); Fig. 1, Paragraph [0071]) over a substrate ((102); Fig. 2, Paragraph [0074]);
-etching the active region to form a recess ((810); Figs. 9A and 9C, Paragraph [0107]);
-forming a sacrificial layer in the recess ((1020); Figs. 10A and 10C, Paragraph [0113]);
-forming a source/drain feature ((1220); Figs. 12A and 12C, Paragraph [0119]) over the sacrificial layer in the recess (1020);
-removing the substrate ((102); Fig. 14C, Paragraph [0133]);
-etching the active region and the sacrificial layer (1020) to form an opening ((1820); Figs. 18A and 18C, Paragraph [0142]) exposing a backside surface of the source/drain feature (1220); and
-forming a first contact plug in the opening ((1930); Figs. 19A and Fig. 19C, Paragraph [0145]).
Regarding Claim 2, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a second contact plug ((1320), specifically the contact element, below the line; Fig. 13A, Paragraph [0130]) on a frontside surface (above in the Y cross sections) of the source/drain feature (1220).
Regarding Claim 3, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 2 wherein:
-in a direction parallel to a longitudinal axis of the active region (along X-Y plane), the second contact plug ((1320), See Fig. 19A) is narrower than the first contact plug ((1930), See Fig. 19C).
Regarding Claim 4, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 2 wherein:
-in a direction perpendicular to a longitudinal axis of the active region (along Z-Y plane), the second contact plug is longer (1320), See Fig. 19A) than the first contact plug ((1930), See Fig. 19A).
Regarding Claim 5, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a power supply line ((1920); Figs. 19A and 19C, Paragraph [0146]) below and in direct contact with the first contact plug (1930).
Regarding Claim 6, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming an insulating layer ((620); Fig. 6A, Paragraph [0098]) between the sacrificial layer (1020) and the source/drain feature (1220). (See Fig. 12A)
Regarding Claim 7, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 1, further comprising:
-forming a stack ((10); Fig. 4A, Paragraph [0080]) over the substrate (102), wherein the stack (10) includes first semiconductor layers ((110); Fig. 4A, Paragraph [0080]) and second semiconductor layers ((112); Fig. 4A, Paragraph [0080]) alternately stacked;
-patterning the stack (10) and the substrate (10) into the active region (regions (12) and (16), See also X and Y cross sections);
-forming a dummy gate structure ((410); Fig. 4C, Paragraph [0092]) over the active region (regions (12) and (16), See also X and Y cross sections);
-forming a gate spacer layer ((610); Fig. 6C, Paragraph [0098]) alongside the dummy gate structure (410);
-removing the dummy gate structure (410) and the first semiconductor layers (110) (Paragraph [0124]); and
-forming a gate stack ((1310); Figs. 13B and 13C, Paragraph [0124]) surrounding the second semiconductor layers ((112), See also Fig. 13B).
Regarding Claim 8, Xie I teaches a method for forming a semiconductor structure ((100); Fig. 1, Paragraphs [0071] and [0069]) of Claim 7, wherein:
etching the active region and the sacrificial layer to form the opening (810) comprises:
-forming a patterned mask layer ((804); Figs. 8A-8C, Paragraph [0107]) having an opening pattern (top of opening (810) with (804) side) corresponding to the source/drain feature ((1220) being deposited within (810)), wherein an extension line (i.e. a vertical line drawn along) of a sidewall of the opening (sides of (804) of (810)) pattern passes through the gate spacer layer (610) (See Fig. 8C).
Claims 9 and 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (U.S. Pub. 2023/0093101), hereinafter Xie II.
Regarding Claim 9, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]), comprising:
-forming a plurality of nanostructures (‘nanosheets’ (305), specifically the Si layers (315); Figs. 1 and 3A) over a fin element ((100); Fig. 3A);
-forming a first sacrificial layer (e.g. (605-1); Fig. 6A, Paragraph [0051]) in the fin element (100); ((1215); Fig. 12)
-forming a first source/drain feature (e.g. (620-1); Fig. 6A, Paragraph [0051]) over the first sacrificial layer (605-1) and adjoining the plurality of nanostructures ((315) of (305)); ((1235); Fig. 12)
-forming a gate stack (e.g. (715-1); Fig. 7A, Paragraph [0055]) surrounding the plurality of nanostructures ((315) of (350));
-flipping the semiconductor structure upside down (Fig. 8A, Paragraph [0061]); ((1250); Fig. 12)
-etching the fin element (100) to form a first portion of an opening ((905); Fig. 9A, Paragraph [0063]); (As part of (1255); Fig. 12)
-etching the first sacrificial layer (605-1) to form a second portion of the opening ((1005); Fig. 10A, Paragraph [0065]), wherein the first portion (905) of the opening is wider than the second portion (1005) of the opening; (As part of (1255); Fig. 12)
-and forming a first contact plug to fill the opening ((1105); Fig. 11A, Paragraph [0066]). ((1270) of Fig. 12)
Regarding Claim 11, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, further comprising:
-forming a silicide layer on a surface of the fin element (100) exposed from the opening and on a surface of the first source/drain feature (605-1) exposed from the opening. (Paragraph [0066] specifies deposition of (1105) includes a silicide liner, necessarily it would be formed on the exposed surfaces)
Regarding Claim 12, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, further comprising:
-forming a second sacrificial layer (e.g. (605-2); Fig. 6A, Paragraph [0051]) in the fin element;
-forming a second source/drain feature (e.g. (620-2); Fig. 6A, Paragraph [0051]) over the second sacrificial layer (605-2) and adjoining the plurality of nanostructures ((315) of (305));
-forming an interlayer dielectric layer ((720); Fig. 7A, Paragraph [0059]) covering the first source/drain feature (620-1) and the second source/drain feature (620-2); and
-forming a second contact plug ((725); Fig. 7A, Paragraph [0059]) through the interlayer dielectric layer (720) (explicitly stated “forming an electrical contact 725 (that is, a frontside contact) through the ILD layer 720”, Paragraph [0059]) and on the second source/drain feature (620-2) before flipping the semiconductor structure upside down (as in Fig. 8A, also step (1250) of Fig. 12, Paragraph [0061]). ((1240) of Fig. 12)
Regarding Claim 13, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 12, further comprising:
-forming a metal line on (‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]) and electrically connected (by ‘via’ (1115); Paragraph [0067]) to the first contact plug (1105), wherein the metal line (1125) is electrically isolated from the second source/drain feature (605-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xie II.
Regarding Claim 11, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 9, wherein:
-the first portion of the opening (905) has a first width (‘W1’ necessarily, Fig. 10A)
- the second portion of the opening (1005) has a second width (‘W2’ necessarily, Fig. 10A)
-the first width (W1) is greater than the second width (W2)
Xie does not explicitly state:
-a ratio of the first width to the second width is in a range from about 1.15 to about 5.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie II such that a ratio of the first width to the second width is in a range from about 1.15 to about 5. This would be due to the fact that doing so would fall under optimization or routine experimentation within prior art conditions (See MPEP 2144.05). In this case, Xie II already teaches the relative width conditions (W1 > W2). Furthermore, the width ratio is a result effective variable portions: the second width is restricted by the available area above the source/drain feature (for self-alignment (Xie II, Paragraph [0066]) and safety of other device elements), while the first width is dependent on desired etchant methods, ease of deposition during metallization and latter connections, etc.
Furthermore, Applicant has provided no evidence in the disclosure as to either the critical nature of the width ratio or unexpected results arising therefrom. Patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Xie II in view of Lu et al. (U.S. Pub. 2023/0114191), hereinafter Lu.
Regarding Claim 14, Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]) of Claim 13, further comprising:
-forming a first dummy gate structure and a second dummy gate structure (e.g. (405-2) and (405-1); Fig. 4A, Paragraph [0047]) over an active region (e.g. region of assembly (300); Fig. 4A, Paragraph [0040]);
-patterning the active region into the plurality of nanostructures and the fin element (Fig. 5A, Paragraph [0049]); ((1220) of Fig. 12) and
-replacing the second dummy gate structure with the gate stack ((715-1); Fig. 7A, Paragraph [0055])
Xie II does not disclose:
-replacing the first dummy gate structure with a gate isolation structure;
-wherein the gate isolation structure extends into the fin element and is spaced apart from the metal line by the fin element.
Lu teaches a method for forming a semiconductor structure ((200); Fig. 22, Paragraphs [0012] and [0015]) comprising forming dummy gate structures (including (34) and (32); Fig. 3, Paragraph [0016]) on fin elements ((24)/(24’) of (20); Fig. 3, Paragraph [0015], and further comprising:
-replacing the first dummy gate structure ((34) and (32) of e.g. leftmost structure of 8C) with a gate isolation structure ((72); Figs. 9-11, Paragraphs [0031] and [0034]);
- wherein the gate isolation structure (72) extends into the fin element ((24)/(24’))
The limitation “and is spaced apart from the metal line by the fin element” is necessarily fulfilled by the incorporation of the teachings of Lu into Xie II.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lu into the method of Xie II such that it further comprises replacing the first dummy gate structure with a gate isolation structure, wherein the gate isolation structure extends into the fin element and is spaced apart from the metal line by the fin element. This would be due to the fact that doing so would reduce parasitic capacitance and leakage current between features (Lu, Paragraph [0011] and [0064]).
Claims 21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Pub. 2024/0297167), hereinafter Xie III, in view of Xie II (U.S. Pub. 2023/0093101).
Regarding Claim 21, Xie III teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]), comprising:
forming an active region (‘nanosheet region’ (20); Fig. 1, Paragraph [0069]) over a substrate ((102); Fig. Figs. 2A-2C, Paragraph [0072]), wherein the substrate includes a first cell region (Corresponding to NFET (12); Fig. 1, Paragraph [0069]- later identified as right three stacks of Fig. 8C) and a second cell region (Corresponding to PFET (16); Fig. 1, Paragraph [0069]- later identified as left three stacks of Fig. 8C), and the active region includes alternating first and second semiconductor layers ((110) and (112); Figs. 3A-3C, Paragraph [0079]) over a fin element ((106); Figs. 3A-3C, Paragraph [0072]);
etching the active region to form a first recess in the first cell region and the second recess in the second cell region (corresponding to right of center (840) and left of center (840), respectively; Fig. 8C, Paragraph [0107]);
forming a first sacrificial layer in the first recess and a second sacrificial layer in the second recess (corresponding to right of center (920) and left of center (920), respectively; Fig. 9C, Paragraph [0110]);
forming a first source/drain feature over the first sacrificial layer and a second source/drain feature over the second sacrificial layer (corresponding to right of center (930) and left of center (930), respectively; Fig. 9C, Paragraph [0110]);
forming an isolation structure along a boundary between the first cell region and the second cell region ((1040); Fig. 10C, Paragraph [0122]);
removing the first semiconductor layers (with formation of gate structure (1010); Fig. 10C, Paragraph [0120]), wherein the second semiconductor layers in the first cell region ((112) in three right stacks, corresponding to (12)) form first nanostructures (necessarily, removal of (110) and deposition of gate (1010) creates GAA transistors) and the second semiconductor layers in the second cell region ((112) in three left stacks, corresponding to (16)) form second nanostructures (necessarily, removal of (110) and deposition of gate (1010) creates GAA transistors);
removing the substrate ((Fig. 12C, Paragraph [0129]);
forming a first contact plug ((1710) on the right; Fig. 17C, Paragraph [0141]) through the first sacrificial layer (via opening (1602) on the right; Paragraph [0141]) and on the first source/drain feature (right (930));
forming a second contact plug ((1710) on the left; Fig. 17C, Paragraph [0141]) through the second sacrificial layer (via opening (1602) on the left) and on the second source/drain feature (left (930)); and
forming a metal line ((1720); Fig. 17C, Paragraph [0142]) on the first contact plug and the second contact plug ((1710) on right and left, respectively).
Xie III does not explicitly teach:
- forming a first contact plug through the fin element
-forming a second contact plug through the fin element
Xie II teaches a method for forming a semiconductor structure (method (1200) of structure; Fig. 12, Paragraphs [0069]), comprising:
-forming a contact plug ((1105); Fig. 11A, Paragraph [0066]). ((1270) of Fig. 12)
through a fin element ((100); Fig. 9A-11A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Xie II into the device of Xie III such that the method further comprised forming a first contact plug through the fin element and forming a second contact plug through the fin element. Futhermore, the incorporation would be done such that a bottom portion of the first contact plug is wider than an upper portion of the first contact plug in a cross-sectional view (Xie II, (1105) corresponding to the top contacting the via (1115) and the bottom contacting the source/drain (605); Fig. 11A). This would be due to the fact that doing so would produce the expected result of self-aligned contacts while also offering a lower resistance of buried power rails (Xie II, Paragraph [0033]).
Regarding Claim 23, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-the isolation structure (Xie III, (1040)) is separated from the metal line (Xie II, ‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]) by the fin element (Xie II, (100)). (Necessarily by incorporation of Xie II).
Regarding Claim 24, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-the first sacrificial layer (Xie III, right (930)) is made of a different material (Xie III, e.g. AlOx, Paragraph [0112]) than the fin element (Xie II, (100) is silicon; Paragraph [0037]), and the second sacrificial layer (Xie III, left (930)) is made of a different material (Xie III, e.g. AlOx, Paragraph [0112]) than the fin element (Xie II, (100) is silicon; Paragraph [0037]).
Regarding Claim 25, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-a bottom portion of the first contact plug is wider than an upper portion of the first contact plug in a cross-sectional view (Xie II, (1105) corresponding to the top contacting the via (1115) and the bottom contacting the source/drain (605); Fig. 11A).
Regarding Claim 26, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, wherein:
-a top surface of the isolation structure (Xie III, top of (1040), Fig. 10C) is higher than a top of the first source/drain feature (Xie III, top of right (930), Fig. 10C), and a bottom surface of the isolation structure(Xie III, bottom of (1040), Fig. 10C) is lower than a bottom of the first source/drain feature (Xie III, top of right (930), Fig. 10C).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Xie III and Xie II as supported by Lu.
Regarding Claim 22, Xie III as modified by Xie II teaches a method for forming a semiconductor structure ((1200); Fig. 12, Paragraph [0069]) of Claim 21, but after modification the method does not teach:
- the isolation structure (Xie III, (1040)) is interfaced with the metal line (Xie II, ‘buried power rail’ (1125) made of e.g. Cu; Fig. 11A, Paragraph [0067]). As the incorporation of the teachings of Xie II expands the fin element and changes the connection structure.
Xie III originally teaches:
-the isolation structure (Xie III, (1040)) is interfaced (understood as in direct contact with, sharing an interface) with the metal line (Xie III, (1720)) See Fig. 17C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reincorporate the teachings of Xie III into the Xie III as modified by Xie II such that the isolation structure is interfaced with the metal line. This would be due to the fact that doing so would provide for a separation of NFET and PFET cells and flexibility in cell height (Xie III, Paragraphs [0142] and [0146]). Furthermore, it is known that the deeper (longer) an isolation feature is through a semiconducting portion, the more effective it is at reducing leakage current (Lu, Paragraphs [0039] and [0040]). One of ordinary skill of the art would recognize, therefore, that the length of the isolation structure is a result effective variable in relation to leakage current, and to expand the isolation structure such that it is interfaced with the metal line would be under length considerations.
Conclusion
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/D.M./ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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