Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I in the reply filed on 09/30/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamauchi, U.S. Patent 5,065,201.
Yamauchi shows the invention as claimed including a semiconductor device comprising:
A substrate;
A transistor comprising a gate electrode (for example, floating gate 4) disposed on the substrate; and
A capacitor (5,6) electrically connected to the transistor and comprising a capacitor dielectric and a capacitor electrode, wherein the capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor (see figs. 1-2 and col. 2-line 40 to col. 3-line 25).
Concerning dependent claim 2, note that Yamauchi discloses wherein at least one of the capacitor electrodes (5 or 6) vertically overlaps the gate electrode of the transistor (see fig. 2).
With respect to dependent claim 3, note that Yamauchi discloses wherein the gate electrode 4 of the transistor is electrically floating (see fig. 2).
Regarding dependent claim 5, note that Yamauchi discloses wherein the capacitor dielectric is spaced apart from the substrate and between electrodes 5 and 6 (see fig. 2).
With respect to dependent claim 6, Yamauchi discloses the semiconductor device further comprising: a spacer (see layer 8 disposed on sidewalls of gate electrode 4) disposed on a sidewall of the gate electrode of the transistor, wherein the capacitor electrode 5 is disposed on the spacer.
Concerning dependent claim 7, note that Yamauchi discloses wherein the capacitor electrode (both electrodes 5 and 6) is conformally disposed on the spacer.
Claim(s) 10-14, 16, and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim, US Patent 6,246,084.
Kim shows the invention as claimed including a semiconductor device, comprising:
A substrate 31;
A first gate dielectric 33 disposed on the substrate;
A first semiconductor layer 34 disposed on the first gate dielectric;
An insulation layer 39 disposed on the first semiconductor layer; and
A metal structure 43a disposed on the insulation layer, wherein the first semiconductor layer functions as a first electrode of a capacitor, and the metal structure function as a second electrode of the capacitor (see figs. 3a-3f and col. 3-line 44 to col. 4-line 37).
With respect to dependent claim 11, note that Kim discloses a capacitor contact 44 electrically connected to the second electrode of the capacitor and spaced apart from the substrate (see fig. 3g).
Concerning dependent claim 12, Kim discloses: a second semiconductor layer 35 disposed on the substrate and spaced apart from the first semiconductor layer 34; and a contact (43,44) electrically connected to the second semiconductor layer, wherein a lower surface of the contact is lower than a lower surface of the capacitor contact 44 (see fig. 3g).
As to dependent claim 13, note that when giving the claim its broadest reasonable interpretation Kim discloses wherein an elevation of the second semiconductor layer 35 is substantially the same as an elevation of the first semiconductor since the word substantially
With respect to dependent claim 14, Kim discloses wherein the capacitor contact 44 is in contact with the second electrode of the capacitor 43a (see fig. 3g).
Concerning dependent claim 16, note that in Kim a portion of the first semiconductor layer is exposed from the metal structure.
With respect to independent claim 21, Kim shows the invention as claimed including a semiconductor device, comprising:
A substrate 31;
A first semiconductor layer (34 or 35) formed on the substrate;
A capacitor dielectric 39 formed on the first semiconductor layer; and
A metal structure 43a formed on the capacitor dielectric, wherein the first semiconductor layer 35 functions as a first electrode of a capacitor, and the metal structure 43a function as a second electrode of a capacitor (see figs. 3a-3f and col. 3-line 44 to col. 4-line 37).
Regarding dependent claim 22, note that Kim discloses: a conductive layer formed on the capacitor dielectric 39, wherein the conductive layer is patterned to form the metal structure 43a covering the first semiconductor layer 35 (see fig. 3g).
With respect to dependent claim 23, Kim further comprises: a second semiconductor layer formed on the substrate; and a silicide layer formed on the second semiconductor layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi, U.S. Patent 5,065,201 in view of Kim, U.S. Patent 6,246,084.
Yamauchi is applied as above but does not expressly disclose a capacitor contact disposed on the capacitor electrode. Kim discloses a capacitor contact 44 disposed on a capacitor electrode (for example, 43). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yamauchi so as to comprise a capacitor contact on one of the capacitor electrodes as disclosed by Kim because in such a way communication between adjacent capacitor and memory devices can be facilitated.
Regarding dependent claim 8, Yamauchi is applied as above but does not expressly disclose wherein the transistor comprises a first contact and a second contact arranged along a first orientation, and the capacitor electrode extends from the gate electrode to the spacer along a second orientation different from the first orientation. However, Yamauchi does disclose where the capacitor electrode extends from the gate electrode in a horizontal orientation. Kim discloses wherein the transistor comprises a first contact and a second contact arranged along a vertical orientation that is different than the horizontal orientation (see, for example, fig. 2 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yamauchi so as to comprise a transistor contact having a different vertical orientation as shown by Kim because in such a way an effective transistor-capacitor device combination feature can be realized.
As to dependent claim 9, Yamauchi does not expressly disclose wherein the capacitor contact is disposed along the claimed second orientation. However, a prima facie case of obviousness still exists because rearrangement of parts has been held to have been obvious.
Claim(s) 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, U.S. Patent 6,246,084.
Kim is applied as above but does not expressly disclose wherein a width of the metal structure exceeds a width of the first semiconductor along an X-axis. However, a prima facie case of obviousness has been established because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Concerning dependent claim 17, Kim is applied as above but does not expressly disclose where the metal structure covers a portion of a lateral surface of the first semiconductor layer. However, a prima facie case of obviousness still exists because rearrangement of parts has been held to have been obvious. Additionally, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim so as to have a metal structure that covers a portion of a lateral surface of the first semiconductor layer because this particular semiconductor/metal configuration is a well-known configuration for array-based memory structures.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kunishima, U.S. Patent 6,121,649 discloses an upper electrode of a capacitor composed of metal (see, for example, col. 4-lines 51-58), and Lee et al., U.S. Patent 6,080,615 discloses a capacitor/transistor combination (see abstract) but fails to show the upper electrode composed of metal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
November 30, 2025