Prosecution Insights
Last updated: October 02, 2026
Application No. 18/348,064

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING

Final Rejection §103
Filed
Jul 06, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1149 granted / 1361 resolved
+16.4% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
31 currently pending
Career history
1398
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
64.5%
+24.5% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1361 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2017/0194149) in view of Kim et al (US Publication No. 2013/0277720)and Guler et al (US Publication No. 2022/0399445). Regarding claim 21, Chang discloses a method comprising: forming a gate structure Fig 1L, 185/180;forming a trench adjacent to the gate structure Fig 1L, forming a spaced apart projections separated by recesses Fig 1J, wherein each projection has an uppermost surface Fig 1J, and wherein the uppermost surfaces of the projections located nearer to the gate structure are located at a greater depth than the uppermost surfaces of the projections located at a center of the trench Fig 1J; and forming a dielectric material in the trench Fig 1J. Chang discloses all the limitations but silent on a trench bottom surface including spaced apart projections. Whereas Kim discloses forming a trench Fig 10, wherein the trench has a trench bottom surface including spaced apart projections separated by recesses Fig 10, wherein each projection has an uppermost surface Fig 10. Chang and Kim are analogous art because they are directed to finfets and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Chang and incorporate the teachings of Kim as an alternative method that would improve device processing. Chang discloses all the limitations but silent on layers included in the gate structure. Whereas Guler discloses a gate structure comprising a gate dielectric, work function metal overlying the gate dielectric, and a metal gate electrode layer overlying the work function metal Fig 1B ¶0045;forming a trench adjacent to the gate structure by etching through the metal gate electrode layer, the work function metal, and the gate dielectric of the gate structure Fig 1B. Chang and Guler are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Chang and incorporate the teachings of Guler as an alternative gate structure known in the art. Regarding claim 22, Chang discloses a vertical depth of each uppermost surface, measured from the top surface of the gate structure, is less than 170 nanometers (nm) ¶0019. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the depth of the recess, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). Regarding claim 23, Kim discloses wherein each recess has a lowest surface, and wherein the lowest surfaces are located at depths within ten percent of one another Fig 10. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the depth of the recess in Chang as taught by Kim, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2017/0194149) in view of Kim et al (US Publication No. 2013/0277720), Guler et al (US Publication No. 2022/0399445) and Huang et al (US Publication No. 2022/0301922). Regarding claim 24, Chang discloses all the limitations but silent on the forming of source and drain regions. Whereas Huang discloses recessing fins in source and drain regions and forming epitaxial source and drain features over the recessed fins ¶0049-0050 Fig 10D. Chang and Huang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Chang and incorporate the teachings of Huang as an alternative method in forming the source and drain regions of the device. Allowable Subject Matter Claims 9-16, 25-33 are allowed over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “the etching process etches the fins to remove the fins and etches material under the fins to form recesses with trench bottom surfaces at first depths; the etching process etches the isolation layer segments to form projections having uppermost surfaces at second depths; and the first depths are deeper than the second depths”, as recited in independent claim 9 and “forming a semiconductor layer over the gate structure; forming a hard mask over the semiconductor layer; performing a first etching process to form an opening by etching through the hardmask and the semiconductor layer and landing on the conductive layer, wherein the hardmask protects the gate structure outside the opening; and performing a second etching process to etch through the conductive layer, the work function metal, and the gate dielectric to expose the active regions and the isolation regions”, as recited in independent claim 25. Claims 10-16, 26-33 are also allowed as being directly or indirectly dependent of the allowed independent base claims. Response to Arguments Applicant’s arguments with respect to claims 21-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811
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Prosecution Timeline

Jul 06, 2023
Application Filed
Dec 11, 2025
Non-Final Rejection (signed) — §103
Feb 05, 2026
Non-Final Rejection mailed — §103
Feb 20, 2026
Interview Requested
Mar 23, 2026
Applicant Interview (Telephonic)
Mar 23, 2026
Examiner Interview Summary
May 18, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751029
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH POWER RAIL
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Patent 12751039
CONTACT STRUCTURE WITH ARCHED TOP SURFACE AND FABRICATION METHOD THEREOF
3y 8m to grant Granted Sep 29, 2026
Patent 12745413
SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 1m to grant Granted Sep 22, 2026
Patent 12745414
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 9m to grant Granted Sep 22, 2026
Patent 12733200
NON-EPITAXIAL ELECTRICAL COUPLING BETWEEN A FRONT SIDE TRENCH CONNECTOR AND BACK SIDE CONTACTS OF A TRANSISTOR
4y 5m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
95%
With Interview (+10.3%)
1y 12m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1361 resolved cases by this examiner. Grant probability derived from career allowance rate.

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