DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The 112 rejections are overcome by the claim amendments.
The amended claims read on Kim with layer 135 being the storage gate layer. See the rejections below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, and 9 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim, CN 101286514 A.
Note: the references to Kim are to the attached machine translation.
Claim 1: Kim discloses
a semiconductor substrate comprising a plurality of fin-type structures (105a and 105b);
a select transistor formed on the semiconductor substrate, the select transistor comprising a gate layer (135) disposed over a first dielectric isolation layer (130) that is positioned over a first section of the plurality of fin-type structures, wherein the select transistor is a P-channel metal oxide semiconductor (PMOS) transistor; “selection transistor ST may include a MOSFET (MOS field effect transistor)” (page 4 second to last paragraph); “the first conductivity type and the second conductivity type may be any type selected from n-type and p-type.” (page 7 first paragraph)
and a storage device formed on the semiconductor substrate, the storage device comprising a storage gate layer (135) disposed over a second dielectric isolation layer (130) that is positioned over a second section on the plurality of fin-type structures, wherein the storage gate layer is a charge-trapping dielectric material configured to trap charges within the storage gate layer (“charge storage layers 135a and 135b may correspond to storage node SN of FIG. 1, and may include … a nitride layer”), and wherein the storage device is a P-channel storage device;
wherein the select transistor is coupled to the storage device;
it is coupled in the sense it selects the string that the storage device is in.
and wherein the first section of the plurality of fin-type structures is adjacent to the second section of the plurality of fin-type structures (FIG. 2).
Claim 2: the first dielectric isolation layer comprises a high-κ dielectric material: : Kim discloses that “tunnelling insulation layers 130a and 130b and the blocking insulating layer 140 may include an oxide layer, a nitride layer or a high dielectric layer (high-k).” (page 6, second to last paragraph.)
Claim 6: the trapped charges are electrons. “FIG. 15 and FIG. 16 is a simulated perspective view of electron concentration distribution of experimental examples of non-volatile memory device”, showing electron flow into the memory device. (page 9 paragraph 6.)
Claim 9: those in the art would recognize that the storage device is arranged to store a bit of information, as that is what the elements of all such non-volatile memory devices are for. It was well understood that each memory cell was to store a single bit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Son, US 2017/0098656 A1.
Claims 3 and 7: Kim discloses that “tunnelling insulation layers 130a and 130b and the blocking insulating layer 140 may include an oxide layer, a nitride layer or a high dielectric layer (high-k).” (page 6 second to last paragraph.) The claimed materials were known high-k dielectrics. See e.g. Son [0075]: “high-k dielectric layer (e.g., an aluminum oxide (Al2O3) layer or a hafnium oxide (HfO2) layer)”. It would have been obvious to use hafnium oxide as a known high-k dielectric.
Claim 5: The claimed materials were known gate materials. See e.g. Son [0136]: “the gate metal layer 159 may include a metal material (e.g., tungsten).” It would have been obvious to have used this in Kim as a known material used for a known purpose.
Claim 8: Kim discloses a “bulk semiconductor wafer” (page 6 paragraph 4). Kim does not disclose specifically that it is a silicon wafer, but those in the art would have understood that silicon was the most common type of bulk wafer and would have been obvious to use. See also Son [0065], “silicon wafer”.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Huang, US 2005/0083738 A1. Kim does not disclose that the storage device is configured to be programmed by a sub-threshold current flowing through a channel of the storage device when the storage device is in an off-state during a programming operation, wherein the sub-threshold current induces hot carrier injection into the storage gate layer. However, Huang at [0035] discloses that “[d]uring the programming operation, the negative drain voltage Vdd is applied to the drain region and the gate voltage Vg is around the threshold voltage Vt that dependent on the design, wherein the threshold voltage Vt in the preferred embodiment is around -4 volts. Due to the drain voltage Vdd is higher than the threshold voltage Vt to induce the hot electron injection from channel through the tunneling oxide layer into the floating gate, such that the electrons are hold in the floating gate. Furthermore, the bias would only allow a sub-threshold current flow in the flash cell during the programming operation, such that the injection efficiency is high for this flash cell and the power consumption of the integration circuit device would be lowered.” It would have been obvious to configure the device of Kim in this way to achieve this benefit, that is, lower power consumption.
Claims 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Huang and Yaegashi, US 2001/0000625 A1.
Claim 16 recites a NOR non-volatile memory (NVM). While Kim discloses a NAND device. However, it was well-understood that they same NVM technology could be adapted to different memory types. See e.g., Yaegashi, FIG. 32 showing a NAND device, and FIG. 33 showing a NOR device. Those in the art would have known that it would have been straightforward to adapt the device of Kim to a NOR configuration.
Thus a NOR device of Kim in view of Yaegashi (FIG. 33) would have:
a semiconductor substrate comprising a plurality of fin-type structures (105a and 105b);
a memory array formed in the semiconductor substrate and comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of memory cells consists of a select transistor (connected to SG) and a storage device (connected to CG);
a plurality of word lines (horizontal lines connected to CG) electrically connected to the plurality of rows, respectively;
a plurality of source lines (VS) electrically connected to the plurality of columns, respectively;
and a plurality of bit lines (BL) electrically connected to the plurality of columns, respectively;
and wherein, as disclosed by Kim:
the select transistor is formed on the semiconductor substrate, the select transistor comprising a gate layer (135) disposed over a first dielectric isolation layer (130) that is positioned over a first section of the plurality of fin-type structures, wherein the select transistor is a P-channel metal oxide semiconductor (PMOS) transistor (“selection transistor ST may include a MOSFET (MOS field effect transistor)” (page 4 second to last paragraph); “the first conductivity type and the second conductivity type may be any type selected from n-type and p-type.” (page 7 first paragraph.)
and the storage device is formed on the semiconductor substrate, the storage device comprising a storage gate layer (135) disposed over a second dielectric isolation layer (130) that is positioned over a second section on the plurality of fin-type structures, wherein the storage gate layer is a charge-trapping dielectric material configured to trap charges within the storage gate layer, and wherein the storage device is a P-channel storage device; (“the first conductivity type and the second conductivity type may be any type selected from n-type and p-type.” page 7 first paragraph);
the select transistor is coupled to the storage device (it is coupled in the sense it selects the string that the storage device is in);
the first section of the plurality of fin-type structures is adjacent to the second section of the plurality of fin-type structures (Kim FIG. 2);
Kim does not disclose that the storage device is configured to be programmed by a sub-threshold current flowing through a channel of the storage device when the storage device is in an off-state during a programming operation, wherein the sub-threshold current induces hot carrier injection into the storage gate layer. However, Huang at [0035] discloses that “[d]uring the programming operation, the negative drain voltage Vdd is applied to the drain region and the gate voltage Vg is around the threshold voltage Vt that dependent on the design, wherein the threshold voltage Vt in the preferred embodiment is around -4 volts. Due to the drain voltage Vdd is higher than the threshold voltage Vt to induce the hot electron injection from channel through the tunneling oxide layer into the floating gate, such that the electrons are hold in the floating gate. Furthermore, the bias would only allow a sub-threshold current flow in the flash cell during the programming operation, such that the injection efficiency is high for this flash cell and the power consumption of the integration circuit device would be lowered.” It would have been obvious to configure the device of Kim in this way to achieve this benefit, that is, lower power consumption.
Claim 17: Kim discloses that “tunnelling insulation layers 130a and 130b and the blocking insulating layer 140 may include an oxide layer, a nitride layer or a high dielectric layer (high-k).” (page 6, second to last paragraph.)
Claim 19: the trapped charges are electrons. “FIG. 15 and FIG. 16 is a simulated perspective view of electron concentration distribution of experimental examples of non-volatile memory device” (page 9 paragraph 6), showing electron flow into the memory device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Son, US 2017/0098656 A1. Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Son, Huang and Yaegashi.
Claim 8: Kim discloses a “bulk semiconductor wafer”. Kim does not disclose specifically that it is a silicon wafer, but those in the art would have understood that silicon was the most common type of bulk wafer and would have been obvious to use. See also Son [0065], “silicon wafer”.
Claim 18: Kim discloses that “tunnelling insulation layers 130a and 130b and the blocking insulating layer 140 may include an oxide layer, a nitride layer or a high dielectric layer (high-k).” (page 6, second to last paragraph.) The claimed materials were known high-k dielectrics. See e.g. Son [0075]: “high-k dielectric layer (e.g., an aluminum oxide (Al2O3) layer or a hafnium oxide (HfO2) layer)”. It would have been obvious to use hafnium oxide as a known high-k dielectric.
Claim 20: The claimed materials were known gate materials. See e.g. Son [0136]: “the gate metal layer 159 may include a metal material (e.g., tungsten).” It would have been obvious to have used this in Kim as a known material used for a known purpose.
Allowable Subject Matter
Claims 21-26 are allowed.
The following is an examiner’s statement of reasons for allowance: The examiner did not find a device with all the features of claim 21, with two storage devices respectively coupled to the first and second S/D layers on either side of the select transistor as claimed, in light of the overall claimed device.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure and is listed in the attached Notice of References Cited.
35.Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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