DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Group I and Species B, identified as encompassing claims 1-5, 11-20, and 21-25 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1, 5, 11, 12, 13, 18-21, and 23-24 are rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Ping et al. (US 2008/0062596 A1), hereinafter as P1
5. Regarding Claim 1, P1 discloses a semiconductor structure (see Fig. 5D and [0021] “ESD protection circuit 300 may be fabricated using … high electron mobility transistor (HEMT)”), comprising:
a source and a drain in a substrate (see Fig. 5B source and drain of transistor element 360 and [0021] “ESD protection circuit 300 is formed on a Gallium Arsenide (GaAs) substrate” and [0023] “transistor shunt element 360 … HEMT”);
a gate of a gallium nitride (GaN) high-electron-mobility transistor (HEMT) device (gate of element 360) configured to control a channel between the source and the drain; and
a resistor (element R1, see [0034] “resistor R1”) between the gate and a circuit (element 330, see [0034] “triggering element 330 comprises a plurality of diodes D1, D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350”) on the substrate (see [0021]).
6. Regarding Claim 5, P1 discloses the semiconductor structure of claim 1, wherein the circuit is a clamp circuit (see Fig. 5D and [0034] The voltage is clamped when triggered by a high voltage), and wherein the resistor is connected in parallel with a transistor of the clamp circuit (see Fig. 5D)
7. Regarding Claim 11, P1 discloses a semiconductor device (see Fig. 5D and [0021] “ESD protection circuit 300 may be fabricated using … high electron mobility transistor (HEMT)”), comprising:
a source and a drain in a substrate (see Fig. 5B source and drain of transistor element 360 and [0021] “ESD protection circuit 300 is formed on a Gallium Arsenide (GaAs) substrate” and [0023] “transistor shunt element 360 … HEMT”);
a gate (gate of element 360) configured to control a channel between the source and the drain;
a clamp circuit (see Fig. 5D element 330 and [0034] The voltage is clamped when triggered by a high voltage; note, the clamp circuit comprises a series of diodes in the same manner as the Applicant’s invention) on the substrate and configured to perform electrostatic discharge (ESD) (see [0040] “ESD protection circuit 300”); and
a resistor (element R1, see [0034] “resistor R1”) between the gate and the clamp circuit (see Fig. 5D).
8. Regarding Claim 12, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit comprises a static clamp (see Fig. 5D element 330 and [0034] The voltage is clamped when triggered by a high voltage; note, the clamp circuit comprises a series of diodes in the same manner as the Applicant’s invention).
9. Regarding Claim 13, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit comprises a series of diodes configured to control a field-effect transistor (see [0034] “triggering element 330 comprises a plurality of diodes D1, D2, through DN”).
10. Regarding Claim 18, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit comprises a forward diode connected to a field-effect transistor (see Fig. 5D one of the elements D1-Dn).
11. Regarding Claim 19, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit is configured to perform the ESD based on a voltage threshold (see [0038-0039] “the plurality of diodes D1, D2, through DN, of triggering element 330 provide for controlling or setting the turn-on voltage of transistor shunt element 360” and “during a negative ESD event, shut-off element 340 becomes the element that turns-on transistor shunt element 360”).
12. Regarding Claim 20, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit is configured to perform the ESD based on a time constant (see Fig. 5D and [0038-0039]; note, the current claim is directed towards a device, for which the prior art discloses all the claimed structural limitations capable of performing the functional language “configured to perform the ESD based on a time constant”).
13. Regarding Claim 21, P1 discloses a semiconductor device (see Fig. 5D and [0021] “ESD protection circuit 300 may be fabricated using … high electron mobility transistor (HEMT)”), comprising:
a contact (contact between 320 and source of element 360, see [0029] “the drain of transistor shunt element 360 is coupled with terminal 310, the source of transistor shunt element 360 is coupled with terminal 320”) over a source of a gallium nitride (GaN) high-electron-mobility transistor (HEMT) device (element 360, see [0023] “transistor shunt element 360 is an enhancement-mode pHEMT”);
a resistor (element R1, see [0034] “resistor R1”) electrically connected to a gate of the GaN HEMT device (see Fig. 5D); and
a clamp circuit (element 330, see [0034] “triggering element 330 comprises a plurality of diodes D1, D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350” The voltage is clamped when triggered by a high voltage) electrically connected to the contact and to the resistor (see Fig. 5D).
14. Regarding Claim 23, P1 discloses the semiconductor device of claim 21, further comprising: a control device connected to an input/output of the clamp circuit (see [0022] “terminal 310 may be coupled with a device or an integrated circuit to be protected from an ESD event … terminal 310 may be coupled with a bond pad, input/output pin or any other connection associated with ESD protection circuit 300”).
15. Regarding Claim 24, P1 discloses the semiconductor device of claim 21, wherein the resistor contacts the gate of the GaN HEMT device (see Fig. 5D).
16. Claim(s) 21,25 are rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Ping et al. (US 2008/0062596 A1), hereinafter as P1
17. Regarding Claim 21, P1 discloses a semiconductor device (see Fig. 5G and [0021] “ESD protection circuit 300 may be fabricated using … high electron mobility transistor (HEMT)”), comprising:
a contact (contact between 320 and source of element 360, see [0029] “the drain of transistor shunt element 360 is coupled with terminal 310, the source of transistor shunt element 360 is coupled with terminal 320”) over a source of a gallium nitride (GaN) high-electron-mobility transistor (HEMT) device (element 360, see [0023] “transistor shunt element 360 is an enhancement-mode pHEMT”);
a resistor (element R1, see [0037] “resistor R1”) electrically connected to a gate of the GaN HEMT device (see Fig. 5G); and
a clamp circuit (element 330, see [0037] “triggering element 330 comprises a gate-source-coupled transistor 370 coupled with a plurality of diodes D1, D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350” The voltage is clamped when triggered by a high voltage) electrically connected to the contact and to the resistor (see Fig. 5G).
Regarding Claim 25, P1 discloses the semiconductor device of claim 21, wherein the clamp circuit comprises a field-effect transistor (FET) (see Fig. 5G element 370 and [0037] “transistor 370”), and wherein the resistor is connected in parallel with the FET (see Fig. 5G).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claim 2 is rejected under 35 U.S.C. 103 as obvious over Ping et al. (US 2008/0062596 A1), hereinafter as P1, in view of Pendharkar et al. (US 2014/0327010 A1), hereinafter as P2
19. Regarding Claim 2, P1 discloses the semiconductor structure of claim 1.
P1 does not disclose wherein the resistor comprises a silicon resistor.
P2 discloses wherein the resistor comprises a silicon resistor (see Fig. 1 and 9, [0056] “voltage dropping component in the form of a well resistor 928 is formed in the silicon substrate 902” and [0023] “voltage dropping component 120”).
The type of resistor as taught by P2 is incorporated as the type of resistor of P1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P2 with P1 because the combination provides a desired on-state bias of a gate node for overvoltage clamping (see P2 [0023]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see P2 Figs. 1 and 9).
20. Claim 3 is rejected under 35 U.S.C. 103 as obvious over Ping et al. (US 2008/0062596 A1), hereinafter as P1, in view Chen et al. (US 2014/0264751 A1), hereinafter as C1
21. Regarding Claim 3, P1 discloses the semiconductor structure of claim 1.
P1 does not disclose wherein the resistor comprises a metal nitride resistor.
C1 discloses wherein the resistor comprises a metal nitride resistor (see [0045-0046] “The resistor metal layer may include TiN, TaN”)
The type of resistor as taught by C1 is incorporated as the type of resistor of P1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with P1 because the combination provides a precise resistance resistor (see C1 [0045]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see C1 [0045-0046]).
22. Claim 4 is rejected under 35 U.S.C. 103 as obvious over Ping et al. (US 2008/0062596 A1), hereinafter as P1, in view of Knoedgen et al. (US 10,103,633 B1), hereinafter as K1
23. Regarding Claim 4, P1 discloses the semiconductor structure of claim 1.
P1 does not disclose wherein the resistor comprises a GaN resistor.
K1 discloses wherein the resistor comprises a GaN resistor (see Column 2 lines 6-9 “The resistor may be a … GaN resistor”).
The type of resistor as taught by K1 is incorporated as the type of resistor of P1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with P1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
24. Claims 14-17 are rejected under 35 U.S.C. 103 as obvious over Ping et al. (US 2008/0062596 A1), hereinafter as P1, in view of Kumar et al. (US 2019/0267801 A1), hereinafter as K2
25. Regarding Claim 14, P1 discloses the semiconductor device of claim 11.
P1 does not disclose wherein the clamp circuit comprises a capacitor-resistor clamp
K2 discloses wherein the clamp circuit comprises a capacitor-resistor clamp (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of P1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with P1 because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
26. Regarding Claim 15, P1 discloses the semiconductor device of claim 11.
P1 does not disclose wherein the clamp circuit comprises a resistor-capacitor clamp.
K2 discloses wherein the clamp circuit comprises a resistor-capacitor clamp (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of P1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with P1 because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
27. Regarding Claim 16, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit is configured to control a field-effect transistor (see Fig. 5D configured to control element 360, see [0034])
P1 does not disclose wherein the clamp circuit comprises a capacitor and a resistor.
K2 discloses wherein the clamp circuit comprises a capacitor and a resistor (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of P1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with P1 because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
28. Regarding Claim 17, P1 discloses the semiconductor device of claim 11, wherein the clamp circuit is configured to control a field-effect transistor (see Fig. 5D configured to control element 360, see [0034])
P1 does not disclose wherein the clamp circuit comprises an inverter.
K2 discloses wherein the clamp circuit comprises an inverter (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of P1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with P1 because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
29. Claim 22 is rejected under 35 U.S.C. 103 as obvious over Ping et al. (US 2008/0062596 A1), hereinafter as P1, in view of Kinzer (US 2016/0049786 A1), hereinafter as K1
30. Regarding Claim 22, P1 discloses the semiconductor device of claim 21, further comprising: an additional contact over a drain (additional contact between element 310 and the drain of element 360 see [0029]) of the GaN HEMT device.
P1 does not disclose wherein the additional contact is connected to ground.
K1 discloses wherein the additional contact is connected to ground (see Fig. 3A bottom source side is connected to ground and see [0042] “source terminal 120 (i.e., ground)”)
The transistor type with source connected to ground as taught by K1 is incorporated as the transistor type with source connected to ground of P1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with P1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source and drain orientation for another in a similar device to obtain predictable results (see K1 Fig. 3A and [0036]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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