DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on August 18, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 7-9, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 7-9, regarding the newly presented amendments:
The Examiner notes that new combination of prior arts are presented in light of the newly amended claim limitations such that arguments directed solely to the previously present prior art combinations are now moot.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 5, 11-13, 18-21, and 23-25 is rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1
6. Regarding Claim 1, M1 discloses a semiconductor structure (see Fig. 4 and [0035] “semiconductor power switching device”), comprising:
a target device (element Qmain, see [0046] “e-mode GaN HEMTs, which are represented by power transistor switch Qmain”) comprising:
a source (element “Source”, see [0046]) and a drain (element “Drain”, see [0046]) in a substrate (see [0044] “semiconductor substrate”); and
a gate (element “G”, see [0046]) configured to control a channel between the source and the drain (see [0046] “An e-mode GaN HEMT is capable of gate controlled forward and reverse conduction, to provide a bidirectional ESD discharge path.”),
wherein the target device is a gallium nitride (GaN) high-electron-mobility transistor (HEMT) device (see [0046]);
a clamp circuit (element ESD protection circuit), wherein the clamp circuit comprises a transistor (element Q1, see [0046] “clamp transistor Q1”); and
configured to prevent an electrostatic discharge (ESD) current from flowing across the gate during an ESD event (see [0046] “When either of the positive or negative trigger circuits conduct to turn-on the gate of clamp transistor Q1, it is the clamp transistor Q1 that conducts the majority of the current to provide a discharge path which dissipates an ESD event”).
M1 does not explicitly disclose the clamp circuit on the substrate; a resistor between the gate of the target device and the clamp circuit; wherein the resistor is configured to prevent an ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
L1 discloses the target device and the clamp circuit on the substrate (see [0014] “an integrated circuit (IC) chip including an electrostatic discharge (ESD) protection circuit 100 integrated with a GaN based transistor 102 on a single semiconductor substrate”).
The substrate having both the target device and the clamp circuit as taught by L1 is incorporated as the substrate having both the target device and the clamp circuit of M1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for the ESD protection circuit is integrated and fabricated together with the GaN based transistor such that parasitic inductance and parasitic capacitance are reduced (see L1 [0013]).
M1, L1 do not explicitly disclose a resistor between the gate of the target device and the clamp circuit; wherein the resistor is configured to prevent an ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
T1 discloses (see Fig. 3) a resistor (element 345, see [0033] “gate resistor 345”) between the gate of the target device and the clamp circuit (between element 310 and 340 see [0033])
The resistor connected between the gate of the target device and the clamp circuit as taught by T1 is incorporated as a resistor connected between the gate of the target device and the clamp circuit of M1, L1, the combination further disclose wherein the resistor is configured to prevent and ESD current from flowing across the gate during an ESD event (the resistor provides a resistance which contributes towards preventing current flow to the gate during an ESD event), wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor (see M1 Fig. 4 between the drain of element Q1 and the gate element G of element Qmain).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for eliminated or reduced generation of oscillations by the gate resistor (see L1 [0039]).
7. Regarding Claim 5, M1, L1, T1 disclose the semiconductor structure of claim 1, wherein the resistor is connected in parallel with the transistor of the clamp circuit (see M1 Fig. 4 the combined resistor left of element G of Qmain is in parallel with element Q1)
8. Regarding Claim 11, M1 discloses a semiconductor device (see Fig. 4 and [0035] “semiconductor power switching device”), comprising:
a target device (element Qmain, see [0046] “e-mode GaN HEMTs, which are represented by power transistor switch Qmain”), comprising:
a source (element “Source”, see [0046]) and a drain (element “Drain”, see [0046]) in a substrate (see [0044] “semiconductor substrate”); and
a gate (element “G”, see [0046]) configured to control a channel between the source and the drain (see [0046] “An e-mode GaN HEMT is capable of gate controlled forward and reverse conduction, to provide a bidirectional ESD discharge path.”);
a clamp circuit (element ESD protection circuit) configured to perform electrostatic discharge (ESD) (see [0046] “When either of the positive or negative trigger circuits conduct to turn-on the gate of clamp transistor Q1, it is the clamp transistor Q1 that conducts the majority of the current to provide a discharge path which dissipates an ESD event”),
wherein the clamp circuit comprises a field-effect transistor (element Q1, see [0046] “clamp transistor Q1”); and
configured to prevent an ESD current from flowing across the gate during the ESD (see [0046]).
M1 does not explicitly disclose the clamp circuit on the substrate; a resistor between the gate of the target device and the clamp circuit; wherein the resistor is configured to prevent an ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
L1 discloses the target device and the clamp circuit on the substrate (see [0014] “an integrated circuit (IC) chip including an electrostatic discharge (ESD) protection circuit 100 integrated with a GaN based transistor 102 on a single semiconductor substrate”).
The substrate having both the target device and the clamp circuit as taught by L1 is incorporated as the substrate having both the target device and the clamp circuit of M1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for the ESD protection circuit is integrated and fabricated together with the GaN based transistor such that parasitic inductance and parasitic capacitance are reduced (see L1 [0013]).
M1, L1 do not explicitly disclose a resistor between the gate of the target device and the clamp circuit; wherein the resistor is configured to prevent an ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
T1 discloses (see Fig. 3) a resistor (element 345, see [0033] “gate resistor 345”) between the gate of the target device and the clamp circuit (between element 310 and 340 see [0033])
The resistor connected between the gate of the target device and the clamp circuit as taught by T1 is incorporated as a resistor connected between the gate of the target device and the clamp circuit of M1, L1, the combination further disclose wherein the resistor is configured to prevent and ESD current from flowing across the gate during an ESD event (the resistor provides a resistance which contributes towards preventing current flow to the gate during an ESD event), wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor (see M1 Fig. 4 between the drain of element Q1 and the gate element G of element Qmain).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for eliminated or reduced generation of oscillations by the gate resistor (see L1 [0039]).
9. Regarding Claim 12, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit comprises a static clamp (see M1 Fig. 4 and [0046]; note, the clamp circuit comprises a series of diodes and transistor in the same manner as the Applicant’s invention).
10. Regarding Claim 13, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit comprises a series of diodes configured to control the field-effect transistor (see M1 Fig. 4 and [0046] “When either of the positive or negative trigger circuits conduct to turn-on the gate of clamp transistor Q1”).
11. Regarding Claim 18, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit comprises a forward diode connected to the field-effect transistor (see M1 Fig. 4).
12. Regarding Claim 19, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit is configured to perform the ESD based on a voltage threshold (see M1 Fig. 4 and [0046] “The positive trigger voltage is set by the sum of threshold voltages of the plurality of diode elements the first diode string D1. The negative trigger voltage is set by the sum of threshold voltages of the plurality of diode elements of the second diode string D2.”).
13. Regarding Claim 20, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit is configured to perform the ESD based on a time constant (see M1 Fig. 4 and [0046]; note, the current claim is directed towards a device, for which the prior art discloses all the claimed structural limitations capable of performing the functional language “configured to perform the ESD based on a time constant”).
14. Regarding Claim 21, M1 discloses a semiconductor device (see Fig. 4 and [0035] “semiconductor power switching device”), comprising:
a contact (contact connecting to the source terminal of element Qmain, see [0046] “Qmain, having source, drain and gate terminals”) over a source of a gallium nitride (GaN) high-electron-mobility transistor (HEMT) device (element Qmain, see [0046] “e-mode GaN HEMTs, which are represented by power transistor switch Qmain”);
a clamp circuit (element ESD protection circuit),
wherein the clamp circuit comprises a field-effect transistor (element Q1, see [0046] “clamp transistor Q1”),
configured to prevent an electrostatic discharge (ESD) current from flowing across the gate of the GaN HEMT device during an ESD event (see [0046] “When either of the positive or negative trigger circuits conduct to turn-on the gate of clamp transistor Q1, it is the clamp transistor Q1 that conducts the majority of the current to provide a discharge path which dissipates an ESD event”)
The clamp circuit on the substrate; the clamp circuit electrically connected to the contact and to the resistor; a resistor between the gate of the target device and the clamp circuit; wherein the resistor is configured to prevent an ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
L1 discloses the target device and the clamp circuit on the substrate (see [0014] “an integrated circuit (IC) chip including an electrostatic discharge (ESD) protection circuit 100 integrated with a GaN based transistor 102 on a single semiconductor substrate”).
The substrate having both the target device and the clamp circuit as taught by L1 is incorporated as the substrate having both the target device and the clamp circuit of M1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for the ESD protection circuit is integrated and fabricated together with the GaN based transistor such that parasitic inductance and parasitic capacitance are reduced (see L1 [0013]).
M1, L1 do not explicitly disclose a resistor between the gate of the target device and the clamp circuit; the clamp circuit electrically connected to the contact and to the resistor; wherein the resistor is configured to prevent and ESD current from flowing across the gate during an ESD event; and wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor.
T1 discloses (see Fig. 3) a resistor (element 345, see [0033] “gate resistor 345”) between the gate of the target device and the clamp circuit (between element 310 and 340 see [0033]), the clamp circuit electrically connected to the contact and to the resistor (see Fig. 3 and [0033])
The resistor connected between the gate of the target device and the clamp circuit as taught by T1 is incorporated as a resistor connected between the gate of the target device and the clamp circuit of M1, L1, the combination further disclose wherein the resistor is configured to prevent and ESD current from flowing across the gate during an ESD event (the resistor provides a resistance which contributes towards preventing current flow to the gate during an ESD event), wherein one of a source terminal or a drain terminal of the transistor is connected to the resistor (see M1 Fig. 4 between the drain of element Q1 and the gate element G of element Qmain).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with M1 because the combination allows for eliminated or reduced generation of oscillations by the gate resistor (see L1 [0039]).
15. Regarding Claim 23, M1, L1, T1 disclose the semiconductor device of claim 21, further comprising: a control device connected to an input/output of the clamp circuit (see M1 Fig. 4 “Gate driver input” and see [0044] “I/O pin 124 of the IC chip, or is connected to a gate driver circuit”).
16. Regarding Claim 24, M1, L1, T1 disclose the semiconductor device of claim 21, wherein the resistor contacts the gate of the GaN HEMT device (see T1 Fig. 3).
17. Regarding Claim 25, M1, L1, T1 disclose the semiconductor device of claim 21, wherein the resistor is connected in parallel with the FET (see M1 Fig. 4 the combined resistor left of element G of Qmain is in parallel with element Q1).
18. Claim 2 is rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1, in view of Pendharkar et al. (US 2014/0327010 A1), hereinafter as P2
19. Regarding Claim 2, M1, L1, T1 disclose the semiconductor structure of claim 1.
M1, L1, T1 do not disclose wherein the resistor comprises a silicon resistor.
P2 discloses wherein the resistor comprises a silicon resistor (see Fig. 1 and 9, [0056] “voltage dropping component in the form of a well resistor 928 is formed in the silicon substrate 902” and [0023] “voltage dropping component 120”).
The type of resistor as taught by P2 is incorporated as the type of resistor of M1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P2 with M1 because the combination provides a desired on-state bias of a gate node for overvoltage clamping (see P2 [0023]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see P2 Figs. 1 and 9).
20. Claim 3 is rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1, in view Chen et al. (US 2014/0264751 A1), hereinafter as C1
21. Regarding Claim 3, M1, L1, T1 disclose the semiconductor structure of claim 1.
M1, L1, T1 do not disclose wherein the resistor comprises a metal nitride resistor.
C1 discloses wherein the resistor comprises a metal nitride resistor (see [0045-0046] “The resistor metal layer may include TiN, TaN”)
The type of resistor as taught by C1 is incorporated as the type of resistor of M1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with M1 because the combination provides a precise resistance resistor (see C1 [0045]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see C1 [0045-0046]).
22. Claim 4 is rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1, in view of Knoedgen et al. (US 10,103,633 B1), hereinafter as K1
23. Regarding Claim 4, M1, L1, T1 disclose the semiconductor structure of claim 1.
M1, L1, T1 does not disclose wherein the resistor comprises a GaN resistor.
K1 discloses wherein the resistor comprises a GaN resistor (see Column 2 lines 6-9 “The resistor may be a … GaN resistor”).
The type of resistor as taught by K1 is incorporated as the type of resistor of M1
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with M1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
24. Claims 14-17 are rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1in view of Kumar et al. (US 2019/0267801 A1), hereinafter as K2
25. Regarding Claim 14, M1, L1, T1 disclose the semiconductor device of claim 11.
M1, L1, T1 do not disclose wherein the clamp circuit comprises a capacitor-resistor clamp
K2 discloses wherein the clamp circuit comprises a capacitor-resistor clamp (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of M1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with M1because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
26. Regarding Claim 15, M1, L1, T1 disclose the semiconductor device of claim 11.
M1, L1, T1 do not disclose wherein the clamp circuit comprises a resistor-capacitor clamp.
K2 discloses wherein the clamp circuit comprises a resistor-capacitor clamp (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of M1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with M1because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
27. Regarding Claim 16, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit is configured to control the field-effect transistor (see Fig. 5D configured to control element 360, see [0034])
M1, L1, T1 do not disclose wherein the clamp circuit comprises a capacitor and a resistor.
K2 discloses wherein the clamp circuit comprises a capacitor and a resistor (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of M1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with M1because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
28. Regarding Claim 17, M1, L1, T1 disclose the semiconductor device of claim 11, wherein the clamp circuit is configured to control the field-effect transistor (see Fig. 5D configured to control element 360, see [0034])
M1, L1, T1 do not disclose wherein the clamp circuit comprises an inverter.
K2 discloses wherein the clamp circuit comprises an inverter (see Fig. 1 element C1, R1, see [0034] “electrostatic discharge (ESD) protection circuit … capacitor C1 … resistor R1” and see [0015] “RC timing circuit 12 is coupled to a trigger circuit (inverter) 14 comprising a p-type FET 14a and a n-type FET 14b, in series … the trigger circuit 14 generates a trigger pulse for driving the ESD clamp TN0”)
The clamp circuit as taught by K2 is incorporated as a clamp circuit of P1 (element 12,14 of K2 to replace element 330 of P1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K2 with P1 because the combination provides reduces size and reduced leakage with adequate ESD protection (see K2 [0012]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of resistor for another in a similar device to obtain predictable results (see K1 Column 2 lines 6-9).
29. Claim 22 is rejected under 35 U.S.C. 103 as obvious over Mizan et al. (US 2023/0198252 A1), hereinafter as M1, in view of Lin et al. (US 2018/0026029 A1), hereinafter as L1, in view of Treu et al. (US 2011/0227095 A1), hereinafter as T1, in view of Kinzer (US 2016/0049786 A1), hereinafter as K1
30. Regarding Claim 22, M1, L1, T1 disclose the semiconductor device of claim 21, further comprising: an additional contact over a drain (additional contact between element 310 and the drain of element 360 see [0029]) of the GaN HEMT device.
M1, L1, T1 do not disclose wherein the additional contact is connected to ground.
K1 discloses wherein the additional contact is connected to ground (see Fig. 3A bottom source side is connected to ground and see [0042] “source terminal 120 (i.e., ground)”)
The transistor type with source connected to ground as taught by K1 is incorporated as the transistor type with source connected to ground of M1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with M1because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source and drain orientation for another in a similar device to obtain predictable results (see K1 Fig. 3A and [0036]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Primary Examiner, Art Unit 2818
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