DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/11/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitations “forming a first gate stack including a gate dielectric layer disposed over the first fin; and forming a first doped layer near a surface of the first fin including beneath the first gate stack, an entirety of the first doped layer disposed within the first fin… and wherein the gate dielectric layer is separate from and free of the first doped layer” was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed. The applicant’s specification in Fig 6B and Fig 8C shows a doped fin 402 and a gate structure (with dielectric layer) 707. The specification does not show a gate dielectric layer is separated from the first doped layer. The gate dielectric layer is abutting the doped fin 402 as illustrated in Fig 6B and Fig 8C.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitations in claim 1 “forming a first gate stack including a gate dielectric layer disposed over the first fin; and forming a first doped layer near a surface of the first fin including beneath the first gate stack, an entirety of the first doped layer disposed within the first fin… and wherein the gate dielectric layer is separate from and free of the first doped layer” is unclear. It is not feasible to have the gate dielectric layer separated from the doped fin when the limitations requires the first doped layer to be beneath the first gate stack (includes the dielectric layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 6, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2022/0093472) in view of Wang et al (US Publication No. 2022/0123111).
Regarding claim 1, as best understood, Hsu discloses a method of fabricating a semiconductor device, comprising: providing a first fin extending from a substrate ¶0022; forming a first gate stack including a gate dielectric layer disposed over the first fin Fig 15; and forming a first doped layer Fig 8, 216’ along a surface of the first fin including beneath the first gate stack Fig 8 and Fig 15; wherein a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device ¶0034. Hsu discloses all the limitations but silent on the arrangement of the doped layer. Whereas Wang discloses forming a first doped layer Fig 13, 58 along near a surface of the first fin including beneath the first gate stack Fig 13, an entirety of the first doped layer disposed within the first fin Fig 13; wherein the gate dielectric layer is separate from and free of the first doped layer Fig 14B. Hsu and Wang are analogous art because they are directed to semiconductor devices having dipole layer and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of the doped layer and incorporate the teachings of Wang to improve device performance ¶0010.
Regarding claim 3, Hsu discloses wherein the first doped layer causes a current path of the semiconductor device to be moved a distance away from a channel-to-gate dielectric interface Fig 15.
Regarding claim 5, Hsu discloses wherein the forming the first doped layer includes: prior to forming the first gate stack, forming an atomic layer deposition (ALD)-deposited doped layer over the first fin ¶0031-0035; after forming the ALD-deposited doped layer, performing a drive-in anneal to cause dopants within the ALD-deposited doped layer to diffuse into the surface of the first fin to form the first doped layer ¶0032,0036; and after performing the drive-in anneal, removing a remaining portion of the ALD-deposited doped layer Fig 27.
Regarding claim 6, Hsu discloses wherein the first gate stack is formed over the first fin after the remaining portion of the ALD-deposited doped layer is removed Fig 36.
Regarding claim 8, Hsu discloses wherein the second dopant species of the source/drain feature includes an N-type dopant species, and wherein the first dopant species of the first doped layer includes at least one of phosphorous, arsenic, antimony ¶0021 and 0034.
Regarding claim 9, Hsu discloses wherein the second dopant species of the source/drain feature includes a P-type dopant species, and wherein the first dopant species of the first doped layer includes boron ¶0021 and 0034.
Regarding claim 10, Hsu discloses providing a second fin extending from a substrate Fig 26, wherein the second fin includes a plurality of semiconductor channel layers having gaps therebetween Fig 26, forming an atomic layer deposition (ALD)-deposited doped layer on surfaces of each of the plurality of semiconductor channel layers ¶0031-0035; after forming the ALD-deposited doped layer, performing a drive-in anneal to cause dopants within the ALD-deposited doped layer to diffuse into the surfaces of each of the plurality of semiconductor channel layers to form a second doped layer near the surfaces of each of the plurality of semiconductor channel layers Fig 26 and 27; and after performing the drive-in anneal, removing a remaining portion of the ALD-deposited doped layer Fig 27.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2022/0093472) and Wang et al (US Publication No. 2022/0123111) and in further view of More et al (US Publication No. 2022/0052045).
Regarding claim 2, Hsu discloses all the limitations but silent on the dopant concentration. Whereas More discloses wherein a first dopant concentration of the first doped layer is less than a second dopant concentration of the source/drain feature ¶0033, 0041, 0064. Hsu and More are analogous art because they are directed to semiconductor devices having dipole layer and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the doping concentration and incorporate the teachings of More to improve device performance and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2022/0093472) and Wang et al (US Publication No. 2022/0123111) and in further view of Srinivasan et al (US Publication No. 2023/0178372).
Regarding claim 4, Hsu discloses all the limitations but silent on the implantation process. Whereas Srinivasan discloses wherein the forming the first doped layer includes performing an ion implantation process into the surface of the first fin, and wherein the ion implantation process penetrates at least a lower portion of the first gate stack to form the first doped layer beneath the first gate stack ¶0035-0037 Fig 4C-4F. Hsu and Srinivasan are analogous art because they are directed to semiconductor devices having doped layer and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the doping method of Hsu and incorporate the teachings of Srinivasan as an alternative method known in the art for doping semiconductor layers.
Regarding claim 7, Srinivasan discloses wherein the forming the first doped layer includes performing a plasma doping (PLAD) process prior to forming the first gate stack ¶0031.
Allowable Subject Matter
Claims 11-20 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “removing a remaining portion of the first doped layer to expose the surfaces of the plurality of first epitaxial layers; and after removing the remaining portion of the first doped layer, forming a gate dielectric layer over the exposed surfaces of the plurality of first epitaxial layers, the gate dielectric layer separate from and free of the second doped layer”, as recited in independent claim 11 and “ wherein the portion of the first gate structure includes a gate dielectric layer disposed over surfaces of the adjacent layers of the plurality of silicon epitaxial layers, and wherein the gate dielectric layer is separate from and free of the first doped layer” as recited in independent claim 18.
Claims 12-17, 19-20 are also allowed as being directly or indirectly dependent of the allowed independent base claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811