DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-16 and newly added claims 21-24, in the reply filed on November 13, 2025, is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 23, it appears the limitation “the gate” and subsequently “removing the gate” to form a metal gate, is requiring the dummy gate as “the gate”. However, this is inconsistent with claim 21 wherein the claim requires “forming a silicon nitride capping layer on the top of the gate”. Here, “the gate” refers to the replacement (metal) gate and not the dummy gate that claim 23 appears to be requiring. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-11, 13-16 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. Pub. 2022/0223422) [Hereafter “Chou”] in view of Woodruff et al. (U.S. Pub. 2018/0323055) [Hereafter “Woodruff”].
Regarding claim 1, Chou [Figs.9-13] discloses a method for semiconductor fabrication, comprising:
forming a metal gate [74] surrounded by a first silicon oxide layer [60] [Para.24], wherein a metallic surface of the metal gate is exposed [Fig.9];
depositing a silicon nitride layer [78] [Para.31] on the metallic surface; and
depositing a second silicon oxide layer [80] [Para.32] on the first silicon oxide layer and on the silicon nitride layer [Fig.10].
Chou fails to explicitly disclose selectively depositing a silicon nitride layer on the metallic surface and not on the first silicon oxide layer. However, Woodruff [Figs.1-5] discloses a method for semiconductor fabrication comprising selectively depositing a silicon nitride layer [508] on the metallic surface [504A] and not on the first silicon oxide layer [502A] [Fig.5].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Woodruff into the method of Chou to selectively deposit a silicon nitride layer on the metallic surface and not on the first silicon oxide layer. The ordinary artisan would have been motivated to modify Chou in the manner set forth above for at least the purpose of having an efficient and cost-effective method of forming the SiN layer only on the desired area of the substrate. [Woodruff; Paras.3-6]. Further, it would have been obvious to apply a known technique to a known process in order to yield predictable results would have been obvious. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 10, Chou [Figs.8-13] discloses a method for semiconductor fabrication, comprising:
providing a structure having a substrate [20], a source and a drain [52] over the substrate, one or more semiconductor channel layers [26,36] connecting the source and the drain, gate spacers [46] over the substrate, a first interlayer dielectric (ILD) layer [60] over the source and the drain and on sidewalls of the gate spacers such that a gate trench [62] is provided between portions of the gate spacers and exposes the one or more semiconductor channel layers [Fig.8];
depositing a metal gate electrode [74] into the gate trench and over the gate spacers and the first ILD layer [Para.30];
performing a chemical mechanical planarization process [Para.30] to the metal gate electrode until the first ILD layer is exposed and a top surface of the metal gate electrode is exposed [Fig.9];
depositing a silicon nitride layer [78] on the top surface of the metal gate electrode; and
depositing a second ILD layer [80] on the first ILD layer and on the silicon nitride layer [Fig.10].
Chou fails to explicitly disclose selectively depositing a silicon nitride layer on the top surface of the metal gate electrode and not on the first ILD layer. However, Woodruff [Figs.1-5] discloses a method for semiconductor fabrication comprising selectively depositing a silicon nitride layer [508] on the top surface of the metal gate electrode [504] and not on the first ILD layer [502] [Fig.5].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Woodruff into the method of Chou to selectively deposit a silicon nitride layer on the top surface of the metal gate electrode and not on the first ILD layer. The ordinary artisan would have been motivated to modify Chou in the manner set forth above for at least the purpose of having an efficient and cost-effective method of forming the SiN layer only on the desired area of the substrate. [Woodruff; Paras.3-6]. Further, it would have been obvious to apply a known technique to a known process in order to yield predictable results would have been obvious. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 21, Chou [Figs.7-13] discloses a method for semiconductor fabrication, comprising:
providing a gate [74] between a source and a drain [52];
providing a first silicon oxide layer [60] on sidewalls of the gate and on top of the source and drain;
forming a silicon nitride capping layer [78] on top of the gate;
depositing a second silicon oxide layer [80] on the silicon nitride capping layer and on the first silicon oxide layer; and
etching a first contact hole [86] extending through at least the second silicon oxide layer [80];
filling the first contact hole with conductive material [96] to provide a conductive path to the source or the drain, wherein the first contact does not directly contact the silicon nitride capping layer [separated by contact spacers 88] [Fig.13].
Chou fails to explicitly disclose forming a silicon nitride capping layer on the top of the gate and not on top of the first silicon oxide layer. However, Woodruff [Figs.1-5] discloses a method for semiconductor fabrication comprising forming a silicon nitride capping layer [508] on the top of the gate and not on top of the first silicon oxide layer [502] [Fig.5].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Woodruff into the method of Chou to selectively form a silicon nitride capping layer on the top of the gate and not on top of the first silicon oxide layer. The ordinary artisan would have been motivated to modify Chou in the manner set forth above for at least the purpose of having an efficient and cost-effective method of forming the SiN layer only on the desired area of the substrate. [Woodruff; Paras.3-6]. Further, it would have been obvious to apply a known technique to a known process in order to yield predictable results would have been obvious. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 2-6, Chou [Figs.8-13] and Woodruff [Figs.1-5] disclose a method for semiconductor fabrication
wherein the selectively depositing of the silicon nitride layer includes using an atomic layer deposition (ALD) process that includes a precursor adsorption phase, a first purging phase, a co-reactant adsorption phase, and a second purging phase [Woodruff; Figs.1-4 and related texts (Pars.25-62)];
wherein the precursor adsorption phase is timed such that silicon nitride precursor adsorbs onto the metallic surface and not on the first silicon oxide layer [Woodruff; Figs.1-4 and related texts (Pars.25-62)];
wherein the co-reactant adsorption phase is timed such that silicon nitride co-reactant reacts with the silicon nitride precursor and does not adsorb on the first silicon oxide layer [Woodruff; Figs.1-4 and related texts (Pars.25-62)];
wherein duration for the precursor adsorption phase is in a range from 0.1 second to 3 seconds, and duration for the co-reactant adsorption phase is in a range from 3 seconds to 10 seconds [Woodruff; Para.37];
wherein duration for the first purging phase is in a range from 0.5 second to 10 seconds, and duration for the second purging phase is in a range from 0.5 second to 20 seconds [Woodruff; Para.38].
Regarding claims 7-8, Chou [Figs.8-13] and Woodruff [Figs.1-5] disclose a method for semiconductor fabrication
wherein the metal gate [74] is sandwiched between two gate spacers [46] and the two gate spacers are surrounded by the first silicon oxide layer [60], wherein the silicon nitride layer [78] is formed to extend directly on top of the two gate spacers [Chou; Fig.10];
further comprising:
etching a contact hole [86] adjacent the metal gate, wherein the contact hole extends into the first and the second silicon oxide layers without exposing the silicon nitride layer [separated by contact spacers 88] [Fig.12]; and
forming a metallic contact [96] in the contact hole [Chou; Fig.13].
Regarding claims 11 and 13-16, Chou [Figs.8-13] and Woodruff [Figs.1-5] disclose a method for semiconductor fabrication [Discussed above in the treatment of claims 2-6 and 8]
further comprising:
etching a contact hole adjacent one of the gate spacers, wherein the contact hole extends through the first and the second ILD layers and reaches one of the source and the drain without exposing the silicon nitride layer; and
forming a metallic contact in the contact hole;
wherein the selectively depositing of the silicon nitride layer includes using an atomic layer deposition (ALD) process that includes a precursor adsorption phase, a first purging phase, a co-reactant adsorption phase, and a second purging phase, wherein the precursor adsorption phase is controlled such that silicon nitride precursor adsorbs onto the top surface of the metal gate electrode and not on the first ILD layer;
wherein the co-reactant adsorption phase is controlled such that silicon nitride co-reactant reacts with the silicon nitride precursor and does not adsorb on the first ILD layer;
wherein duration for the precursor adsorption phase is controlled to be in a range from 0.1 second to 5 seconds;
wherein duration for the co-reactant adsorption phase is controlled to be in a range from 3 seconds to 10 seconds.
Regarding claims 22-23, Chou [Figs.8-13] and Woodruff [Figs.1-5] disclose a method for semiconductor fabrication
further comprising:
forming an opening [104] extending through the second silicon oxide layer [80] and the silicon nitride capping layer [78] [Chou; Fig.15];
filling the opening with conductive materials to form a gate via [110], wherein the gate via provides a conductive path to the gate [74] [Chou; Fig.16];
further comprising:
depositing dielectric gate spacers [46] on sidewalls of the gate (a dummy gate) [34] and between the first silicon oxide layer [60] and the gate; and
subsequently removing the gate [62] to form a metal gate [74] [Chou; Figs.7-9].
Claim(s) 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. Pub. 2022/0223422) in view of Woodruff et al. (U.S. Pub. 2018/0323055), as applied above and further in view of Chi et al. (U.S. Pub. 2019/0164752) [Hereafter “Chi”].
Regarding claims 9 and 12, Chou fails to explicitly disclose wherein a sidewall of the contact hole has a continuously angular face. However, Chi [Figs.14A,15A] discloses a method
wherein a sidewall of the contact hole [132] has a continuously angular face;
wherein two opposing sidewalls of the contact hole [132] have continuously angular faces extending through the first and the second ILD layers [100,130].
It would have been obvious to provide wherein a sidewall of the contact hole has a continuously angular face, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. Pub. 2022/0223422) in view of Woodruff et al. (U.S. Pub. 2018/0323055), as applied above and further in view of Su et al. (U.S. Pub. 2021/0287904) [Hereafter “Su”].
Regarding claim 24, Chou and Woodruff fail to explicitly disclose wherein the silicon nitride capping layer has rounded corners directly above the dielectric gate spacers. However, it appears obvious that the rounded corner is an apparent result of the selective deposition process. Su [Figs.16-17] discloses and makes obvious a method wherein a capping layer has rounded corners directly above the dielectric gate spacers [338]. It would have been obvious to include wherein the capping layer has rounded corners directly above the dielectric gate spacers, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
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/BAC H AU/Primary Examiner, Art Unit 2898