DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 12/24/2025. Claims 12 and 18 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 12-14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20200035690 A1, hereafter Chen) in view of Chen et al (US 10276554 B1, hereafter Chen-554), and further in view of Chen et al (US 20210098594 A1, hereafter Chen-594).
Regarding claim 12, Chen teaches: An integrated circuit layout (Chen 200, fig 4, 5A, 7), comprising:
a memory circuit (Chen 10, 202) with a first boundary (Chen ¶0078, 1st cell height, fig 5A), the memory circuit including:
a plurality of first active regions (Chen 302A-D) over a substrate (Chen ¶0025, “… semiconductor material formed on an insulator layer…. The insulator layer is provided on a substrate…”), and
a plurality of first gate structures (Chen 304A-D) across the first active regions (Chen fig 5A),
a logic circuit (Chen 204, 400) with a second boundary (Chen 1st cell height, fig 7), the logic circuit including:
a plurality of second active regions (Chen 502A1, 502A2, 502B1, 502B2) over the substrate (Chen ¶0025), and
a second gate structure (Chen 504); and
a transition region (Chen 206, under a broadest reasonable interpretation, strap cells 206 are at least in a region wherein an array transitions from one cell type to another).
Chen does not teach: the first gate structures having a gate pitch;
a plurality of second gate structures across the second active regions, the second gate structures having the gate pitch; and
a transition region spanning from an edge of the first boundary to an edge of the second boundary with a width of an integer multiple of the gate pitch, the transition region including:
at least one dielectric feature separating the first active regions from contacting the second active regions and extending into the substrate.
Chen-554, in the same field of endeavor of semiconductor device manufacturing, teaches:
a plurality of first active regions (Chen-554 left 106, fig 6) over a substrate (Chen-554 102)(Chen-554 Col 2, Line 7, “various active regions 106 on the substrate 102”, fig 5B), and
a plurality of first gate structures (Chen-554 112 within 302, fig 6) across the first active regions (Chen-554 left 106, fig 6), the first gate structures having a gate pitch (Chen-554 P)(Chen fig 6, Col 9, Lines 57-61);
a plurality of second active regions (Chen-554 right 106, fig 6) over the substrate (Chen-554 fig 5B), and
a plurality of second gate structures (Chen-554 112 within 304, fig 6) across the second active regions (Chen-554 right 106, fig 6), the second gate structures having the gate pitch (Chen-554 fig 6, Col 9, Lines 57-61); and
a transition region (Chen-554 202) spanning from an edge of a first boundary (Chen-554, boundary of 302 formed by 114, fig 6) to an edge of a second boundary (Chen-554, boundary of 304 formed by 114, fig 6) with a width of an integer multiple of the gate pitch (Chen-554 fig 6, Col 9, Lines 57-61, Df being 2P), the transition region including:
at least one dielectric feature (Chen-554 center 114, fig 6) separating the first active regions from contacting the second active regions (Chen-554 fig 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to replace the transition region of Chen with that of Chen-554, such that “a transition region spanning from an edge of the first boundary to an edge of the second boundary with a width of an integer multiple of the gate pitch, the transition region including: at least one dielectric feature separating the first active regions from contacting the second active regions.”, in order to provide improvement in manufacturing margin (Chen ¶0023), and/or in order to provide isolation between cell types at a periphery of the SRAM array (Chen-554 Col 4, Lines 40-50).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the second gate structure of Chen in order to provide a different logic function (Chen ¶0014, Chen-554 fig 3A), since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first gate structures of Chen to be space by a gate pitch, as taught by Chen-554, in order to reduce design uncertainty and/or improve processing uniformity (Chen Col 6, Lines 5-16).
Chen in view of Chen-554 does not explicitly teach: the at least one dielectric feature extending into the substrate.
Chen-594, in the same field of endeavor of semiconductor device manufacturing, teaches: a dielectric feature (Chen-594 230, ¶0037) extending into a substrate (Chen-594 202)(Chen-594 fig 3B, ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the at least one dielectric feature of Chen in view of Chen-554, such that it extends into the substrate, in order reduce parasitic capacitance and improve device performance (Chen-594 ¶0023, 0066).
Regarding claim 13, Chen in view of Chen-554 and Chen-594 teaches: The integrated circuit layout of claim 12.
Chen in view of Chen-554 and Chen-594 does not explicitly teach: the transition region has the width of one gate pitch, and the at least one dielectric feature has a first sidewall contacting the first active regions and a second sidewall contacting the second active regions.
Chen-554, in at least one embodiment, further teaches: wherein a transition region (Chen-554 124, similar to Chen-554 202) has a width of one gate pitch (Chen-554 P)(Chen fig 3A), and an at least one dielectric feature (Chen-554 left and right 114, fig 3A) has a first sidewall contacting a plurality of first active regions (Chen-554 left 106, fig 6) and a second sidewall contacting a plurality of second active regions (Chen-554 right 106, fig 6)(Chen-554 fig 3A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the transition region of Chen in view of Chen-554 and Chen-594 such that “the transition region has the width of one gate pitch, and the at least one dielectric feature has a first sidewall contacting the first active regions and a second sidewall contacting the second active regions”, in order to reduce the area required for cell isolation, thereby improving packing density (Chen-554 Col 6, Lines 4-7).
Regarding claim 14, Chen in view of Chen-554 and Chen-594 teaches: The integrated circuit layout of claim 12, wherein the transition region (Chen 206 as modified by Chen-554 202) has the width of two gate pitches (Chen-554 Col 9, Lines 57-61, Df being 2P), and the transition region includes first and second dielectric features (Chen-554 left and right 114, fig 6) that are spaced apart for one gate pitch (Chen-554 fig 6).
Regarding claim 18, Chen teaches: A static random-access memory (SRAM) circuit (Chen 10, fig 1, 4, 5A), comprising:
an SRAM cell (Chen 10) including a first pass-gate transistor (Chen PG-1) and a first pull-down transistor (Chen PD-1) formed on a first active region (Chen 302B) and a second pass-gate transistor (Chen PG-2) and a second pull-down transistor (Chen PD-2) formed on a second active region (Chen 302D), wherein the first and second active regions extend lengthwise in a first direction (Chen Y dir, fig 5A) over a substrate (Chen ¶0025, “… semiconductor material formed on an insulator layer…. The insulator layer is provided on a substrate…”);
and a second direction (Chen X dir, fig 5A) perpendicular to the first direction (Chen fig 5A).
Chen does not teach: a dielectric feature extending lengthwise in a second direction perpendicular to the first direction, wherein the dielectric feature has a sidewall in contact with the first active region and the second active region, wherein the dielectric feature extends into the substrate.
Chen further teaches: an SRAM array (Chen 200), including: an SRAM cell (Chen 10), and a strap cell (Chen 206) adjacent to the SRAM cell (Chen fig 4).
Chen-554, in the same field of endeavor of semiconductor device manufacturing, teaches: a dielectric feature (Chen-554 114) extending lengthwise in a second direction (Chen-554 X dir, fig 2A, similar to Chen X dir) perpendicular to a first direction (Chen-554 Y dir, fig 2A, similar to Chen Y dir), wherein the dielectric feature has a sidewall in contact with a first active region (Chen-554 top 106, fig 2A) and the second active region (Chen-554 bottom 106, fig 2A);
wherein the first and second active regions extend lengthwise in the first direction (Chen-554 Y dir, fig 2A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen to include the dielectric feature of Chen-554, such that the dielectric feature has a sidewall in contact with the first and second active regions, in order to provide improvement in manufacturing margin (Chen ¶0023), and/or in order to provide isolation between cell types at a periphery of the SRAM array (Chen-554 Col 4, Lines 40-50).
Chen in view of Chen-554 does not explicitly teach: wherein the dielectric feature extends into the substrate.
Chen-594, in the same field of endeavor of semiconductor device manufacturing, teaches: a dielectric feature (Chen-594 230, ¶0037) extending into a substrate (Chen-594 202)(Chen-594 fig 3B, ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the dielectric feature of Chen in view of Chen-554, such that it extends into the substrate, in order provide sufficient isolation, thereby reducing parasitic capacitance while maintaining a small cell size (Chen-594 ¶0023, 0060, 0066).
Regarding claim 19, Chen in view of Chen-554 and Chen-594 teaches: The SRAM circuit of claim 18, wherein the first pass-gate transistor (Chen PG-1) has a first gate structure (Chen 304C) extending lengthwise in the second direction (Chen X dir, similar to Chen-554 X dir)(Chen fig 5A), the first pull-down transistor (Chen PD-1) includes a second gate structure (Chen 304A) extending lengthwise in the second direction (Chen fig 5A).
Chen in view of Chen-554 and Chen-594 does not teach: the first gate structure, the second gate structure, and the dielectric feature are evenly spaced along the first direction.
Chen-554 further teaches: evenly spacing gates (Chen-554) and dielectric features (Chen-554 114) by multiples of a pitch (Chen-554 P)(Chen-554 Col 5, Lines 19-25, Col 6, Lines 5-16, fig 2A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen in view of Chen-554 and Chen-594, such that “the first gate structure, the second gate structure, and the dielectric feature are evenly spaced along the first direction”, in order to reduce design uncertainty and/or improve processing uniformity (Chen-554 Col 6, Lines 5-16).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20200035690 A1, hereafter Chen) in view of Chen et al (US 10276554 B1, hereafter Chen-554) and Chen et al (US 20210098594 A1, hereafter Chen-594), as applied to claim 18, and further in view of Liaw et al (US 20210098466 A1, hereafter Liaw).
Regarding claim 20, Chen in view of Chen-554 and Chen-594 teaches: The SRAM circuit of claim 18.
Chen in view of Chen-554 and Chen-594 does not explicitly teach: wherein a length of the dielectric feature measured in the second direction is larger than a height of the SRAM cell measured in the second direction.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a dielectric feature continuously spanning multiple SRAM cells (Liaw ¶0107).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the dielectric feature of Chen in view of Chen-554 and Chen-594 to have a length longer than a height of a single SRAM cell, such that “a length of the dielectric feature measured in the second direction is larger than a height of the SRAM cell measured in the second direction”, in order to reduce the number of process steps required for forming the dielectric feature (Liaw ¶0107), and/or in order to eliminate dielectric feature ends between adjacent cells shrinking, thereby ensuring isolation between cell ends (Liaw ¶0107).
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
the first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region, and
the second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region. (Applicant fig 7, ¶0065).
Chen in view of Chen-554 in combination disclose some of the features of the claimed invention, as disclosed in the office action dated 09/24/2025, but there is no motivation/teaching and do not render obvious to combine and/or modify Chen, Chen-554, Liaw, Baek, Azmat, or any other prior arts of record so that all of limitations of claim 1 as a whole can be met.
Regarding claims 2-11, the dependent claims are allowed for their dependency to claim 1.
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the transition region has the width of three gate pitches.
Chen et al (US 20200035690 A1, here after Chen) in view of Chen et al (US 10276554 B1, hereafter Chen-554) and Chen et al (US 20210098594 A1, hereafter Chen-594) teaches: The integrated circuit layout of claim 12, wherein the at least one dielectric feature (Chen-554 center 114, fig 6) is located on a center line of the transition region (Chen 206 as modified by Chen-554 202)(Chen-554 fig 6).
Regarding claim 16, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the transition region has the width of three gate pitches, and
the transition region includes a plurality of third gate structures disposed between the first and second dielectric features.
Chen et al (US 20200035690 A1, here after Chen) in view of Chen et al (US 10276554 B1, hereafter Chen-554) and Chen et al (US 20210098594 A1, hereafter Chen-594) further teaches: The integrated circuit layout of claim 12, wherein the transition region (Chen 206 as modified by Chen-554 202) includes first and second dielectric features (Chen-554, left and right 114 of 202, fig 6) that are spaced apart for two gate pitches (Chen fig 6, Col 9, Lines 57-61, Df being 2P).
Regarding claim 17, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the transition region has the width of three gate pitches.
Chen et al (US 20200035690 A1, here after Chen) in view of Chen et al (US 10276554 B1, hereafter Chen-554) and Chen et al (US 20210098594 A1, hereafter Chen-594) teaches: The integrated circuit layout of claim 12, wherein the transition region (Chen 206 as modified by Chen-554 202) includes first, second, and third dielectric features (Chen-554 fig 6, three 114) that are spaced apart from adjacent ones for the gate pitch (Chen-554 fig 6, Col 9, Lines 57-61).
Regarding claims 15-17, Chen in view of Chen-554 in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Chen, Chen-554, Liaw, Baek, Azmat, or any other prior arts of record so that all of limitations of claims 15-17 as a whole can be met.
Response to Arguments
Applicant’s arguments with respect to claim(s) 12 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818