DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16,21-24 in the reply filed on 10/02/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16,21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guan(USPGPUB DOCUMENT: 2020/0043969, hereinafter Guan) in view of Kim (USPGPUB DOCUMENT: 2017/0117358, hereinafter KIm).
Re claim 1 Guan discloses a method for forming a through substrate(505) via(506), the method comprising: forming a trench that extends through an insulation layer(50) and into a substrate(505), wherein the substrate(505) has a first side and a second side, the insulation layer(50) is disposed over the first side of the substrate(505), and the second side is opposite the first side; filling the trench with a dielectric material(507); performing a thinning process on the second side of the substrate(505), wherein the removal process exposes(Fig 10) the dielectric material(507) (Fig 10); and after performing the thinning process and removing the dielectric material(507) from the trench, forming an electrically conductive structure(511) in the trench, wherein the electrically conductive structure(511) extends through the substrate(505) from the first side to the second side.
Guan does not disclose wherein the thinning process exposes(Fig 10) the dielectric material(507) (Fig 10)
Kim disclose wherein the thinning process exposes the dielectric material[0058]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Guan in order to increasing data rates of devices [0004, Kim].
Re claim 2 Guan and Kim disclose the method of claim 1, wherein the forming the electrically conductive structure(511) in the trench includes: forming a barrier layer in the trench that forms a top and sidewalls of the electrically conductive structure(511); and forming an electrically conductive layer over the barrier layer in the trench, wherein a portion of the barrier layer that forms the top of the electrically conductive structure(511) is disposed in the insulation layer(50).
Re claim 3 Guan and Kim disclose the method of claim 2, wherein the forming the barrier layer includes: depositing a dielectric liner over the second side of the substrate(505), wherein the dielectric liner partially fills the trench; and depositing a metal-comprising liner over the dielectric liner.
Re claim 4 Guan and Kim disclose the method of claim 1, wherein: the dielectric material(507) filling the trench has a first thickness; and the thinning process removes a portion of the dielectric material(507), thereby providing the dielectric material(507) filling the trench with a second thickness that is less than the first thickness.
Re claim 5 Guan and Kim disclose the method of claim 1, wherein the removing the dielectric material(507) includes performing an etching process that selectively removes the dielectric material(507) relative to the insulation layer(50) and the substrate(505).
Re claim 6 Guan and Kim disclose the method of claim 1, wherein: the trench has a first aspect ratio (see Fig 11-15)); and after the thinning process and the removing of the dielectric material(507), the trench has a second aspect ratio that is less than the first aspect ratio (see Fig 11-15)).
Re claim 7 Guan and Kim disclose the method of claim 1, wherein: the insulation layer(50) and the substrate(505) form a semiconductor structure; and the method further includes flipping the semiconductor structure, such that the forming the electrically conductive structure(511) in the trench includes depositing electrically conductive material over the second side of the substrate(505).
Re claim 8 Guan and Kim disclose the method of claim 1, wherein after the thinning process and the removing of the dielectric material(507), the trench has a top critical dimension in the insulation layer(50), a middle critical dimension proximate an interface of the insulation layer(50) and the first side of the substrate(505), and a bottom critical dimension in the substrate(505); and a ratio of the top critical dimension to the middle critical dimension to the bottom critical dimension is about 1:1:1 to about 4:2:1.
Re claim 9 Guan and Kim disclose the method of claim 1, wherein the insulation layer(50) and the substrate(505) form a first semiconductor structure, the method further comprising bonding the first semiconductorstructure to a second semiconductor structure, wherein the electrically conductive structure(511) connects the first semiconductor structure and the second semiconductor structure.
Re claim 10 Guan discloses a method comprising: receiving a workpiece having a device substrate(505) wherein the device substrate(505) has a first thickness between a first side and a second side thereof and the MLI feature is disposed over the first side; forming a through via(506) opening that extends through an insulation layer(50) and a depth into the device substrate(505), wherein the depth is less than the first thickness and the through via(506) opening has a first aspect ratio (see Fig 11-15)) ; filling the through via(506) opening with a sacrificial material; removing a portion of the device substrate(505) to reduce the first thickness to a second thickness, wherein the removing of the portion of the device substrate(505) further includes removing a portion of the sacrificial material; selectively removing the sacrificial material relative to the insulation layer(50) and the device substrate(505), wherein the through via(506) opening has a second aspect ratio after selectively removing the sacrificial material and the second aspect ratio is less than the first aspect ratio (see Fig 11-15)); and forming a through via(506) in the through via(506) opening having the second aspect ratio, wherein the through via(506) includes a barrier liner(508) that wraps an electrically conductive plug(511) and the barrier liner(508) and the insulation layer(50) form a top surface of the workpiece.
Guan does not disclose a multilayer interconnect (MLI) feature,
Kim disclose a multilayer interconnect (MLI) feature,[0059]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Guan in order to increasing data rates of devices [0004, Kim].
Re claim 11 Guan and Kim disclose the method of claim 10, wherein the forming the through via(506) includes: forming a barrier layer over the second side of the device substrate(505), wherein the barrier layer partially fills the through via(506) opening; forming a bulk layer over the barrier layer and the second side of the device substrate(505), wherein the bulk layer fills a remainder of the through via(506) opening; and performing a planarization process to remove a portion of the bulk layer and a portion of the barrier layer from over the second side of the device substrate(505), wherein a remaining portion of the bulk layer forms the electrically conductive plug(511) and a remaining portion of the barrier layer forms the barrier liner(508).
Re claim 12 Guan and Kim disclose the method of claim 11, wherein the forming the barrier layer includes: forming a dielectric layer over the second side of the device substrate(505); and forming a barrier/seed layer over the dielectric layer, wherein a remaining portion of the dielectric layer forms a dielectric liner, a remaining portion of the barrier/seed layer forms a barrier/seed liner, and the barrier liner(508) includes the dielectric liner and the barrier/seed liner.
Re claim 13 Guan and Kim disclose the method of claim 10, wherein a top of the workpiece is formed by the insulation layer(50) of the MLI feature, a bottom of the workpiece is formed by the second side of the device substrate(505), and the forming the through via(506) in the through via(506) opening includes flipping over the workpiece before forming the through via(506) in the through via(506) opening.
Re claim 14 Guan and Kim disclose the method of claim 10, wherein the first side is a frontside of the device substrate(505) and the second side is a backside of the device substrate(505).
Re claim 15 Guan and Kim disclose the method of claim 10, wherein the device substrate(505), the MLI feature, and the through via(506) form a portion of a first chip, the method further comprising bonding the first chip to a second chip, wherein the through via(506) provides an electrical connection between the first chip and the second chip.
Re claim 16 Guan and Kim disclose the method of claim 10, further comprising forming a patterned metal layer over the MLI feature and the through via(506), wherein the patterned metal layer includes a metal line disposed over the through via(506) and the barrier liner(508) of the through via(506) is between the metal line of the pattered metal layer and the electrically conductive plug(511) of the through via(506).
Re claim 21 Guan discloses a method comprising: forming a through via(506) trench in a dielectric structure and a semiconductor structure; after filling the through via(506) trench with a dielectric material(507),; and after reducing the thickness of the semiconductor structure to expose the dielectric material(507) inthe semiconductor structure, replacing the dielectric material(507) with a through via(506) structure, wherein the through via(506) structure is disposed in the dielectric structure and the semiconductor structure and the through via(506) structure has a first aspect ratio (see Fig 11-15)) that is less than a second aspect ratio of the through via(506) trench in the dielectric structure and the semiconductor structure.
Guan does not disclose reducing a thickness of the semiconductor structure to expose the dielectric material(507) in the semiconductor structure
Kim disclose reducing a thickness of the semiconductor structure [0058]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Guan in order to increasing data rates of devices [0004, Kim]. In doing so, reducing a thickness of the semiconductor structure [0058 of Kim] to expose the dielectric material(507 of Guan) in the semiconductor structure
Re claim 22 Guan and Kim disclose the method of claim 21, wherein the through via(506) trench is a first through via(506) trench and the replacing the dielectric material(507) with the through via(506) structure includes: performing an etching process and a cleaning process to remove the dielectric material(507) to form a second through via(506) trench in the dielectric structure and the semiconductor structure, wherein the second through via(506) trench has the second aspect ratio; and performing a deposition process to form a through via(506) layer of the through via(506) structure over a backside of the semiconductor structure and in the second through via(506) trench.
Re claim 23 Guan and Kim disclose the method of claim 22, wherein the performing the deposition process includes performing an electrochemical plating process to form the through via(506) layer.
Re claim 24 Guan and Kim disclose the method of claim 21, wherein the reducing the thickness of the semiconductor structure to expose the dielectric material(507) in the semiconductor structure includes performing a planarization process on a backside of the semiconductor structure.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812