Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 8, 9, 11, 14, 15, 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20130031521A1 (Teoh) in view of US20110145775A1 (Sano).
In regards to claim 1 (Teoh) shows a computer-implemented method comprising:
accessing physical design data for an integrated circuit, the physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit; Teoh [0038] and [0061] teach receiving data corresponding to a block of intellectual property including a layout design comprising a plurality of geometric elements bounded by boundaries, mapping to accessing physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit as recited in the claim.
performing shapes-based checking of the physical design data to identify a circuit region containing problematic content, wherein the problematic content corresponds to a defined pattern; Teoh [0040] and [0062] teach scanning at least a boundary of the layout design against one or more problematic layout patterns and identifying, at the boundary, one or more partial matches using multi-dimensional pattern matching techniques, mapping to performing shapes-based checking of the physical design data to identify a circuit region containing problematic content corresponding to a defined pattern as recited in the claim.
Teoh differs from the claimed invention in that it does not explicitly disclose identifying a first circuit of the identified circuit region containing the problematic content; providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; and performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked.
Sano teaches identifying a first circuit of the identified circuit region containing the problematic content; Sano [0042] and [0043] teach identifying a target cell that easily causes a defect at a risk portion of a boundary due to an adjacently placed cell, constituting identifying a first circuit of the identified circuit region containing the problematic content as recited in the claim.
Sano teaches providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; Sano [0056], [0057], and [0060] teach an adjacent placement risk attribute value assigned to a specified edge of a cell, e.g., "CELL RIGHT EDGE DAMAGE VA," constituting a keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
Sano teaches based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; Sano [0051] and [0067] teach determining the risk attribute from LRC-reported defect portions and noting the attribute in the external-form/terminal-position information library of the cell library, constituting updating a circuit identification file with the keyword for the first circuit based on identifying the problematic content as recited in the claim.
Sano teaches performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked; Sano [0075] and [0082] teach the placement-position correcting unit reading the edge attribute value, detecting the risk boundary at that edge, and inserting a predetermined grid spacing between the target cell and the adjacent cell measured from that edge, constituting performing construction placement checking that uses the location-specific identifier of the keyword to determine the at least one circuit boundary from which placement compliance with the predetermined separation spacing is checked to a second circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 5 (Teoh) does not show: accessing a circuit identification file associated with the predefined circuit shapes forming the at least one subcircuit;
Sano teaches accessing a circuit identification file associated with the predefined circuit shapes forming the at least one subcircuit; Sano [0067] and [0073] teach inputting a cell library including an external-form/terminal-position information library and the roughly placing unit obtaining form and terminal position information of each cell from that library, constituting accessing a circuit identification file associated with the predefined circuit shapes forming the at least one subcircuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 6 (Teoh) does not show: wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern;
Sano teaches wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern; Sano [0049], [0057], and [0060] teach the adjacent placement risk attribute provided respectively to the top, bottom, left, and right edges of a cell, e.g., "CELL TOP EDGE DAMAGE S" and "CELL LEFT EDGE DAMAGE V," constituting the location-specific identifier identifying at least one of a north, south, east, or west boundary of the first circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 8 (Teoh) does not show: wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit, and further comprises providing a separation spacing greater than or equal to the predetermined separation spacing based on determining that the second circuit comprises the sensitive circuit;
Sano teaches wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit; Sano [0044] and [0055] teach an adjacent second cell assigned a victim or aggressor risk attribute, constituting determining that the second circuit comprises a sensitive circuit as recited in the claim.
Sano teaches further comprises providing a separation spacing greater than or equal to the predetermined separation spacing based on determining that the second circuit comprises the sensitive circuit; Sano [0085] teaches setting the number of grids of separation so the movement distance exceeds the distance reached by the optical proximity effect, constituting providing a separation spacing greater than or equal to the predetermined separation spacing based on that determination as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 9 (Teoh) shows the method of claim 1:
the defined pattern comprises at least one of a predefined configuration of shapes or a density pattern of shapes greater than or equal to a predefined threshold density value; Teoh [0040] and [0041] teach that actual problematic layout patterns are predefined configurations of geometric elements that when fabricated result in at least one manufactured hotspot, mapping to the defined pattern comprising at least one of a predefined configuration of shapes or a density pattern of shapes greater than or equal to a predefined threshold density value as recited in the claim.
In regards to claim 11 (Teoh) shows a system, comprising:
a processor; and a memory, wherein the memory includes a computer program product configured to perform operations for implementing defined circuit structure pattern identification and placement avoidance in an integrated circuit, the operations comprising: Teoh [0075] teaches a computer system including at least one processor and at least one memory storing applications executed by the processor, mapping to a system comprising a processor and a memory as recited in the claim.
accessing physical design data for an integrated circuit, the physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit; Teoh [0038] and [0061] teach receiving data corresponding to a block of intellectual property including a layout design comprising a plurality of geometric elements bounded by boundaries, mapping to accessing physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit as recited in the claim.
performing shapes-based checking of the physical design data to identify a circuit region containing problematic content, wherein the problematic content corresponds to a defined pattern; Teoh [0040] and [0062] teach scanning at least a boundary of the layout design against one or more problematic layout patterns and identifying, at the boundary, one or more partial matches using multi-dimensional pattern matching techniques, mapping to performing shapes-based checking of the physical design data to identify a circuit region containing problematic content corresponding to a defined pattern as recited in the claim.
Teoh differs from the claimed invention in that it does not explicitly disclose identifying a first circuit of the identified circuit region containing the problematic content; providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; and performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked.
Sano teaches identifying a first circuit of the identified circuit region containing the problematic content; Sano [0042] and [0043] teach identifying a target cell that easily causes a defect at a risk portion of a boundary due to an adjacently placed cell, constituting identifying a first circuit of the identified circuit region containing the problematic content as recited in the claim.
Sano teaches providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; Sano [0056], [0057], and [0060] teach an adjacent placement risk attribute value assigned to a specified edge of a cell, e.g., "CELL RIGHT EDGE DAMAGE VA," constituting a keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
Sano teaches based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; Sano [0051] and [0067] teach determining the risk attribute from LRC-reported defect portions and noting the attribute in the external-form/terminal-position information library of the cell library, constituting updating a circuit identification file with the keyword for the first circuit based on identifying the problematic content as recited in the claim.
Sano teaches performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked; Sano [0075] and [0082] teach the placement-position correcting unit reading the edge attribute value, detecting the risk boundary at that edge, and inserting a predetermined grid spacing between the target cell and the adjacent cell measured from that edge, constituting performing construction placement checking that uses the location-specific identifier of the keyword to determine the at least one circuit boundary from which placement compliance with the predetermined separation spacing is checked to a second circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 14 (Teoh) does not show: wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern;
Sano teaches wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern; Sano [0049], [0057], and [0060] teach the adjacent placement risk attribute provided respectively to the top, bottom, left, and right edges of a cell, e.g., "CELL TOP EDGE DAMAGE S" and "CELL LEFT EDGE DAMAGE V," constituting the location-specific identifier identifying at least one of a north, south, east, or west boundary of the first circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 15 (Teoh) does not show: wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit, and further comprises providing the separation space greater than or equal to a predefined minimum separation space based on determining that the second circuit comprises the sensitive circuit;
Sano teaches wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit; Sano [0044] and [0055] teach an adjacent second cell assigned a victim or aggressor risk attribute, constituting determining that the second circuit comprises a sensitive circuit as recited in the claim.
Sano teaches further comprises providing the separation space greater than or equal to a predefined minimum separation space based on determining that the second circuit comprises the sensitive circuit; Sano [0085] teaches setting the number of grids of separation so the movement distance exceeds the distance reached by the optical proximity effect, constituting providing the separation space greater than or equal to a predefined minimum separation space based on that determination as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 16 (Teoh) shows:
a computer program product for implementing defined circuit structure pattern identification and placement avoidance in an integrated circuit (IC) design, the computer program product comprising a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform operations comprising: Teoh [0075] teaches applications comprising computer program code stored on storage and executed by one or more processors, mapping to a computer program product embodied on a computer-readable storage medium as recited in the claim.
accessing physical design data for an integrated circuit, the physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit; Teoh [0038] and [0061] teach receiving data corresponding to a block of intellectual property including a layout design comprising a plurality of geometric elements bounded by boundaries, mapping to accessing physical design data comprising predefined circuit shapes forming at least one subcircuit of the integrated circuit as recited in the claim.
performing shapes-based checking of the physical design data to identify a circuit region containing problematic content, wherein the problematic content corresponds to a defined pattern; Teoh [0040] and [0062] teach scanning at least a boundary of the layout design against one or more problematic layout patterns and identifying, at the boundary, one or more partial matches using multi-dimensional pattern matching techniques, mapping to performing shapes-based checking of the physical design data to identify a circuit region containing problematic content corresponding to a defined pattern as recited in the claim.
Teoh differs from the claimed invention in that it does not explicitly disclose identifying a first circuit of the identified circuit region containing the problematic content; providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; and performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked.
Sano teaches identifying a first circuit of the identified circuit region containing the problematic content; Sano [0042] and [0043] teach identifying a target cell that easily causes a defect at a risk portion of a boundary due to an adjacently placed cell, constituting identifying a first circuit of the identified circuit region containing the problematic content as recited in the claim.
Sano teaches providing a keyword for the first circuit, the keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern; Sano [0056], [0057], and [0060] teach an adjacent placement risk attribute value assigned to a specified edge of a cell, e.g., "CELL RIGHT EDGE DAMAGE VA," constituting a keyword comprising a location-specific identifier of at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
Sano teaches based on identifying the problematic content in the first circuit, updating a circuit identification file with the keyword for the first circuit of the identified circuit region containing the problematic content; Sano [0051] and [0067] teach determining the risk attribute from LRC-reported defect portions and noting the attribute in the external-form/terminal-position information library of the cell library, constituting updating a circuit identification file with the keyword for the first circuit based on identifying the problematic content as recited in the claim.
Sano teaches performing construction placement checking, based on the keyword of the first circuit, to determine placement compliance with a predetermined separation spacing from the at least one circuit boundary to a second circuit of the integrated circuit, wherein the construction placement checking uses the location-specific identifier of the keyword to determine the at least one circuit boundary of the first circuit from which placement compliance with the predetermined separation spacing is checked; Sano [0075] and [0082] teach the placement-position correcting unit reading the edge attribute value, detecting the risk boundary at that edge, and inserting a predetermined grid spacing between the target cell and the adjacent cell measured from that edge, constituting performing construction placement checking that uses the location-specific identifier of the keyword to determine the at least one circuit boundary from which placement compliance with the predetermined separation spacing is checked to a second circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 19 (Teoh) does not show: wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern;
Sano teaches wherein the location-specific identifier identifies at least one of a north boundary, a south boundary, an east boundary or a west boundary of the first circuit containing the defined pattern; Sano [0049], [0057], and [0060] teach the adjacent placement risk attribute provided respectively to the top, bottom, left, and right edges of a cell, e.g., "CELL TOP EDGE DAMAGE S" and "CELL LEFT EDGE DAMAGE V," constituting the location-specific identifier identifying at least one of a north, south, east, or west boundary of the first circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
In regards to claim 20 (Teoh) does not show: wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit, and further comprises providing the separation space greater than or equal to a predefined minimum separation space based on determining that the second circuit comprises the sensitive circuit;
Sano teaches wherein performing construction placement checking, based on the keyword of the first circuit further comprises determining that the second circuit comprises a sensitive circuit; Sano [0044] and [0055] teach an adjacent second cell assigned a victim or aggressor risk attribute, constituting determining that the second circuit comprises a sensitive circuit as recited in the claim.
Sano teaches further comprises providing the separation space greater than or equal to a predefined minimum separation space based on determining that the second circuit comprises the sensitive circuit; Sano [0085] teaches setting the number of grids of separation so the movement distance exceeds the distance reached by the optical proximity effect, constituting providing the separation space greater than or equal to a predefined minimum separation space based on that determination as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout.
Claims 2, 3, 4, 7, 10, 12, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US20130031521A1 (Teoh) in view of US20110145775A1 (Sano) as applied to claims 1, 11, and 16 above, and further in view of US20070226662A1 (Pokorny).
In regards to claim 2 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers of a predetermined width and spacing for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify a presence, configuration, or characteristic of a circuit region of tiles matching the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 3 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify within the circuit region a density pattern matching the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify within the circuit region a density pattern matching the defined pattern; Pokorny [0027] and [0038] teach that shapes larger than a given threshold are identified as potential problems and only those with a measured length greater than or equal to a threshold level are kept for further analysis, constituting sequentially processing tiles to identify within the circuit region a density pattern matching the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 4 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify the at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 7 (Teoh modified by Sano) does not show: wherein the predefined circuit shapes comprise multiple layers of the physical design data and wherein performing shapes-based checking further comprises performing shapes-based checking of the multiple layers of the physical design data;
Pokorny teaches wherein the predefined circuit shapes comprise multiple layers of the physical design data and wherein performing shapes-based checking further comprises performing shapes-based checking of the multiple layers of the physical design data; Pokorny [0036] teaches generating sampling slivers for each mask layer in question and overlaying them to sample each mask layer of the layout, constituting performing shapes-based checking of the multiple layers of the physical design data as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 10 (Teoh modified by Sano) does not show: wherein performing construction placement checking, based on the keyword of the first circuit further comprises performing construction circuit placement checking of multiple layers of the physical design data of a layout of the integrated circuit;
Pokorny teaches wherein performing construction placement checking, based on the keyword of the first circuit further comprises performing construction circuit placement checking of multiple layers of the physical design data of a layout of the integrated circuit; Pokorny [0036] teaches generating sampling slivers for each mask layer in question and overlaying them to sample each mask layer of the layout, constituting performing construction circuit placement checking of multiple layers of the physical design data of a layout of the integrated circuit as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 12 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers of a predetermined width and spacing for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify a presence, configuration, or characteristic of a circuit region of tiles matching the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 13 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify the at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 17 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify at least one of a presence, configuration, and characteristic of the circuit region of tiles matching the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers of a predetermined width and spacing for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify a presence, configuration, or characteristic of a circuit region of tiles matching the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
In regards to claim 18 (Teoh modified by Sano) does not show: wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern;
Pokorny teaches wherein performing shapes-based checking of the physical design data further comprises sequentially processing tiles of a set area size of a given layer of the physical design data to identify the at least one circuit boundary of the first circuit containing the defined pattern; Pokorny [0026] and [0036] teach generating sampling slivers for each mask layer and overlaying them to sequentially sample the layout and identify regions where structures satisfy a predetermined value, constituting sequentially processing tiles of a set area size of a given layer to identify the at least one circuit boundary of the first circuit containing the defined pattern as recited in the claim.
It would have been obvious to one of ordinary skill in the art to combine Teoh and Sano with a reasonable expectation of success as both address avoidance of lithographic defects at cell boundaries in integrated circuit layout. It would have been obvious to one of ordinary skill in the art to combine Teoh, Sano, and Pokorny with a reasonable expectation of success as all three address identifying problematic shape regions across mask layers in integrated circuit layout.
Response to Arguments
Applicant's arguments filed on August 13, 2026 have been fully considered but are moot in view of the new grounds of rejection necessitated by Applicant's amendment.
Applicant argues that Teoh and Culp do not teach providing a keyword comprising a location-specific identifier of at least one circuit boundary, updating a circuit identification file with the keyword based on identifying the problematic content, and using the location-specific identifier during construction placement checking to determine the boundary from which the separation spacing is checked. These amended limitations are now addressed by Sano.
Sano teaches an adjacent placement risk attribute assigned to a specified edge of a cell and noted in the external-form/terminal-position information library of the cell library, and the placement-position correcting unit reads that edge attribute to detect the risk boundary and insert a predetermined grid spacing measured from that edge to an adjacent cell. Accordingly, the combination of Teoh and Sano teaches the amended limitations, and the rejections are maintained as set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANWER AHMED ALAWDI/
Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
