Listed by the USPTO as ALAWDI, ANWER AHMED
Tech Center 2800 • Art Units: 2147 2851
This examiner grants 75% of resolved cases
Anwer Ahmed Alawdi is an examiner in Tech Center 2800 and Art Unit 2147. The examiner has 12 resolved cases and an allowance rate of 75.0 percent. The median days to allowance for these cases is 1461. This pendency of 1461 days is a metric for applicants to consider when managing their patent portfolios.
The interview lift is 16.7 percent, which indicates a correlation between conducting interviews and obtaining an allowance. Major companies appearing before this examiner include International Business Machines Corporation, Samsung Electronics Co., Ltd., and Google LLC. The firms ADELI LLP, BIRCH STEWART KOLASCH & BIRCH, LLP, and Haynes and Boone, LLP are among the top representatives. With 12 resolved cases, the 75.0 percent allowance rate provides a baseline for applicants who utilize direct communication with the examiner. The 16.7 percent interview lift suggests that oral advocacy is a factor in successful prosecution.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18631815 | COMPUTING SYSTEM AND INTEGRATED CIRCUIT DESIGN SYSTEM USING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18394330 | LAYOUT CORRECTION METHOD AND MASK MANUFACTURING METHOD USING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 17895246 | DESIGN SYSTEM, DESIGN METHOD AND METHOD OF MANUFACTURE OF SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18623977 | GENERATING DESCRIPTIONS OF INTEGRATED CIRCUITS USING NEURAL NETWORKS | Non-Final OA | Google LLC |
| 17780401 | FLUX QUBIT READOUT OF TRANSMON QUBITS | Non-Final OA | Google LLC |
| 18122612 | Systems And Methods For Correcting Errors in Code For Circuit Designs | Final Rejection | Intel Corporation |
| 18655367 | METHOD AND DEVICE FOR CHARGING AND DISCHARGING BATTERY SYSTEM, BATTERY SYSTEM AND ELECTRIC VEHICLE | Non-Final OA | CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED |
| 18289902 | HIGH-LEVEL SYNTHESIS DEVICE, HIGH-LEVEL SYNTHESIS METHOD, AND INFORMATION PROCESSING DEVICE | Non-Final OA | Mitsubishi Electric Corporation |
| 17559442 | METHOD FOR TIMING SIGNOFF IN MIXED-TRANSISTOR DESIGNS | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18522162 | METHOD FOR DESIGNING INTEGRATED CIRCUIT LAYOUT BY USING ANALOG/MIXED-SIGNAL STANDARD CELLS THAT DO NOT VIOLATE LAYOUT RULES OF DIGITAL STANDARD CELLS AND ASSOCIATED COMPUTER SYSTEM | Non-Final OA | Mediatek INC. |
| 18455745 | CIRCUIT DESIGN WITH ENSEMBLE-BASED LEARNING | Final Rejection | International Business Machines Corporation |
| 18349390 | DEFINED CIRCUIT STRUCTURE PATTERN IDENTIFICATION AND PLACEMENT AVOIDANCE | Final Rejection | International Business Machines Corporation |
| 17816178 | QUBIT COUPLING OVER DISTANCE WITH MULTI-MODE BUSES | Non-Final OA | International Business Machines Corporation |
| 17834852 | CONTROLLED JITTER INJECTION INTO A SIGNAL | Non-Final OA | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 18484016 | SCALING FOR DIE-LAST ADVANCED IC PACKAGING | Non-Final OA | Applied Materials, Inc. |
| 17545781 | RECIPE OPTIMIZATION THROUGH MACHINE LEARNING | Final Rejection | Applied Materials, Inc. |
| 17833439 | Semiconductor Device Simulation Platform | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17796434 | DETERMINING LITHOGRAPHIC MATCHING PERFORMANCE | Final Rejection | ASML NETHERLANDS B.V. |
| 17936838 | WIRING QUALITY TEST METHOD AND APPARATUS AND STORAGE MEDIUM | Final Rejection | CHANGXIN MEMORY TECHNOLOGIES, INC. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy75.0% of resolved applications examined by Anwer Ahmed Alawdi were allowed (12 resolved cases), compared with 47.4% across Art Unit 2147 over the last five years.
This examiner's interview lift is +16.7 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Anwer Ahmed Alawdi took 1,461 days on average from filing to allowance.
Anwer Ahmed Alawdi examines applications in Art Unit 2147 in Tech Center 2800 (Semiconductors, Circuits & Optics).
