Prosecution Insights
Last updated: April 19, 2026
Application No. 18/349,412

SEMICONDUCTOR PACKAGE SUBSTRATE WITH STRESS BUFFER PADS AND METHODS FOR MAKING THE SAME

Non-Final OA §102§103
Filed
Jul 10, 2023
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
86%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
700 granted / 929 resolved
+7.3% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
53 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
19.7%
-20.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of Group I, species A, claims 19-20, in the reply filed on 10/16/25 is acknowledged. Applicant’s cancellation of non-elected claims 1-18 is acknowledged. Applicant’s addition of new claims 21-38 is acknowledged. Claims 19-38 are pending and subject to examination at this time. Allowable Subject Matter Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Objections Claims 26 and 37-38 are objected to because of the following informalities: There are grammatical issues as highlighted below. Appropriate correction is needed. In claim 26, “forming a bonding pad over the second layer of dielectric material the bonding pad electrically connected to the first conductive interconnect structures”. (A comma seems missing.) In claim 37, “…and the stress buffer pad. curing the second layer of dielectric material at a temperature…”. (It seems the period should be replaced with a comma. In claim 38, there is an extra period at the end of the limitation. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 19-21, 25-27, 29, 30, 32-35 and 38 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liang et al., US Publication No. 2016/0322337 A1. Liang anticipates: 19. A method of fabricating a package substrate, comprising (see figs. 1-4 and 12-13): forming a conductive interconnect structure (116) within a dielectric material (120a) over a surface of a substrate core (144); forming a stress buffer pad (134) over the conductive interconnect structure; forming a bonding pad (128) over the stress buffer layer pad, wherein the stress buffer (134) pad is vertically separated from and at least partially overlapping with the bonding pad (128); and forming a passivation layer (120b or 138) covering a portion of the bonding pad (128). See Liang at para. [0001] – [0101], figs. 1-15 20. The method of claim 19, wherein a ratio of a minimum width dimension of the stress buffer pad (d4) to a minimum width dimension of the bonding pad (d3) is at least 0.7 (e.g. See para. [0027] - [0028] and figs. 3-4, the dimension d4 is greater than dimension d3 by an amount of dimension d2. The dimension d2 is 5-20 µm and the dimension d3 is 150-220 µm. The ratio of d4/d3 = (d3+d2)/d3. Exemplary values of the ratio are (220+5)/220 = 1.02; (150+5)/150 = 1.03; (220+20)/220 = 1.09; and (150+20)/150 = 1.13.) 21. The method of claim 20, wherein the ratio of the minimum width dimension of the stress buffer pad to the minimum width dimension of the bonding pad is less than 1.5 (e.g. See para. [0027] - [0028] and figs. 3-4, the dimension d4 is greater than dimension d3 by an amount of dimension d2. The dimension d2 is 5-20 µm and the dimension d3 is 150-220 µm. The ratio of d4/d3 = (d3+d2)/d3. Exemplary values of the ratio are (220+5)/220 = 1.02; (150+5)/150 = 1.03; (220+20)/220 = 1.09; and (150+20)/150 = 1.13.) 25. The method of claim 19, further comprising forming a plurality of additional stress buffer pads over the conductive interconnect structure and a plurality of additional bonding pads, wherein each additional stress buffer pad is vertically separated from and at least partially overlaps a corresponding additional bonding pad (e.g. See figs. 12-13, at least two stress buffer pads 134 and bonding pads 128 are shown.) 26. A method of fabricating a package substrate, comprising: forming a substrate core (144) having a first surface and a second surface opposite the first surface; forming core metal features (126) over the second surface of the substrate core; forming a first layer (120a) of dielectric material over the core metal features and first conductive interconnect structures (116 or 130) within the first layer of dielectric material (120a), the first conductive interconnect structures electrically connected to the core metal features (126); forming a stress buffer pad (134) over the first layer of dielectric material (120a), the stress buffer pad (134) having a minimum width dimension (d4); forming a second layer of dielectric material (120b) over the first layer of dielectric material and the stress buffer pad; forming a bonding pad (128) over the second layer of dielectric material, the bonding pad electrically connected to the first conductive interconnect structures (116 or 130) by a via (129) in the second layer of dielectric material (120b), the bonding pad (128) having a minimum width dimension (d3) such that a ratio of the minimum width dimension of the stress buffer pad to the minimum width dimension of the bonding pad is at least 0.7 (e.g. See para. [0027] - [0028] and figs. 3-4, the dimension d4 is greater than dimension d3 by an amount of dimension d2. The dimension d2 is 5-20 µm and the dimension d3 is 150-220 µm. The ratio of d4/d3 = (d3+d2)/d3. Exemplary values of the ratio are (220+5)/220 = 1.02; (150+5)/150 = 1.03; (220+20)/220 = 1.09; and (150+20)/150 = 1.13.), wherein the bonding pad (128) at least partially overlaps the stress buffer pad (134) in a vertical direction; and forming a passivation layer (138) over the second layer of dielectric material, the passivation layer (138( defining an outer surface of the package substrate and exposing a portion of the bonding pad (128) through an opening (e.g. opening occupied by 136) in the passivation layer. See Liang at para. [0001] – [0101], figs. 1-15 27. The method of claim 26, wherein forming the stress buffer pad comprises: depositing a first layer of conductive material over the first layer of dielectric material (120a) and electrically contacting the first conductive interconnect structures (e.g. interpreted as 116 in claim 26.); and etching the first layer of conductive material through a photolithographically-patterned mask to form the stress buffer pad (134), para. [0059]. 29. The method of claim 26, wherein the minimum width dimension of the stress buffer pad (134) is equal to a shortest distance between peripheral edges of the stress buffer pad through a geometric center of the stress buffer pad (e.g. See circle in fig. 4, para. [0028]) Regarding claim 30: Liang teaches the limitations as applied to claim 20 above. Regarding claim 32: Liang teaches the limitations as applied to claim 25 above. Regarding claim 33: Liang teaches the limitations as applied to claims 20 and 26 above. Liang further teaches the added limitations: the stress buffer pad (134) having a ring shape; the bonding pad (128) comprising a ring shaped bonding pad region (e.g. See ring shapes in fig. 4.) Liang further teaches: 34. The method of claim 33, wherein forming the stress buffer pad (134) comprises electroplating a conductive material within an opening in the first layer of dielectric material (120a) and over at least a portion of a surface of the first layer of dielectric material, para. [0058] – [0059]. 35. The method of claim 33, wherein the stress buffer pad and the bonding pad are composed of copper, para. [0058] – [0059]. 38. The method of claim 33, wherein the stress buffer pad (134) closer to the bonding pad (128) than to the substrate core (144), figs. 3 and 12-13. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 24, 31, 36 and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang, as applied to claims 19 and 26 above. Regarding claims 24 and 31: Liang teaches all the limitations of claims 19 and 26 above and further teaches: wherein a vertical separation between the stress buffer pad and the bonding pad is between 20 µm and 40 µm (e.g. The separation distance between the stress buffer pad 134 and the bonding pad 128 is approximately the height of dielectric layer 120b. Liang teaches dielectric layer 120b has similar dimensions as dielectric layer 120a that has a thickness of 3-30 µm. See Liang at para. [0055], [0060]. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.) Regarding claim 36: Liang teaches all the passivation layer (138) comprises a dielectric material, para. [0070]. Liang does not expressly teach the passivation layer comprises a solder resist material. It would have been obvious to one having ordinary skill in the art to form the passivation layer comprises a solder resist material, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. Regarding claim 37: Liang further teaches: 37. The method of claim 33, further comprising forming the second layer (120b) of dielectric material by vacuum laminating a polymer-based dielectric film over the first layer of dielectric material and the stress buffer pad (134) curing the second layer of dielectric material at a temperature… after forming the lower portion of the stress buffer pad, para. [0055], [0060]. Liang is silent the temperature is between 170°C and 200°C. However, absent any disclosure by the Applicant that a temperature between 170°C and 200°C is critical or provides for unexpected results, such a temperature can be considered within the skill level of one of ordinary skill in the art or by the guidance provided by Liang. See MPEP § 2144.05, Obviousness of Ranges: “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” (Emphasis added.) In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.) [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Claim(s) 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang, as applied to claim 19 above, in view of Lin et al., US Publication No. 2019/0090391 A1. Regarding claims 22 and 23: Liang teaches all the limitations of claim 19 above and further teaches the stress buffer pad and bonding pad is made of Cu, a Cu alloy, Ti or ENEPIG at para. [0058] – [0060]. Liang does not expressly teach: wherein the stress buffer pad is composed of a material having a higher Young's modulus than a Young's modulus of a material of the bonding pad; wherein the bonding pad is composed of a metal material and the stress buffer pad is composed of a ceramic material. In an analogous art, Lin teaches a stress buffer pad (e.g. stress modulator 43) is composed of a ceramic material, metal or metal alloys, para. [0041], figs 7 and 18. One of ordinary skill in the art modifying Liang with Lin to form the stress buffer pad of a ceramic a material, as taught by Lin, would form: wherein the stress buffer pad is composed of a material (e.g. ceramic) having a higher Young's modulus than a Young's modulus of a material of the bonding pad (e.g. Cu); wherein the bonding pad is composed of a metal material (e.g. Cu) and the stress buffer pad is composed of a ceramic material. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Liang with the teachings of Li because one of ordinary skill in the art would be motivated to look for alternative materials for the stress buffer pad and Li teaches ceramics is a known material suitable as an stress modulator. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle. 325 U.S. at 335, 65 USPQ at 301.” It is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 13 January 2026
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Prosecution Timeline

Jul 10, 2023
Application Filed
Jan 13, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
86%
With Interview (+11.2%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allow rate.

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