Prosecution Insights
Last updated: July 17, 2026
Application No. 18/349,440

SEMICONDUCTOR DEVICE PACKAGE

Final Rejection §103§112
Filed
Jul 10, 2023
Priority
Jul 12, 2022 — provisional 63/368,202
Examiner
NIELSEN, DEREK LANG
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
41 granted / 60 resolved
At TC average
Strong +41% interview lift
Without
With
+41.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
20 currently pending
Career history
80
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
93.7%
+53.7% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 60 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This Office Action is in response to the Amendment and Request for Reconsideration filed March 10, 2026. Applicant’s amendments to claims 17, 19-20, 27 and 38 have been entered. Claims 17-38 are pending. Election/Restrictions In the previous Office Action filed December 11, 2025, claims 23, 24, 26-29, and 36-38 were withdrawn from consideration, as being directed to an invention that is independent or distinct from the invention originally claimed. However, in view of Applicant’s arguments, on pages 9-11, which distinctly and specifically point out supposed errors in the restriction requirement, the restriction requirement as set forth in the Office Action filed December 11, 2025 has been withdrawn. Specifically, Applicant persuasively argues on page 9 that claims 23, 24, 26-29, and 36-38 do not exhibit characteristics that are mutually exclusive with the subject matter of the original claims. Claims 23, 24, 26-29, and 36-38 are hereby rejoined and fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, Applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. Response to Amendment The amendments to the claims filed March 10, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed December 11, 2025. Response to Arguments Applicant’s amendments and supporting arguments filed March 10, 2026, with respect to the rejection(s) of claim(s) 17-22, 25, 30, 31, 33, and 34 under 35 U.S.C. 102(a)(1), have been fully considered and are persuasive. Specifically, Miura does not explicitly teach at least the following limitations of amended claim 1: “a first side wing and a second side wing that bend toward a bottom side of the molded body”. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103. Applicant’s arguments on pages 11-12, with respect to the 35 U.S.C. 102(a)(1) rejections, have been fully considered but are moot because they do not apply to the references as applied in the current Office Action. The 35 U.S.C. 102(a)(1) rejections have been withdrawn, and the new ground(s) of rejection, made under 35 U.S.C. 103, rely on additional references, as explained below. In response to Applicant’s argument on page 12 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claims, as amended, see the rejections of the claims below. Claim Objections Claim 37 is objected to because of the following informalities: claim 37 recites, inter alia, “a portion of the lead extending to an outside the molded body”. This appear to be a typo, and has been interpreted as “a portion of the lead extending to an outside of the molded body”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 27 and 37 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 27 recites, inter alia, “wherein only the first side wing and the second side wing of the drain contact lead extend outside of the molded body”; similarly, claim 37 recites, inter alia, “wherein only the side wings having the end tips of the drain contact lead extend to the outside of the molded body”. However, these limitations are not supported by either Applicant’s nonprovisional or provisional specifications, which describe additional leads extending outside of the molded body (see FIGs. 1-8 and associated text). A person having ordinary skill in the art at the time the application was filed would not have recognized that the inventor was in possession of the invention as claimed in view of the disclosure of the application as filed because, in addition to the drain contact lead, additional leads extending outside of the molded body are understood to be essential for device functionality (see Applicant’s specification [0044]). Applicant has not pointed out where the amended claim is supported, nor does there appear to be a written description of the claim limitations “wherein only the first side wing and the second side wing of the drain contact lead extend outside of the molded body” or “wherein only the side wings having the end tips of the drain contact lead extend to the outside of the molded body” in the application as filed. To comply with the written description requirement of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, or to be entitled to an earlier priority date or filing date under 35 U.S.C. 119, 120, 365, or 386, each claim limitation must be expressly, implicitly, or inherently supported in the originally filed disclosure. When an explicit limitation in a claim "is not present in the written description whose benefit is sought it must be shown that a person of ordinary skill would have understood, at the time the patent application was filed, that the description requires that limitation." Hyatt v. Boone, 146 F.3d 1348, 1353, 47 USPQ2d 1128, 1131 (Fed. Cir. 1998); see MPEP 2163. This rejection may be overcome by amending claims 27 and 37 to recite only those limitations which can be supported by Applicant’s specification. For examination purposes, this limitation will be interpreted as “wherein the first side wing and the second side wing of the drain contact lead extend outside of the molded body but other portions of the drain contact lead do not extend outside of the molded body”, with regard to claim 27; and “wherein the side wings having the end tips of the drain contact lead extend to the outside of the molded body but other portions of the drain contact lead do not extend outside of the molded body”, with regard to claim 37. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 17-23, 25-27, 29-31, 33, 34, and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Miura, US 2019/0326204 A1 (hereinafter Miura) in view of Fuergut et al., US 2022/0157682 A1 (hereinafter Fuergut). Regarding claim 17, as amended, Miura discloses: A method for fabricating a package, the method comprising: disposing a semiconductor die on a substrate (Miura, FIGs. 1-7, semiconductor element 1, a power MOSFET, [0046-0048]); attaching a drain contact lead to the semiconductor die (Miura, FIGs. 1-7, third lead 5, “third lead 5 [the drain contact lead] is a conductive member that is electrically connected to the drain electrode 13 of the semiconductor element 1 [the semiconductor die],” [0075]); and encapsulating the semiconductor die in a molded body (Miura, FIGs. 1-7, sealing resin 2, [0053-0054]), wherein the molded body is a six- sided rectangular box-like structure (Miura, FIGs. 1-7, show sealing resin 2 [the molded body] as a six-sided rectangular box-like structure) and at least a corner portion of the molded body formed by two adjacent sides is devoid of molding material (Miura, FIG. 7, shows corner portion of two adjacent sides of sealing resin 2 [the molded body] devoid of molding material on the left side) (Miura, FIGs. 1-7, “third lead 5 [the drain contact lead] includes a third exposure part 52 [the portion of the drain contact lead] exposed from the sealing resin 2 [the molded body],” [0079]), Miura is silent regarding reducing a size and a weight of the molded body. However, the claim language reducing a size and a weight of the molded body has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. A "‘whereby clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited.’" Id. (quoting Minton v. Nat’l Ass’n of Securities Dealers, Inc., 336 F.3d 1373, 1381, 67 USPQ2d 1614, 1620 (Fed. Cir. 2003)). MPEP 2111.04. Miura is silent regarding: the portion including a first side wing and a second side wing that bend toward a bottom side of the molded body. However, Fuergut, in the same field of endeavor, teaches: the portion including a first side wing (Fuergut, FIG. 11, third group 146, [0119-0121]) and a second side wing (Fuergut, FIG. 11, fourth group 148, [0119-0121]) that bend toward a bottom side of the molded body (Fuergut, FIG. 11 shows third group 146 [the first side wing] and fourth group 148 [the second side wing] bend toward a bottom side of the encapsulant 114 [the molded body], [0067; 0119-0121]; “carrier 106 and the leads 110 [including third group 146 [the first side wing] and fourth group 148 [the second side wing]] form part of a common patterned and bent metal plate,” [0119]). Fuergut teaches that bending the leads, i.e., the first and second side wings, downwardly, i.e., toward the bottom side of the molded body, enables a simplified electrical connection at the bottom side of the electrical component (Fuergut, [0067]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura with the teachings of Fuergut, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Fuergut, to simplify electrical connection at the bottom side of the electrical component, thereby improving manufacturing efficiency. Regarding claim 18, Miura in view of Fuergut teaches: The method of claim 17, further comprising: disposing a heat dissipating surface in a top surface of the molded body (Miura, FIGs. 1-7, surface 50 b, copper, [0055]); and thermally coupling the semiconductor die encapsulated in the molded body to the heat dissipating surface (Miura, FIGs. 1-7, semiconductor element 1 shown thermally coupled to surface 50 b [the heat dissipating surface] of third lead 5, made of copper, [0055]). PNG media_image1.png 703 595 media_image1.png Greyscale Regarding claim 19, as amended, Miura in view of Fuergut teaches: The method of claim 17, further comprising: notching the portion of the drain contact lead extending to an outside of the molded body (Fuergut, FIG. 11 shows notch at top center of carrier 106 between leads 110, i.e., the portion of the drain contact lead extending to an outside of the molded body), wherein the first side wing (Fuergut, FIG. 11, third group 146) and the second side wing (Fuergut, FIG. 11, fourth group 148) oppose each other such that the portion of the drain contact lead forms a U-shaped connector (Fuergut, FIG. 11, shows third group 146 [the first side wing] and the fourth group 148 [the second side wing] oppose each other about the centerline of carrier 106 between leads 110 [the portion of the drain contact lead] forming a U-shaped connector (Fuergut, see annotated FIG. 11 showing letter U). Fuergut teaches that by providing a notch at top center of carrier 106 between leads 110, i.e., the portion of the drain contact lead extending to an outside of the molded body, the notch allows for the exterior of the molded body to be manufactured with or without an indention between leads (Fuergut, see FIGs. 11 and 24-26). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura with the teachings of Fuergut, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be to simplify manufacturing by minimizing the number of unique parts required for variations in packaging, thereby reducing costs and improving manufacturing efficiency. Regarding claim 20, as amended, Miura discloses: A method for fabricating a package, the method comprising: disposing a semiconductor die on a substrate (Miura, FIGs. 1-7, semiconductor element 1, a power MOSFET, [0046-0048]); encapsulating the semiconductor die in a molded body (Miura, FIGs. 1-7, sealing resin 2, [0053-0054]), wherein the molded body is a six- sided rectangular box-like structure (Miura, FIGs. 1-7, show sealing resin 2 [the molded body] as a six-sided rectangular box-like structure); attaching a drain contact lead to the semiconductor die (Miura, FIGs. 1-7, third lead 5, “third lead 5 [the drain contact lead] is a conductive member that is electrically connected to the drain electrode 13 of the semiconductor element 1 [the semiconductor die], [0075]), a portion of the drain contact lead extending to an outside of the molded body and forming an external terminal of the package (Miura, FIGs. 1-7, “the third lead 5 [the drain contact lead] is electrically connected to the drain electrode 13 of the semiconductor element 1 [the semiconductor die], the mounting surface 50 b [the portion of the drain contact lead forming an external terminal of the package] becomes a drain terminal of the semiconductor device,” [0077]), Miura is silent regarding: an end of the portion branching into a first end tip and a second end tip; and notching the portion of the drain contact lead extending to the outside of the molded body to reduce a strength of the drain contact lead, wherein a notch is formed between the first end tip and the second end tip. The claim language to reduce a strength of the drain contact lead has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. MPEP 2111.04. Fuergut, in the same field of endeavor, teaches: an end of the portion branching into a first end tip and a second end tip (Fuergut, FIG. 11 shows upper portion of carrier 106 [the portion of the drain contact lead extending to the outside of the molded body] branching into leads 110, having third group 146 [the first end tip] and the fourth group 148 [the second end tip]; “carrier 106 and the leads 110 [including third group 146 [the first side wing] and fourth group 148 [the second side wing]] form part of a common patterned and bent metal plate,” [0119]); and notching the portion of the drain contact lead extending to the outside of the molded body … wherein a notch is formed between the first end tip and the second end tip (Fuergut, FIG. 11 shows notch at top center of upper portion of carrier 106 [the portion of the drain contact lead extending to the outside of the molded body] between third group 146 [the first end tip] and the fourth group 148 [the second end tip]). Fuergut teaches that this configuration “renders the package appropriate even for complex electronic applications while achieving sufficiently large creepage and clearance distances,” (Fuergut, [0069]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura with the teachings of Fuergut, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Fuergut, to achieve sufficiently large creepage and clearance distances, thereby improving package performance in complex electronic applications. Regarding claim 21, Miura in view of Fuergut teaches: The method of claim 20, further comprising: disposing a heat dissipating surface in a top surface of the molded body (Miura, FIGs. 1-7, surface 50 b, copper, [0055]); and thermally coupling the semiconductor die encapsulated in the molded body to the heat dissipating surface (Miura, FIGs. 1-7, semiconductor element 1 shown thermally coupled to surface 50 b [the heat dissipating surface] of third lead 5, made of copper, [0055]). Regarding claim 22, Miura in view of Fuergut teaches: The method of claim 20, wherein encapsulating the semiconductor die in the molded body (Miura, FIGs. 1-7, sealing resin 2, [0053-0054]) includes excluding mold material from at least a corner portion of the molded body formed by two adjacent sides (Miura, FIG. 7, shows corner portion of two adjacent sides of sealing resin 2 [the molded body] excluding mold material on the left side) Miura in view of Fuergut is silent regarding to reduce a size and a weight of the molded body. However, the claim language to reduce a size and a weight of the molded body has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. MPEP 2111.04. Regarding claim 23, Miura in view of Fuergut teaches: The method of claim 20, further comprising: forming a pair of cutouts in the molded body extending from a bottom side toward a top side of the molded body (Fuergut, FIG. 3, steps 130 and 132 [the pair of cutouts] shown extending from a bottom side toward a top side of encapsulant 114 [the molded body], [0116]), (Fuergut, FIG. 3 shows steps 130 and 132 [the pair of cutouts] formed equidistant from left side [a first side] and right side [an opposing second side] of encapsulant 114 [the molded body]; “the steps 130, 132 are arranged symmetrically with respect to a mirror plane extending vertically and into the paper plane of FIG. 3,” [0116]). The claim language the cutouts forming clamping surfaces along sides of the molded body to clamp the package on a printed circuit board has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. MPEP 2111.04. Regarding claim 25, Miura in view of Fuergut teaches: The method of claim 20, further comprising: connecting a plurality of signal leads to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including at least a source contact pad (Miura, FIGs. 1-7, source electrode 12, [0056-0057]) the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Miura, see FIGs. 1-7), wherein the source contact pad is attached to a respective group of signal leads by a direct lead attach (DLA) clip (Miura, FIGs. 1-7, “the first lead 3 is directly bonded to the source electrode 12 [the source contact pad] of the semiconductor element 1. Thus, it is possible to reduce the internal resistance of the semiconductor device A1 compared with the case of being electrically connected via a bonding wire or a bonding ribbon,” [0092]; note that Applicant’s definition of a “direct lead attach (DLA) process” is substantially identical to the method of connecting the device contact pads on the semiconductor die to the signal leads as disclosed by Miura, (see Applicant’s specification [0046-0047])). Regarding claim 26, Miura in view of Fuergut teaches: The method of claim 20, wherein the semiconductor die is a first semiconductor die (Fuergut, FIGs. 17-18, electronic component 108, [0156]), and wherein the package comprises a second semiconductor die encapsulated in the molded body (Fuergut, FIGs. 17-18, electronic component 108′, [0156]), and wherein the first semiconductor die is an insulated-gate bipolar transistor (IGBT) (Fuergut, electronic component 108 configured as IGBT, [0113]), and the second semiconductor die is a fast recovery diode (FRD) or a silicon carbide diode (Fuergut, electronic component 108 configured as diode, [0113; 0156]; “exemplary embodiments may be implemented in GaN or SiC technology,” [0083]). Regarding claim 27, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Miura in view of Fuergut teaches: The method of claim 17, further comprising: wherein the drain contact lead is shaped as a metal plate that branches into the first side wing and the second side wing (Fuergut, see FIG. 11, “carrier 106 and the leads 110 [including third group 146, analogous to the first side wing, and fourth group 148, analogous to the second side wing] form part of a common patterned and bent metal plate,” [0119]), [[wherein only the first side wing and the second side wing of the drain contact lead extend outside of the molded body]] wherein the first side wing and the second side wing of the drain contact lead extend outside of the molded body but other portions of the drain contact lead do not extend outside of the molded body. (Fuergut, FIG. 11 shows third group 146, analogous to the first side wing, and fourth group 148, analogous to the second side wing, of carrier 106 and the leads 110, analogous to the drain contact lead, extending outside of encapsulant 114 [the molded body] but other portions of carrier 106 and the leads 110, analogous to the drain contact lead, do not extend outside of the molded body. Regarding claim 29, Miura in view of Fuergut teaches: The method of claim 17, further comprising: forming a pair of cutouts in the molded body extending from a bottom side toward a top side of the molded body (Fuergut, FIG. 3, steps 130 and 132 [the pair of cutouts] shown extending from a bottom side toward a top side of encapsulant 114 [the molded body], [0116]), (Fuergut, FIG. 3 shows steps 130 and 132 [the pair of cutouts] formed equidistant from left side [a first side] and right side [an opposing second side] of encapsulant 114 [the molded body]; “the steps 130, 132 are arranged symmetrically with respect to a mirror plane extending vertically and into the paper plane of FIG. 3,” [0116]). The claim language the cutouts forming clamping surfaces along sides of the molded body to clamp the package on a printed circuit board has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. MPEP 2111.04. Regarding claim 30, Miura in view of Fuergut teaches: The method of claim 17, wherein the semiconductor die is attached to a die attach pad (DAP) on the substrate with a solder (Miura, FIGs. 1-7, semiconductor element 1 [the semiconductor die] bonded with solder, [0082-0086]). Regarding claim 31, Miura in view of Fuergut teaches: The method of claim 17, wherein the semiconductor die is attached to a die attach pad (DAP) on the substrate with a silver-based sinter (Miura, FIGs. 1-7, semiconductor element 1 [the semiconductor die] bonded with silver (Ag) paste, i.e., a silver-based sinter, [0082-0086]). Regarding claim 33, Miura in view of Fuergut teaches: The method of claim 17, further comprising: connecting a plurality of signal leads connected to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including at least a source contact pad (Miura, FIGs. 1-7, source electrode 12, [0056-0057]), the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Miura, see FIGs. 1-7), wherein the source contact pad is aluminum wire bonded to a respective group of signal leads (Miura discloses electrically connecting the source electrode 12 [the source contact pad] to the first lead 3 [the respective group of signal leads] via wire bonding, but also discloses that this may be less than optimal, [0092]; MPEP 2131.05). Regarding claim 34, Miura in view of Fuergut teaches: The method of claim 17, further comprising: connecting a plurality of signal leads to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including at least a source contact pad (Miura, FIGs. 1-7, source electrode 12, [0056-0057]) the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Miura, see FIGs. 1-7), wherein the source contact pad is attached to a respective group of signal leads by a direct lead attach (DLA) clip (Miura, FIGs. 1-7, “the first lead 3 is directly bonded to the source electrode 12 [the source contact pad] of the semiconductor element 1. Thus, it is possible to reduce the internal resistance of the semiconductor device A1 compared with the case of being electrically connected via a bonding wire or a bonding ribbon,” [0092]; note that Applicant’s definition of a “direct lead attach (DLA) process” is substantially identical to the method of connecting the device contact pads on the semiconductor die to the signal leads as disclosed by Miura, (see Applicant’s specification [0046-0047])). Regarding claim 36, Miura in view of Fuergut teaches: The method of claim 17, wherein the semiconductor die is a first semiconductor die (Fuergut, FIGs. 17-18, electronic component 108, [0156]), and wherein the package comprises a second semiconductor die encapsulated in the molded body (Fuergut, FIGs. 17-18, electronic component 108′, [0156]), and wherein the first semiconductor die is an insulated-gate bipolar transistor (IGBT) (Fuergut, electronic component 108 configured as IGBT, [0113]), and the second semiconductor die is a fast recovery diode (FRD) or a silicon carbide diode (Fuergut, electronic component 108 configured as diode, [0113; 0156]; “exemplary embodiments may be implemented in GaN or SiC technology,” [0083], i.e., a silicon carbide diode). Regarding claim 37, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Miura discloses: A method for fabricating a package, the method comprising: disposing a semiconductor die on a substrate (Miura, FIGs. 1-7, semiconductor element 1, a power MOSFET, [0046-0048]); encapsulating the semiconductor die in a molded body (Miura, FIGs. 1-7, sealing resin 2, [0053-0054]), wherein the molded body is a six- sided rectangular box-like structure (Miura, FIGs. 1-7, show sealing resin 2 [the molded body] as a six-sided rectangular box-like structure); and attaching at least a lead to a device contact pad on the semiconductor die (Miura, FIGs. 1-7, third lead 5, “third lead 5 [the drain contact lead] is a conductive member that is electrically connected to the drain electrode 13 of the semiconductor element 1 [the semiconductor die], [0075]), a portion of the lead extending to an outside the molded body and forming an external terminal of the package (Miura, FIGs. 1-7, “third lead 5 [the drain contact lead] includes a third exposure part 52 [the portion of the drain contact lead] exposed from the sealing resin 2 [the molded body],” [0079]), . Miura is silent regarding: wherein the lead is a drain contact lead shaped as a metal plate which extends to form a U-shape connector with side wings having end tips, wherein the side wings having the end tips of the drain contact lead extend to the outside of the molded body but other portions of the drain contact lead do not extend outside of the molded body. However, Fuergut, in the same field of endeavor, teaches: wherein the lead is a drain contact lead shaped as a metal plate which extends to form a U-shape connector with side wings having end tips (Fuergut, see FIG. 11, “carrier 106 and the leads 110 [analogous to the drain contact lead with side wings, having end tips shown as third group 146 and fourth group 148] form part of a common patterned and bent metal plate,” [0119], shown as a U-shaped connector), wherein the side wings having the end tips of the drain contact lead extend to the outside of the molded body but other portions of the drain contact lead do not extend outside of the molded body (Fuergut, FIG. 11 shows leads 110 [the side wings having the end tips shown as third group 146 and fourth group 148] extending to the outside of encapsulant 114 [the molded body]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura with the teachings of Fuergut, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Fuergut, to simplify electrical connection at the bottom side of the electrical component, thereby improving manufacturing efficiency. Regarding claim 38, Miura discloses: A method for fabricating a package, the method comprising: disposing a semiconductor die on a substrate (Miura, FIGs. 1-7, semiconductor element 1, a power MOSFET, [0046-0048]); attaching a drain contact lead to the semiconductor die (Miura, FIGs. 1-7, third lead 5, “third lead 5 [the drain contact lead] is a conductive member that is electrically connected to the drain electrode 13 of the semiconductor element 1 [the semiconductor die], [0075]), an end portion of the drain contact lead branching into a first end tip (Miura, FIG. 1, left side instance of first portion 521a) and a second end tip (Miura, FIG. 1, right side instance of first portion 521a) ; encapsulating the semiconductor die in a molded body (Miura, FIGs. 1-7, sealing resin 2, [0053-0054]), wherein the molded body is a six- sided rectangular box-like structure (Miura, FIGs. 1-7, show sealing resin 2 [the molded body] as a six-sided rectangular box-like structure); Miura is silent regarding: forming a pair of cutouts in the molded body extending from a bottom side toward a top side of the molded body, the cutouts forming clamping surfaces along sides of the molded body to clamp the package on a printed circuit board, the pair of cutouts being formed along an axis that is equidistant from a first side and an opposing second side of the molded body. The claim language the cutouts forming clamping surfaces along sides of the molded body to clamp the package on a printed circuit board has not been given patentable weight because it is merely descriptive of the intended result of a claimed method step. MPEP 2111.04. Fuergut, in the same field of endeavor, teaches: forming a pair of cutouts in the molded body extending from a bottom side toward a top side of the molded body (Fuergut, FIG. 3, steps 130 and 132 [the pair of cutouts] shown extending from a bottom side toward a top side of encapsulant 114 [the molded body], [0116]; “This geometry strongly suppresses creepage current flow and ensures a reliable electric isolation of the package 100,” [0116]), … the pair of cutouts being formed along an axis that is equidistant from a first side and an opposing second side of the molded body (Fuergut, FIG. 3 shows steps 130 and 132 [the pair of cutouts] formed equidistant from left side [a first side] and right side [an opposing second side] of encapsulant 114 [the molded body]; “the steps 130, 132 are arranged symmetrically with respect to a mirror plane extending vertically and into the paper plane of FIG. 3,” [0116]). Fuergut teaches that a symmetric configuration of the steps, i.e., the cutouts, ensures reliable protection against creepage current at both or all sides of the package equally, (Fuergut, [0063]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura with the teachings of Fuergut, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Fuergut, to achieve reliable protection against creepage current, thereby improving package performance in complex electronic applications. Claims 24, 28, 32, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of Fuergut, and further in view of Abe et al., US 2021/0305175 A1 (hereinafter Abe). Regarding claim 24, Miura in view of Fuergut teaches: The method of claim 20, further comprising: connecting a plurality of signal leads to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including a gate contact pad (Miura, FIGs. 1-7, gate electrode 11, [0056-0057]), (Miura, FIGs. 1-7, source electrode 12, [0056-0057]), the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Miura, see FIGs. 1-7); and forming a slot in a top surface of the molded body along the side of the molded body (Fuergut, FIG. 3 shows steps 130 and 132 [the slots] in a top surface along the side of encapsulant 114 [the molded body], [0116]; see also [0055]), the slot having a width and a depth to increase a creepage distance to the plurality of signal leads extending to the outside of the molded body from the side of the molded body (Fuergut, “the steps 130, 132 [the slots] ensure a spatially extended and complex trajectory [width and depth] along which a creepage current must flow for unintentionally short-circuiting electrically conductive constituents [the plurality of signal leads extending to the outside of the molded body] of the package 100. This geometry strongly suppresses creepage current flow and ensures a reliable electric isolation of the package 100,” [0116]; see also [0128-0131] describing method of predictably calculating creepage distance based on dimensions of step). Although Miura in view of Fuergut teaches a gate contact pad, Miura in view of Fuergut is silent regarding: a sense contact pad. However, Abe, in the same field of endeavor, teaches a semiconductor device comprising: a sense contact pad (Abe, FIGs. 2, 4, 8, 9, third front-surface electrode 113, “source sense electrode”, [0070]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura in view of Fuergut with the teachings of Abe, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Abe, to provide for additional device functionality. Regarding claim 28, Miura in view of Fuergut teaches: The method of claim 17, further comprising: connecting a plurality of signal leads to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including a gate contact pad (Miura, FIGs. 1-7, gate electrode 11, [0056-0057]), (Miura, FIGs. 1-7, source electrode 12, [0056-0057]), the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Miura, see FIGs. 1-7; Fuergut, see FIG. 11; package 100 includes source S, drain D, gate G, and a further terminal K, [0118]); and forming a slot in a top surface of the molded body along the side of the molded body (Fuergut, FIG. 3 shows steps 130 and 132 [the slots] in a top surface along the side of encapsulant 114 [the molded body], [0116]; see also [0055]), the slot having a width and a depth to increase a creepage distance to the plurality of signal leads extending to the outside of the molded body from the side of the molded body (Fuergut, “the steps 130, 132 [the slots] ensure a spatially extended and complex trajectory [width and depth] along which a creepage current must flow for unintentionally short-circuiting electrically conductive constituents [the plurality of signal leads extending to the outside of the molded body] of the package 100. This geometry strongly suppresses creepage current flow and ensures a reliable electric isolation of the package 100,” [0116]; see also [0128-0131] describing method of predictably calculating creepage distance based on dimensions of step). Although Miura in view of Fuergut teaches a gate contact pad and a source contact pad, Miura in view of Fuergut is silent regarding: a sense contact pad. However, Abe, in the same field of endeavor, teaches a semiconductor device comprising: a sense contact pad (Abe, FIGs. 2, 4, 8, 9, third front-surface electrode 113, “source sense electrode”, [0070]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura in view of Fuergut with the teachings of Abe, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Abe, to provide for additional device functionality. Regarding claim 32, Miura in view of Fuergut teaches: The method of claim 17, further comprising: connecting a plurality of signal leads to a multiplicity of device contact pads on the semiconductor die (Miura, FIGs. 1-7 show first lead 3, second lead 4, and third lead 5 [the plurality of signal leads] connected to source electrode 12, drain electrode 13, and gate electrode 11 [the multiplicity of device contact pads] on semiconductor element 1 [the semiconductor die], [0055-0057]), the multiplicity of device contact pads including a gate contact pad (Miura, FIGs. 1-7, gate electrode 11, [0048-0049]) and Although Miura in view of Fuergut teaches a gate contact pad wire bonded to a respective signal lead, Miura in view of Fuergut teaches is silent regarding: a sense contact pad wire bonded to a respective signal lead. However, Abe, in the same field of endeavor, teaches a semiconductor device comprising: a sense contact pad (Abe, FIGs. 2, 4, 8, 9, third front-surface electrode 113, “source sense electrode”, [0070]), the plurality of signal leads extending to an outside of the molded body from a side of the molded body (Abe, see FIGs. 1, 3), wherein the gate contact pad (Abe, FIGs. 2, 4, 8, 9, second front-surface electrode 112, “gate electrode”, [0067]) and the sense contact pad (Abe, FIGs. 2, 4, 8, 9, third front-surface electrode 113) are wire bonded to a respective pair of signal leads (Abe, FIG. 2 shows second front-surface electrode 112 [the gate contact pad] wire bonded with second wire 32 to second lead 22 [the gate signal lead], [0067; 0082]]; FIG. 2 shows third front-surface electrode 113 [the sense contact pad] wire bonded with third wire 33 to third lead 23 [the source signal lead], [0070; 0076; 0087; 0109-0110]) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura in view of Fuergut with the teachings of Abe, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Abe, to electrically connect the semiconductor element to the lead frame, thereby providing for device functionality. Regarding claim 35, Miura in view of Fuergut teaches: The method of claim 17, wherein the semiconductor die is a silicon carbide (SiC) power transistor (Fuergut, “such a package may comprise an electronic component embodied in SiC MOS technology,” i.e., a silicon carbide (SiC) power transistor, [0088]). Additionally, Abe, in the same field of endeavor, teaches: wherein the semiconductor die is a silicon carbide (SiC) power transistor (Abe, FIGs. 2, 4, 8, 9, semiconductor element 1, SiC (silicon carbide) MOSFET, IGBT, or fast recovery diode, [0060]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Miura in view of Fuergut with the teachings of Abe, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Abe, to make a power semiconductor chip capable of operating under conditions in which the product of the voltage and the current is 1W or more, thereby improving device performance. Conclusion The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure: the STMicroelectronics STHU36N60DM6AG datasheet, published November 2021, discloses similar materials, devices, and methods, including a power MOSFET with fast-recovery diode enclosed in a package with portions of the leads extending to an outside of the molded body; note that Figure 19 of the datasheet shows the drain lead is notched and formed with side wings arranged as a U-shaped connector. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.L.N./Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 10, 2023
Application Filed
Dec 11, 2025
Non-Final Rejection mailed — §103, §112
Mar 06, 2026
Applicant Interview (Telephonic)
Mar 06, 2026
Examiner Interview Summary
Mar 10, 2026
Response Filed
Jun 01, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12660275
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
4y 0m to grant Granted Jun 16, 2026
Patent 12628375
NANOSHEET TRANSISTOR WITH ASYMMETRIC JUNCTION AND ROBUST STRUCTURE STABILITY
4y 7m to grant Granted May 12, 2026
Patent 12621982
SEMICONDUCTOR DEVICE WITH PAD STRUCTURE AND METHOD FOR FABRICATING THE SAME
2y 7m to grant Granted May 05, 2026
Patent 12610825
SEMICONDUCTOR DEVICE
4y 0m to grant Granted Apr 21, 2026
Patent 12598966
METHOD FOR PRODUCING A THROUGH SEMICONDUCTOR VIA CONNECTION
4y 1m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
99%
With Interview (+41.4%)
3y 7m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 60 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month