DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16, 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai(USPGPUB DOCUMENT: 2021/0057333, hereinafter Tsai) in view of Lin (USPGPUB DOCUMENT: 2015/0270156, hereinafter Lin) and JangJian (USPGPUB DOCUMENT: 2016/0111325, hereinafter JangJian).
Re claim 1 Tsai discloses a method, comprising: receiving a workpiece comprising a first conductive feature(110) embedded in a first dielectric layer(114); selectively depositing a capping layer(111) over the first conductive feature(110); forming an opening(115) through the dielectric layer to expose the capping layer(111); and forming a second conductive feature(118) in the opening(115),
Tsai does not disclose planarizing the workpiece to expose a top surface of the first conductive feature; after the planarizing, selectively depositing a capping layer over the exposed top surface of the first conductive feature;
depositing a first etch stop layer (ESL) over the capping layer(111);depositing a glue layer over the first ESL; depositing a second ESL over the glue layer; depositing a second dielectric layer over the second ESL; forming an opening(115) through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer(111); wherein a density of the second ESL is greater than a density of the first ESL;
Lin disclose depositing a first etch stop layer(112/202 of Lin) (ESL) over the capping layer(111);depositing a glue layer(108/120 of Lin) over the first ESL; depositing a second ESL(112/202 of Lin) over the glue layer; depositing a second dielectric layer (114 of Lin) over the second ESL; forming an opening(116) through the second dielectric layer (114 of Lin), the second ESL, the glue layer, and the first ESL; wherein a density of the second ESL is greater than a density of the first ESL (since 112/202 may be bombarded with ions from plasma this may be interpreted as wherein a density of the second ESL is greater than a density of the first ESL).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Tsai in order to have improved method and structure for the sealing layer in a semiconductor device [0003, Lin]. In doing so, forming an opening(116) through the second dielectric layer (114 of Lin), the second ESL, the glue layer, and the first ESL to expose the capping layer(111 of Tsai);
Tsai and Lin does not disclose planarizing the workpiece to expose a top surface of the first conductive feature; after the planarizing, selectively depositing a capping layer over the exposed top surface of the first conductive feature;
JangJian disclose planarizing the workpiece to expose a top surface of the first conductive feature(left36/right36)[0017]; after the planarizing, selectively depositing a capping layer(38) over the exposed top surface of the first conductive feature;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of JangJian to the teachings of Tsai in order to have form interconnect structures, which include metal lines and vias [0002, JangJian].
Re claim 2 Tsai, Lin and JangJian disclose the method of claim 1, wherein the glue layer(108/120 of Lin) comprises aluminum nitride or silicon nitride[0033].
Re claim 3 Tsai, Lin and JangJian disclose the method of claim 1, wherein the first ESL and the second ESL comprise silicon carbonitride[0018].
Re claim 4 Tsai, Lin and JangJian disclose the method of claim 1, wherein a dielectric constant of the second ESL is greater than a dielectric constant of the first ESL.
Re claim 5 Tsai, Lin and JangJian disclose the method of claim 1, further comprising:before the depositing of the second dielectric layer, depositing a third ESL over the second ESL, wherein the third ESL comprises aluminum oxide[0018].
Re claim 6 Tsai, Lin and JangJian disclose the method of claim 1, further comprising:after the selectively depositing of the capping layer(111), replacing the first dielectric layer(114) with a third dielectric layer.
Re claim 7 Tsai, Lin and JangJian disclose the method of claim 6, wherein the third dielectric layer comprises air gaps[0027].
Re claim 8 Tsai discloses a method, comprising: receiving a workpiece comprising a first conductive feature(110) embedded in a first dielectric layer(114);selectively depositing a capping layer(111) over the first conductive feature(110);depositing a first etch stop layer (ESL) over the capping layer(111); forming an opening(115) through the dielectric layer, to expose the capping layer(111); and forming a second conductive feature(118) in the opening(115),
Tsai does not disclose depositing a first etch stop layer (ESL) over the capping layer(111) using a first plasma-enhanced chemical vapor deposition (PECVD) process; after the depositing of the first ESL, depositing a glue layer over the first ESL to interface a top surface of the first ESL; after the depositing of the glue layer, depositing a second ESL over the glue layer using a second PECVD process; depositing a second dielectric layer over the second ESL; forming an opening(115) through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer(111); wherein each of the first PECVD process and second PECVD process comprise high-frequency pulses and low-frequency pulses, wherein, in the first PECVD process, plasma of a nitrogen-containing precursor is introduced during the high-frequency pulses, wherein, in the second PECVD process, plasma of the nitrogen-containing precursor is introduced during both the high-frequency pulses and the low-frequency pulses;
Lin disclose depositing a first etch stop layer (ESL) (112/202 of Lin) using a first plasma-enhanced chemical vapor deposition (PECVD) process[0024 of Lin]; depositing a glue layer (108/120 of Lin) over the first ESL; depositing a second ESL(112/202 of Lin) over the glue layer using a second PECVD process; depositing a second dielectric layer(114 of Lin) over the second ESL; wherein each of the first PECVD process and second PECVD process comprise high-frequency pulses and low-frequency pulses, wherein, in the first PECVD process, plasma of a nitrogen-containing precursor[0017] is introduced during the high-frequency pulses, wherein, in the second PECVD process, plasma of the nitrogen-containing precursor[0017,0018] is introduced during both the high-frequency pulses and the low-frequency pulses.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Tsai in order to have improved method and structure for the sealing layer in a semiconductor device [0003, Lin]. In doing so, depositing a first etch stop layer (ESL) (112/202 of Lin) over the capping layer(111 of Tsai) using a first plasma-enhanced chemical vapor deposition (PECVD) process[0024 of Lin]; forming an opening(116 of Lin) through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer(111 of Lin);
Tsai and Lin does not disclose after the depositing of the first ESL, depositing a glue layer over the first ESL to interface a top surface of the first ESL; after the depositing of the glue layer, depositing a second ESL over the glue layer using a second PECVD process
JangJian disclose after the depositing of the first ESL(40a), depositing a glue layer(40b) (since 40b is an aluminum nitride layer this may be interpreted as a glue layer)[0025] over the first ESL to interface a top surface of the first ESL; after the depositing of the glue layer, depositing a second ESL(40c)[0030] over the glue layer
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of JangJian to the teachings of Tsai in order to have form interconnect structures, which include metal lines and vias [0002, JangJian]. In doing so, after the depositing of the glue layer, depositing a second ESL(40c) over the glue layer using a second PECVD process [0024 of Lin]
Re claim 9 Tsai, Lin and JangJian disclose the method of claim 8, wherein the first ESL and the second ESL comprise silicon carbonitride[0018].
Re claim 10 Tsai, Lin and JangJian disclose the method of claim 8, wherein a density of the second ESL is greater than a density of the first ESL(since 112/202 may be bombarded with ions from plasma this may be interpreted as wherein a density of the second ESL is greater than a density of the first ESL).
Re claim 11 Tsai, Lin and JangJian disclose the method of claim 8, wherein a dielectric constant of the second ESL is greater than a dielectric constant of the second first ESL.
Re claim 12 Tsai, Lin and JangJian disclose the method of claim 8, wherein the capping layer(111) comprises cobalt or graphene[0012].
Re claim 13 Tsai, Lin and JangJian disclose the method of claim 8, further comprising:before the depositing of the second dielectric layer, depositing a third ESL over the second ESL[0018].
Re claim 14 Tsai, Lin and JangJian disclose the method of claim 13,wherein the third ESL comprises aluminum oxide[0018].
Re claim 15 Tsai, Lin and JangJian disclose the method of claim 8, wherein the capping layer(111) comprises aluminum nitride[0033].
Re claim 16 Tsai, Lin and JangJian disclose the method of claim 15, wherein the selectively depositing the capping layer(111) comprises an atomic layer deposition (ALD) process [0014] that includes use of trimethylaluminum (Al(CH3)3) and ammonia (NH3).
Re claim 21 Tsai discloses a method, comprising: depositing a first conductive feature(110) and a first dielectric layer(114); and forming a second conductive feature(118) in the opening(115) to electrically couple to the first conductive feature(110),
Tsai does not disclose depositing a first etch stop layer (ESL) over a first conductive feature(110) and a first dielectric layer(114); depositing a glue layer over the first ESL to interface a top surface of the first ESL; after the depositing of the glue layer, depositing a second ESL over the glue layer to interface a top surface of the glue layer;
depositing a third ESL over the second ESL; depositing a second dielectric layer over the third ESL; forming an opening(115) through the second dielectric layer, the third ESL, the second ESL, the glue layer, and the first ESL; wherein a dielectric constant of the glue layer is greater than a dielectric constant of the first ESL or a dielectric constant of the second ESL, wherein the third ESL is more etch resistant than the second ESL;
Lin disclose depositing a first etch stop layer (ESL) (112/202 of Lin) over a first conductive feature(106) and a first dielectric layer(104);depositing a glue layer (108/120 of Lin) over the first ESL; depositing a second ESL over the glue layer; wherein a dielectric constant of the glue layer is greater than a dielectric constant of the first ESL or a dielectric constant of the second ESL (since 112/202 may be bombarded with ions from plasma this may be interpreted as wherein a dielectric constant of the glue layer is greater than a dielectric constant of the first ESL or a dielectric constant of the second ESL),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Tsai in order to have improved method and structure for the sealing layer in a semiconductor device [0003, Lin]. In doing so, depositing a third ESL (112 of Tsai) over the second ESL; depositing a second dielectric layer(114 of Lin) over the third ESL; forming an opening(116) through the second dielectric layer, the third ESL, the second ESL, the glue layer, and the first ESL; wherein a dielectric constant of the glue layer is greater than a dielectric constant of the first ESL or a dielectric constant of the second ESL (since 112/202 may be bombarded with ions from plasma this may be interpreted as wherein a dielectric constant of the glue layer is greater than a dielectric constant of the first ESL or a dielectric constant of the second ESL), wherein the third ESL is more etch resistant than the second ESL; wherein the third ESL is more etch resistant than the second ESL.
Tsai and Lin does not disclose depositing a glue layer over the first ESL to interface a top surface of the first ESL; after the depositing of the glue layer, depositing a second ESL over the glue layer to interface a top surface of the glue layer;
JangJian disclose depositing a glue layer over the first ESL(40a) to interface a top surface of the first ESL; after the depositing of the glue layer(40b) (since 40b is an aluminum nitride layer this may be interpreted as a glue layer)[0025], depositing a second ESL(40c)[0030] over the glue layer to interface a top surface of the glue layer;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of JangJian to the teachings of Tsai in order to have form interconnect structures, which include metal lines and vias [0002, JangJian].
Re claim 22 Tsai, Lin and JangJian disclose the method of claim 21 wherein the depositing of the first ESL comprises use of a first plasma-enhanced chemical vapor deposition (PECVD) process[0016,0017 of Lin], wherein the depositing of the second ESL comprises use of a second ESL over the glue layer using a second PECVD process, wherein each of the first PECVD process and second PECVD process comprise high-frequency pulses and low-frequency pulses, wherein, in the first PECVD process, plasma of a nitrogen-containing precursor is introduced during the high-frequency pulses,wherein, in the second PECVD process[0016,0017 of Lin], plasma of the nitrogen-containing precursor[0016,0017 of Lin] is introduced during both the high-frequency pulses and the low-frequency pulses.
Re claim 23 Tsai, Lin and JangJian disclose the method of claim 21, wherein a density of the second ESL is greater than a density of the first ESL(since 112/202 may be bombarded with ions from plasma this may be interpreted as wherein a density of the second ESL is greater than a density of the first ESL).
Re claim 24 Tsai, Lin and JangJian disclose the method of claim 23 wherein the first ESL and the second ESL comprise silicon carbonitride[0018],wherein the third ESL comprises aluminum oxide[0026];
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16, 21-24 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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