DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US 2014/0183599 A1).
Regarding claim 1, Hong teaches a semiconductor structure (device in Figs. 1, 2A-2C of Hong), comprising:
a channel structure (portion of fin F overlapped by gate 151 in Fig. 2B of Hong) on a substrate (100);
a first isolation layer (110) on the substrate and surrounding the channel structure;
a gate structure (151) on the channel structure and the first isolation layer, wherein the gate structure comprises a first portion (widest and bottom portion of the gate 151 at the same level with the protection layer 105 as shown in Fig. 2B) having a first width (width WG2) and a second portion (portion U2) having a second width (width WG1) less than the first width; and
a second isolation layer (protection layer 105) on the first isolation layer and surrounding the first portion of the gate structure (as shown in Fig. 2B of Hong).
Regarding claim 2, Hong teaches all limitations of the semiconductor structure of claim 1, and further comprising a gate dielectric layer (141 in Fig. 2B of Hong) between the gate structure and the second isolation layer.
Regarding claim 3, Hong teaches all limitations of the semiconductor structure of claim 1, and further comprising a source/drain structure (SD in Fig. 1 of Hong) on the channel structure and above the second isolation layer.
Regarding claim 4, Hong teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a top surface (top surface of layer 105 in Fig. 2B of Hong) of the second isolation layer is above the first portion of the gate structure (as shown in Fig. 2B of Hong).
Regarding claim 5, Hong teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a ratio of the first width of the first portion to the second width of the second portion ranges from about 1 to about 2 (as shown in Fig. 2B of Hong).
Regarding claim 7, Hong teaches all limitations of the semiconductor structure of claim 1, and further comprising a gate spacer (131 in Fig. 1 & 2B of Hong) on a top surface of the second isolation layer and sidewall surfaces of the gate structure.
Regarding claim 8, Hong teaches a semiconductor structure (device in Figs. 1, 2A-2C of Hong), comprising:
first and second channel structures (portion of fin F overlapped by gate 151 in Fig. 2B of Hong; there are a plurality of fins, as stated in [0033] of Hong) on a substrate (100);
a first isolation layer (110) on the substrate and between the first and second channel structures;
a gate structure (151) on the first isolation layer and over the first and second channel structures, wherein the gate structure comprises a first portion (widest and bottom portion of the gate 151 at the same level with the protection layer 105 as shown in Fig. 2B) on the first isolation layer and a second portion (portion U2) above the first portion; and
a second isolation layer (protection layer 105) on the first isolation layer and between the first and second channel structures, wherein the first portion of the gate structure is within the second isolation layer (as shown in Fig. 2B of Hong).
Regarding claim 9, Hong teaches all limitations of the semiconductor structure of claim 8, and further comprising a gate dielectric layer (141 in Fig. 1 of Hong) between the gate structure and the second isolation layer.
Regarding claim 10, Hong teaches all limitations of the semiconductor structure of claim 8, and further comprising a first source/drain structure (SD of first fin, as shown in Fig. 1 of Hong) on the first channel structure and a second source/drain structure (SD of second fin, as shown in Fig. 1 of Hong) on the second channel structure, wherein the first and second source/drain structures are above the second isolation layer (as shown in Fig. 1 of Hong).
Regarding claim 11, Hong teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein a top surface of the second isolation layer is above the first portion of the gate structure (as shown in Fig. 2B of Hong).
Regarding claim 12, Hong teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein the first portion of the gate structure has a first width (WG2 in Fig. 2B of Hong) and the second portion of the gate structure has a second width (WG1) less than the first width.
Regarding claim 13, Hong teaches all limitations of the semiconductor structure of claim 12, and also teaches wherein a ratio of the first width to the second width ranges from about 1 to about 2 (as shown in Fig. 2B of Hong, WG2 is slightly larger than WG1 but not twice as large).
Regarding claim 15, Hong teaches all limitations of the semiconductor structure of claim 8, and further comprising a gate spacer (131 in Fig. 1 & 2B of Hong) on a top surface of the second isolation layer and sidewall surfaces of the gate structure.
Regarding claim 16, Hong teaches a method (Figs. 3-16 of Hong), comprising:
forming a channel structure (portion of fin F to be overlapped by gate 151 in Fig. 3 of Hong) on a substrate (100);
forming a first isolation layer (110 in Fig. 3) on the substrate and surrounding the channel structure;
forming a gate structure (gate 151 in Fig. 14) on the channel structure and the first isolation layer, wherein the gate structure comprises a first portion (widest and bottom portion of the gate 151 at the same level with the protection layer 105 as shown in Fig. 14) having a first width (WG2, as shown in Fig. 2B of Hong) and a second portion (portion U2) having a second width (WG1) less than the first width; and
forming a second isolation layer (105 in Fig. 14) on the first isolation layer, wherein the second isolation layer surrounds the first portion of the gate structure (as shown in Fig. 14 of Hong).
Regarding claim 17, Hong teaches all limitations of the method of claim 16, further comprising forming a gate dielectric layer (141 in Fig. 14 of Hong) on the channel structure and the first isolation layer.
Regarding claim 18, Hong teaches all limitations of the method of claim 16, and further comprising forming a source/drain structure (SD in Fig. 1 of Hong) on the channel structure and above the second isolation layer (as shown in Figs. 1 and 2B of Hong).
Regarding claim 20, Hong teaches all limitations of the method of claim 16, and further comprising forming a gate spacer (131 in Fig. 14 of Hong) on a top surface of the second isolation layer and sidewall surfaces of the gate structure.
Claims 1, 6, 8, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Basker et al. (US 2015/0263128 A1).
Regarding claim 1, Basker teaches a semiconductor structure (device in Figs. 11A-B of Basker), comprising:
a channel structure (portion of fin 18 overlapped by gate 56 in Fig. 11B of Basker) on a substrate (10);
a first isolation layer (12) on the substrate and surrounding the channel structure;
a gate structure (56) on the channel structure and the first isolation layer, wherein the gate structure comprises a first portion (wider portion of the gate 56 at the same level with the dielectric layer 32 as shown in Fig. 11B) having a first width (width of the lower and wider portion of gate 56) and a second portion (narrower upper portion of gate 56) having a second width (width of second portion) less than the first width; and
a second isolation layer (32) on the first isolation layer and surrounding the first portion of the gate structure (as shown in Fig. 11B of Basker).
Regarding claim 6, Basker teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a ratio of a height of the first portion of the gate structure to a height of the gate structure ranges from about 5 % to about 20 % (as shown in Figs. 1-6B, the thickness of the first portion of the gate is the same as the thickness of dielectric layer 16L, which is about 5nm to 20nm, as stated in [0036]. On the other hand, the dummy gate layer 22 has thickness of 50nm to 300nm. So ratio of the height of the first portion to that of the gate is about 6% to 9%, within the claimed range).
Regarding claim 8, Basker teaches a semiconductor structure (device in Figs. 11A-B of Basker), comprising:
first and second channel structures (portion of fins F overlapped by gate 56 in Fig. 11B of Basker; there are a plurality of fins, as stated in [0037] of Basker) on a substrate (100);
a first isolation layer (12) on the substrate and between the first and second channel structures;
a gate structure (56) on the first isolation layer and over the first and second channel structures, wherein the gate structure comprises a first portion (wider portion of the gate 56 at the same level with the dielectric layer 32 as shown in Fig. 11B) on the first isolation layer and a second portion (narrower upper portion of gate 56) above the first portion; and
a second isolation layer (32) on the first isolation layer and between the first and second channel structures, wherein the first portion of the gate structure is within the second isolation layer (as shown in Fig. 11B of Basker).
Regarding claim 14, Basker teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein a ratio of a thickness of the second isolation layer to a height of the gate structure ranges from about 5 % to about 20 % (as shown in Figs. 1-6B, the thickness of the first portion of the gate is the same as the thickness of dielectric layer 16L, which is about 5nm to 20nm, as stated in [0036]. On the other hand, the dummy gate layer 22 has thickness of 50nm to 300nm. So ratio of the height of the first portion to that of the gate is about 6% to 9%, within the claimed range).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hong, as applied to claim 1, and further in view of Wang et al. (US 8377779 B1).
Regarding claim 19, Hong teaches all limitations of the method of claim 16, but does not teach wherein forming the second isolation layer comprises depositing a dielectric material on the first isolation layer using a flowable chemical vapor deposition method.
Wang teaches a method of forming a SiN CESL (114) can be deposited using flowable CVD (column 3 lines 35-40 of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the second isolation layer using flowable CVD method, as disclosed by Wang, in order to have a highly conformal layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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