DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 7/28/2026 is acknowledged. Claims 1, 7-8, 16, and 19 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-8, 11-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2015/0340475 A1).
Regarding claim 1, Lin teaches a semiconductor structure (device in Fig. 5, which is made by method in Figs. 4A-4K of Lin), comprising:
a channel structure (112a in Fig. 4B of Lin) on a substrate (110);
a first isolation layer (120 in Fig. 5) on the substrate and surrounding the channel structure;
a gate structure (190) on the channel structure and the first isolation layer, wherein the gate structure comprises a first portion (lower portion 192 in Fig. 5) having a first width (W1) and a second portion (upper portion 194) having a second width (W2) less than the first width; and
a second isolation layer (160) on the first isolation layer and surrounding the first portion of the gate structure, wherein the first portion of the gate structure is directly underneath a portion of the second isolation layer (as shown in Fig. 5, the lower portion 192 of the gate electrode 190 is underneath the insulating layer 160).
Regarding claim 4, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a top surface of the second isolation layer is above the first portion of the gate structure (as shown in Fig. 5 of Lin).
Regarding claim 5, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a ratio of the first width of the first portion to the second width of the second portion ranges from about 1 to about 2 (as shown in Fig. 5, the first portion is larger than the second portion but not twice as large).
Regarding claim 6, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a ratio of a height of the first portion of the gate structure to a height of the gate structure ranges from about 5% to about 20% (as defined in claim 1, the boundary first and second portions is completely arbitrary. Thus, it is defined in such a way that their heights satisfy this requirement).
Regarding claim 7, Lin teaches all limitations of the semiconductor structure of claim 1, and further comprising a gate spacer (140 in Fig. 5 of Lin) on a top surface (as shown in Fig. 5, insulating layer 160 goes underneath the spacer 140. The interface of 160 and 140 is the top surface in the claim) of the second isolation layer and sidewall surfaces of the gate structure and an etch stop layer on the gate spacer and the top surface of the second isolation layer.
Regarding claim 8, Lin teaches a semiconductor structure (device in Fig. 5, which is made by method in Figs. 4A-4K of Lin), comprising:
first and second channel structures (as stated in [0011] of Lin, there are many fins 112 with channel structures 112a. The first and second channel structures are two adjacent channel structures 112a) on a substrate (110);
a first isolation layer (120) on the substrate and between the first and second channel structures;
a gate structure (190) on the first isolation layer and over the first and second channel structures, wherein the gate structure comprises a first portion (lower portion 192 in Fig. 5) on the first isolation layer and a second portion (upper portion 194) above the first portion; and
a second isolation layer (150 and 160) on the first isolation layer and between the first and second channel structures, wherein the first portion (192) of the gate structure comprises a sloped sidewall surface (interface between 192 and the portion 150 of the second isolation layer 150-160, as shown in Fig. 5 of Lin) in contact with the second isolation layer.
Regarding claim 11, Lin teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein a top surface (as shown in Fig. 5, insulating layer 160 goes underneath the spacer 140. The interface of 160 and 140 is the top surface in the claim) of the second isolation layer is above the first portion of the gate structure.
Regarding claim 12, Lin teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein the first portion of the gate structure has a first width (W1 in Fig. 5 of Lin) and the second portion of the gate structure has a second width (W2) less than the first width.
Regarding claim 13, Lin teaches all limitations of the semiconductor structure of claim 12, and also teaches wherein a ratio of the first width to the second width ranges from about 1 to about 2 (as shown in Fig. 5, the first portion is larger than the second portion but not twice as large).
Regarding claim 14, Lin teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein a ratio of a thickness of the second isolation layer to a height of the gate structure ranges from about 5 % to about 20 % (as defined in claim 1, the boundary first and second portions is completely arbitrary. Thus, it is defined in such a way that their heights satisfy this requirement).
Regarding claim 15, Lin teaches all limitations of the semiconductor structure of claim 8, and further comprising a gate spacer (140 in Fig. 5 of Lin) on a top surface of the second isolation layer and sidewall surfaces of the gate structure.
Regarding claim 16, Lin teaches a method (device in Fig. 5, which is made by method in Figs. 4A-4K of Lin), comprising:
forming a channel structure (112a) on a substrate (110);
forming a first isolation layer (120) on the substrate and surrounding the channel structure;
forming a gate structure (190) on the channel structure and the first isolation layer, wherein the gate structure comprises a first portion (192) having a first width (W1) and a second portion (194) having a second width (W2) less than the first width; and
depositing a second isolation layer (150-160) on the first isolation layer and on the first portion of the gate structure, wherein the second isolation layer surrounds the first portion of the gate structure (as shown in Fig. 5 of Lin).
Regarding claim 20, Lin teaches all limitations of the method of claim 16, and further comprising forming a gate spacer (140 in Fig. 5 of Lin) on a top surface of the second isolation layer and sidewall surfaces of the gate structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 9, 10, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above, and further in view of Hong et al. (US 2014/0183599 A1).
Regarding claim 2, Lin teaches all limitations of the semiconductor structure of claim 1, but does not teach further comprising a gate dielectric layer between the gate structure and the second isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B) which includes a gate dielectric layer (141) and a gate electrode (151) above the spacer structure (131).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate dielectric layer as disclosed by Hong, i.e. lining the sidewalls and bottom of the gate electrode, in order to improve the performance of the gate structure.
Regarding claim 3, Lin teaches all limitations of the semiconductor structure of claim 1, but does not teach the semiconductor structure further comprising a source/drain structure on the channel structure and above the second isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B); epitaxial source/drain structures (SD in Fig. 2B) on both sides of the gate structure.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the epitaxial S/D structure as disclosed by Hong in order to improve the performance of the device.
As incorporated, the epitaxial S/D structures would be formed above the insulating layer 160 of Lin.
Regarding claim 9, Lin teaches all limitations of the semiconductor structure of claim 8, but does not teach the semiconductor structure further comprising a gate dielectric layer between the gate structure and the second isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B) which includes a gate dielectric layer (141) and a gate electrode (151) above the spacer structure (131).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate dielectric layer as disclosed by Hong, i.e. lining the sidewalls and bottom of the gate electrode, in order to improve the performance of the gate structure.
Regarding claim 10, Lin teaches all limitations of the semiconductor structure of claim 8, and further comprising a first source/drain structure on the first channel structure and a second source/drain structure (112b-c of each fin 112 of Lin) on the second channel structure, but does not teach that wherein the first and second source/drain structures are above the second isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B); epitaxial source/drain structures (SD in Fig. 2B) on both sides of the gate structure.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the epitaxial S/D structure as disclosed by Hong in order to improve the performance of the device.
As incorporated, the epitaxial S/D structures would be formed above the insulating layer 160 of Lin.
Regarding claim 17, Lin teaches all limitations of the method of claim 16, but does not teach the method further comprising forming a gate dielectric layer on the channel structure and the first isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B) which includes a gate dielectric layer (141) and a gate electrode (151) above the spacer structure (131).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate dielectric layer as disclosed by Hong, i.e. lining the sidewalls and bottom of the gate electrode, in order to improve the performance of the gate structure.
Regarding claim 18, Lin teaches all limitations of the method of claim 16, but does not teach the method further comprising forming a source/drain structure on the channel structure and above the second isolation layer.
Hong teaches a semiconductor structure (Figs. 2A-2C of Hong) comprising: a fin structure (F in Fig. 2A of Hong); a replacement gate structure (141-151 in Fig. 2B); epitaxial source/drain structures (SD in Fig. 2B) on both sides of the gate structure.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the epitaxial S/D structure as disclosed by Hong in order to improve the performance of the device.
As incorporated, the epitaxial S/D structures would be formed above the insulating layer 160 of Lin.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1, and further in view of Wang et al. (US 8377779 B1).
Regarding claim 19, Lin teaches all limitations of the method of claim 16, but does not teach wherein depositing the second isolation layer comprises depositing a dielectric material on the first isolation layer using a flowable chemical vapor deposition method.
Wang teaches a method of forming a SiN CESL (114) can be deposited using flowable CVD (column 3 lines 35-40 of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the second isolation layer using flowable CVD method, as disclosed by Wang, in order to have a highly conformal layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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