Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. [US 9,666,302 B1].
As per claim 19, a method for testing an input/output (I/O) circuit, comprising:
inputting, to a testing circuit [column 1 line 6 DFT], a first input signal or a second input signal [column 1, lines 18, 28 Scan_In (SI), SI inputs], wherein a logic state of one of the first or second input signal is independent of a logic state of the other of the first or second input signal [column 1, lines 26-27 arbitrary test pattern, random 0’s and 1’s]; and
selectively outputting [column 1, lines 18, 32-33 Scan_Out (SO)], from the testing circuit [results of a scan test are then shifted out via chip output pins as SO outputs], a shifted version of a third input signal that is received from a previous scan chain [column 1, lines 13-16, 19-21, 32-33, SE is asserted, results of a scan test are then shifted out via chip output pins as SO outputs, or outputting a captured version of one of the first or second input signal [column 1, lines 31-33 during a “CAPRURE” mode” results of a scan test are then shifted out via chip output pins as SO outputs].
As per claim 20, the method of claim 19, further comprising: selecting, by a multiplexer of the testing circuit, the one of the first or second input signal [column 3, lines 26-35].
Claims 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. [US 9,666,302 B1].
The applied reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As per claim 19, a method for testing an input/output (I/O) circuit, comprising:
inputting, to a testing circuit [column 1 line 6 DFT], a first input signal or a second input signal [column 1, lines 18, 28 Scan_In (SI), SI inputs], wherein a logic state of one of the first or second input signal is independent of a logic state of the other of the first or second input signal [column 1, lines 26-27 arbitrary test pattern, random 0’s and 1’s]; and
selectively outputting [column 1, lines 18, 32-33 Scan_Out (SO)], from the testing circuit [results of a scan test are then shifted out via chip output pins as SO outputs], a shifted version of a third input signal that is received from a previous scan chain [column 1, lines 13-16, 19-21, 32-33, SE is asserted, results of a scan test are then shifted out via chip output pins as SO outputs, or outputting a captured version of one of the first or second input signal [column 1, lines 31-33 during a “CAPRURE” mode” results of a scan test are then shifted out via chip output pins as SO outputs].
As per claim 20, the method of claim 19, further comprising: selecting, by a multiplexer of the testing circuit, the one of the first or second input signal [column 3, lines 26-35].
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lee [US 2005/0091561 A1].
As per claim 19, a method for testing an input/output (I/O) circuit [0002 scan test], comprising:
inputting, to a testing circuit [0069 scan test device], a first input signal or a second input signal [0070], wherein a logic state of one of the first or second input signal is independent of a logic state of the other of the first or second input signal [0070 in response to a select signal S, in response to a scan enable signal SE, 0093]; and
selectively outputting, from the testing circuit [0070-0071 selectively output], a shifted version of a third input signal that is received from a previous scan chain [0076, 0079 shift mode, or outputting a captured version of one of the first or second input signal [0076, 0079 capture mode].
As per claim 20, the method of claim 19, further comprising: selecting, by a multiplexer of the testing circuit, the one of the first or second input signal [0071 for example, a multiplexer, 0094].
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Han [US 7,343,536 B2].
As per claim 19, a method for testing an input/output (I/O) circuit [column 1, lines 9-12], comprising:
inputting, to a testing circuit [column 4, lines 41-42 scan based STPG test circuit], a first input signal or a second input signal [column 4, lines 44, 49-50 scan input pin SCAN_IN, first through fourth scan chains provide first or second signals], wherein a logic state of one of the first or second input signal is independent of a logic state of the other of the first or second input signal [column 9, lines 19, 40 reordering scan chains is logic state independent]; and
selectively outputting [column 4, lines 21-51, column 7, lines 18-20, 41-65, column 8, lines 31-34 selectively outputs based on mode selection signal STD_MODE], from the testing circuit [column 4, lines 46-47 scan output pin SCAN-OUT], a shifted version of a third input signal that is received from a previous scan chain [column 1, lines 52-53 shift operations, column 6, lines 6-7 and column 7, lines 29-31 mode selection signal STD_MODE], or outputting a captured version of one of the first or second input signal [column 1, lines 52-53 capture operation, column 6, lines 6-7 and column 7, lines 29-31 mode selection signal STD_MODE].
As per claim 20, the method of claim 19, further comprising: selecting, by a multiplexer of the testing circuit, the one of the first or second input signal [column 5, lines 31032 a multiplexer, column 6, lines 8-65 first and second multiplexers].
Allowable Subject Matter
Claims 1-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Chang et al. [US 9,666,302] appears to disclose the closest prior art, including vector compression (see, for example, FIGS. 2 and 5, column 5, lines 14-31, column 11, lines 10-55). Han [US 7,343,536 B2] discloses a scan test data compressor comprising XOR circuits (see, for example, FIGS. 4, 6, and 7). However, the prior art of record does not anticipate or render obvious, as per claim 1, a circuit, comprising:
an input/output (I/O) circuit operatively coupled to a functional circuit, and comprising:
a testing circuit comprising:
a plurality of first inputs corresponding to a first I/O of the I/O circuit and configured to receive at least a first input signal or a second input signal;
a multiplexer compressor configured to select one of the first input signal or the second input signal for testing the I/O circuit;
a first output configured to provide a first output signal based on a third input signal, when the testing circuit is configured in a first mode; and
a second output configured to provide a second output signal based on the first or second input signal being selected by the multiplexer compressor, when the testing circuit is configured in a second mode;
wherein regardless of the first input signal or the second input signal being selected, a logic state of the second input signal is independent of a logic state of the first input signal.
And as per claim 12, a circuit, comprising:
a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal;
a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal;
a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and
a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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