DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election, without traverse, of Invention I, directed to a method, cancellation of device Claims 12-20, and addition of new method Claims 21-29, in the Response to Restriction Requirements filed 02/02/26 has been acknowledged. Together with the Response, Applicant amended original Claims 1 and 5.
Since the Applicant did not choose a species for examination, the examiner contacted the applicant’s attorney Mr. Marcus W. Sprow, who said that the applicant was willing to choose Species I-1 (directed to a method of creating a structure shown in Figs. 1-12), and that Claims 1-11 and 21-29 are generic for Species I-1 and I-2. Although Claim 4 may be viewed as being directed to Species I-2 (based on paragraph 0027 of the published application), and Claims 5-11 dependent on Claim 4, the current Office Action, for the reason that will be clear below, examines all pending claims.
Status of Claims
Claims 1-11 and 21-29 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s):
“forming a gate layer in one of a plurality of metallization layers of a semiconductor substrate”, as the amended Claim 1 recites: currently, all gate layers are formed over a semiconductor substrate.
“semiconductor substrate”, cited by Claim 1, and “semiconductor die”, cited by Claim 2: currently, only one of them, such as an element with a number 302, is shown in Fig. 3.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Amended Claim 1 recites: “forming a gate layer in one of a plurality of metallization layers of a semiconductor substrate”, while the original Claim 1 cited: “forming a gate layer in one of a plurality of metallization layers over a semiconductor substrate”. The new recitation of Claim 1 is not supported by the specification, explicitly teaching that a semiconductor substrate is a semiconductor wafer comprised only active regions while all metallization layers are formed over the substrate (see paragraph 0024 of the published application.
The amendment filed 02/02/26 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Amended Claim 1 recites: “forming a gate layer in one of a plurality of metallization layers of a semiconductor substrate”, while the original Claim 1 cited: “forming a gate layer in one of a plurality of metallization layers over a semiconductor substrate”. The new recitation of Claim 1 is not supported by the specification, explicitly teaching that a semiconductor substrate is a semiconductor wafer comprised only active regions while all metallization layers are formed over the substrate (see paragraph 0024 of the published application. Accordingly, this limitation introduces a new matter.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In re Claim 1: Claim 1, as amended 02/02/26, recites: “forming a gate layer in one of a plurality of metallization layers of a semiconductor substrate”, while the original Claim 1 cited: “forming a gate layer in one of a plurality of metallization layers over a semiconductor substrate”. The new recitation of the amended Claim 1 is not supported by the specification, explicitly teaching that a semiconductor substrate is a semiconductor wafer comprised only active regions while all metallization layers are formed over the substrate (see paragraph 0024 of the published application. Accordingly, this limitation introduces a new matter. Appropriate correction is required.
In re Claims 2-11: Claims 2-11 are rejected under 35 U.S.C. 112(a) due to dependency on Claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11 and 21-29 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In re Claim 1: Claim 1, as amended 02/02/26, recites (line 3): “forming a gate layer in one of a plurality of metallization layers of a semiconductor substrate”. However, the original Claim 1, as well as the specification of the application, do(es) not support the cited limitation, and the specification explicitly teaches (paragraph 0024 of the published application) that the semiconductor substrate 302 comprises no metallization layer.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971). Appropriate correction is required to clarify the claimed subject matter.
For this Office Action, the cited limitation of Claim 1 was interpreted as originally filed, e.g.: “forming a gate layer in one of a plurality of metallization layers disposed over a semiconductor substrate”.
In re Claim 1: Lines 5-6 of Claim 1 recites: “defining a plurality of gates from the gate layer; forming a gate oxide layer over the gates”. The second recitation is unclear since it does not clarify what gates are cited with article “the”. Moreover, the recitation is unclear because, in the current application, a gate oxide layer was formed and patterned before the gate layer was divided into a plurality of gates. Appropriate correction is required to clarify the claim language.
For this Office Action, lines 5-6 of Claim 1 were interpreted as: “defining a plurality of gates from the gate layer; forming a gate oxide layer over the defined plurality of gates”.
In re Claim 1: Lines 9-10 of the claim recite: “interconnecting the plurality of gates and the plurality of semiconductor channels to form the first memory cell”. The recitation is not clear, since a memory cell of the current application comprises six transistors (e.g., six channels), as Fig. 12 shows (for convenience, Annotated Fig. 12 is provided below), while gates of access transistors (connected to bit lines BL and BLB) are not connected to any channel and/or to any other gates.
Annotated Fig. 12
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In addition, since Claim 1 associates a transistor (e.g., its semiconductor layer) with its channel, Fig. 12 also clearly shows that not all “channels” are interconnected or are connected to gates – some “channels” are connected to VDD, VSS, BL, or BLB.
Appropriate correction is required to clarify the claim language.
For this Office Action, lines 9-10 of Claim 1 were interpreted as: “interconnecting appropriate gates of the plurality of gates and appropriate semiconductor channels of the plurality of semiconductor channels to form the first memory cell”.
In re Claims 2 and 3: Claims 2 and 3 recite: “a semiconductor die”, while Claims 2 and 3 depend on Claim 1, which recites: “a semiconductor substrate”. The recitations of Claims 2 and 3 are unclear, since the specification of the current application does not teach as separate elements “a semiconductor substrate” and “a semiconductor die”, but equivalents “a semiconductor substrate 302” and “a semiconductor die” in paragraph 0024 of the published application, e.g., the specification, including drawings, does not teach such separate elements as “a semiconductor die” and “a semiconductor substrate”, which makes the above recitation of Claims 2 and 3 – unclear.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971). Appropriate correction is required to clarify the claimed subject matter.
For this Office Action, the cited limitations of Claims 2 and 3 were interpreted in accordance with paragraph 0024 of the published application as: “a semiconductor die comprising the semiconductor substrate”.
In re Claims 4-11: Claims 4-11 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 21: Lines 4-5 of Claim 21 recite: “forming gate isolation trenches in the gate layer to remove a portion of the gate layer between the gate oxide structures”. The recitation is unclear for a few reasons. First, there are no portions of a gate layer between the gate oxide structures – gate oxide structures are formed over the gate layer; accordingly, portions of the gate layer cannot be removed between the gate oxide structures. In addition, as Fig. 5 of the current application clearly shows and as paragraphs 0029-0030 of the published application describe, some portions of the gate layer do not have a gate oxide structures 402 over them, but are covered by an interlayer insulation.
Appropriate correction is required to clarify the claim language.
For this Office Actions, lines 4-5 were interpreted as: “forming gate isolation trenches in the gate layer to create a plurality of gate electrodes”.to
In re Claims 22-26: Claims 22-26 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 21.
In re Claim 27: Lines 5-8 of Claim 27 recite: “forming a vertical channel for transistors of a memory cell over the gate layer, the vertical channel coupled with corresponding source/drain regions; forming first lateral interconnects electrically coupled with the source/drain regions to form a word line of a memory cell”. The recitation is unclear for a few reasons. Initially, the current application does not teach a single vertical channel for a plurality of transistors – it teaches one channel for one transistor. In addition, the current application does not teach a word line coupled to source/drain regions – word lines are coupled with gates (see at least Fig. 12 showing a circuit of the claimed memory cell).
Appropriate correction is required to clarify the claim language.
For this Office Action, lines 5-8 were interpreted as: “forming a plurality of vertical channels, each channel, coupled with respective source/drain regions, is over a respective gate of a transistor belonging to a memory cell; forming first lateral interconnects electrically coupled with corresponding gates of the memory cell to form word lines of the memory cell”.
In re Claim 29: Claim 29 recites: “the first lateral interconnects form a storage node”. The recitation is unclear, since Claim 29 depends on Claim 27, which recites that first lateral interconnects are related to a word line.
Appropriate corrections are required to clarify the claim language.
For this Office Action, based on the citation of Claim 27: “forming second lateral interconnects electrically coupled with the source/drain regions to form a plurality of bit lines” - the cited above recitation of Claim 29 was interpreted as: “the second lateral interconnects form a storage node”.
In re Claim 28: Claim 28 is rejected under 35 U.S.C. 112(b) due to dependency on Claim 27.
Allowable Subject Matter
Claims 1, 21, and 27, as interpreted, contain allowable subject matter.
Reason for Identification of Allowable Subject Matter
Re Claim 1: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 1, as interpreted, as: “forming a gate oxide layer over the defined plurality of gates”, in combination with other limitations of Claim 1, as interpreted.
Re Claim 21: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such combination of limitations of Claim 21, as interpreted as: “forming a gate oxide layer over a gate layer” and: “forming a plurality of semiconductor channels over and extending upwards from the gate oxide structures”, in combination with other limitations of the claim.
Re Claim 27: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 27, as interpreted, as: “forming a plurality of vertical channels, each channel, coupled with respective source/drain regions, is over a respective gate of a transistor belonging to a memory cell”, in combination with all other limitations of Claim 27 (as interpreted).
The prior arts of record include: Chang et al. (US 2020/0343185), Liaw (US 10043571), Liaw (US 10461086), Liaw (US 9236300), Chen et al. (US 2016/0307882), Yang (US 11257824), and Lin et al. (US 11723194).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 02/19/25