DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/23/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-5, 7-14 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a second cap layer covering and in contact with a top surface and a sidewall of the first cap layer and the first adjustment layer” in lines 8-9 (emphasis added).
The terms “a top surface” and “a sidewall” are recited in the singular, but are in reference to surfaces of two separate elements (first cap layer and first adjustment layer). It is unclear if the claim requires the second cap layer to contact a single top surface (a top surface of either the cap layer or the adjustment layer) and a single sidewall (a sidewall of either the cap layer or the adjustment layer), or if the second cap layer contacts two top surfaces (top surfaces of both the cap layer and the adjustment layer) and two sidewalls (sidewalls of both the cap layer and the adjustment layer). This renders the scope of claim 1 indefinite.
Claims 5 and 14 include language equivalent to the indefinite subject matter above.
Claims 3-4, 6-13 and 15-20 depend on claims 1, 5 and 14, and are rejected under 35 USC § 112(b) for implicitly including the indefinite subject matter above.
For the purpose of compact prosecution, the Examiner has interpreted claims 1, 5 and 14 to mean:
“…a second cap layer, covering and in contact with respective top surfaces and respective sidewalls of each of the first cap layer and the adjustment layer.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burke et al. (PG Pub. No. US 2010/0117195 A1).
Regarding claim 1, Burke teaches a semiconductor device (fig. 2F), comprising:
a substrate (¶ 0017: 102);
a bonding structure (¶ 0016: 118, including a bonding surface), located over the substrate (fig. 2F: 118 located over 102);
an adjustment layer (¶ 0018: 110/112), located on a bonding pad of the bonding structure (fig. 2F: 110/112 located on bottom pad-shaped surface of 118);
an interconnection structure (¶ 0016: 104), located between the substrate and the bonding structure (fig. 2F: 104 located between 102 and 118);
a first cap layer (¶ 0018: 108), covering a dielectric layer (¶ 0021: 124) and an entirety of a topmost surface of a topmost conductive layer (¶ 0017: 104a) of the interconnection structure (fig. 2F: 124 covers a portion of top surface of 124 and entirety of top surface of 104a); and
a second cap layer (¶ 0027: 114), covering and in contact with a top surface and a sidewall of the first cap layer and the adjustment layer (fig. 2F: 114 covers and in contact with top and side surfaces of 110/112 and 108).
Regarding claim 3, Burke teaches the semiconductor device according to claim 1, wherein the adjustment layer comprises a conductive layer, a semiconductor layer, an insulating layer or a combination thereof (¶ 0018: in at least one embodiment, adjustment layer portion 110 includes conductive material, and portion 112 comprises insulating dielectric).
Regarding claim 4, Burke teaches the semiconductor device according to claim 1, wherein the bonding pad, the first cap layer, the adjustment layer, the second cap layer and the topmost conductive layer form a passive device (¶ 0018: passive capacitor) or a dummy structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 6-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Burke in view of Chen et al. (PG Pub. No. US 2021/0265313 A1).
Regarding claim 5, Burke teaches a semiconductor device, comprising:
a first die (¶ 0017: 102), comprising a first interconnection structure (¶ 0016: 104);
a bonding structure (¶ 0016: 118, including a bonding surface);
a first adjustment layer (¶ 0018: composite structure including elements 110 and 112), located between a first bonding pad of the bonding structure and a first topmost conductive layer (¶ 0017: 104a) of the first interconnection structure (fig. 2F: 110/112 located between pad portion of 118 and 104a);
a first cap layer (¶ 0018: 108), covering a first dielectric layer (¶ 0021: 124) and an entirety of a topmost surface of the first topmost conductive layer of the first interconnection structure (fig. 2F: 108 covers a portion of 124 and entirety of a top surface of 104a); and
a second cap layer (¶ 0027: 114), covering and in contact with a top surface and a sidewall of the first cap layer and the first adjustment layer (fig. 2F: 114 covers and contacts top and sidewall surfaces of 108 and 110/112).
Burke does not teach the semiconductor device further comprising:
a second die, comprising a second interconnection structure;
the bonding structure, bonding the first die and the second die.
Chen teaches a semiconductor device (¶ 0012 & fig. 10) including:
a first die (¶ 0054: 100, similar to 102 of Burke) comprising a first interconnection structure (¶ 0056: 130, similar to 104 of Burke);
a second die (¶ 0054: 200), comprising a second interconnection structure (¶ 0048: 230), a bonding structure (¶ 0054: 170) bonding the first die and the second die (fig. 1L: 170 bonds 100 and 200).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Burke with the second die of Chen, as a means to increase functionality and/or capacity of memory and/or logic in a single package (Chen, ¶¶ 0055, 0083 among others).
Regarding claim 7, Burke in view of Chen teaches the semiconductor device according to claim 5, wherein the first bonding pad, the first cap layer, the first adjustment layer, the second cap layer and the first topmost conductive layer form a first capacitor (Burke, ¶ 0024-0026: pad-shaped portion of 118, 108, 110/112, 114 and 104a form a capacitor structure), a first resistor or a first dummy structure.
Regarding claim 8, Burke in view of Chen teaches the semiconductor device according to claim 5, comprising a bonding structure (Chen, 170) and a second topmost conductive layer (Chen, ¶ 0030: 232) of a second interconnection structure (fig. 1: 230 includes topmost 232).
Burke in view of Chen as modified above fails to teach the semiconductor device further comprising:
a second adjustment layer, located between a second bonding pad of the bonding structure and a second topmost conductive layer of the second interconnection structure.
However, Chen does teach a second adjustment layer (Chen, ¶ 0031: 246), located between a second bonding pad (Chen, ¶ 0023: 272a) of the bonding structure (Chen, 170/270) and a second topmost conductive layer of a second interconnection structure (Chen, fig. 1L: 246 located between 272a and second conductive pad 232 of 230).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Burke in view of Chen with a second adjustment layer, a second bonding pad, and a second topmost conductive layer, as a means to provide a plurality of passive structures (Chen, ¶ 0029), increasing functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, the second adjustment layer, second bonding pad, and second topmost conductive layer are merely duplication of the essential working parts of Burke and Chen.
Regarding claim 9, Burke in view of Chen teaches the semiconductor device according to claim 8, comprising a second interconnection structure (Chen, e.g. second portion of 270) and a second adjustment layer (Chen, 244).
Burke in view of Chen as applied to claim above does not explicitly teach the semiconductor device further comprising:
a third cap layer, covering a second dielectric layer and a second topmost conductive layer of the second interconnection structure; and
a fourth cap layer, covering the third cap layer and the second adjustment layer.
However, Chen does teach a semiconductor device including:
a third cap layer (¶ 0023: 172a), covering a second dielectric layer (¶¶ 0030, 0033: 234 and/or 274) and a second topmost conductive layer of the second interconnection structure (second 232 of second portion of 230); and
a fourth cap layer (¶ 0031: 242), covering the third cap layer and the second adjustment layer (fig. 1L: 242 covers 172a and 244).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Burke in view of Chen with third and fourth cap layers, as a means to provide a plurality of passive structures (Chen, ¶ 0029), increasing functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, the third and fourth cap layers, second dielectric layer, and second topmost conductive layer are merely duplication of the essential working parts of Burke and Chen.
Regarding claim 10, Burke in view of Chen teaches the semiconductor device according to claim 9, wherein each of the first adjustment layer and the second adjustment layer comprises a conductive layer, a semiconductor layer, an insulating layer or a combination thereof (Burke, ¶ 0018: 110/112 comprises a combination of conductive and insulating layers, as modified with the duplication of Chen).
Regarding claim 11, Burke in view of Chen teaches the semiconductor device according to claim 10, wherein a material the first adjustment layer is the same as a material of the second adjustment layer (Burke, ¶ 0018: 110/112, as modified with the duplication of Chen; at least 110 used in both first and second adjustment layers).
Regarding claim 12, Burke in view of Chen teaches the semiconductor device according to claim 10, wherein a material of the first adjustment layer is different from a material of the second adjustment layer (Burke, ¶ 0018: 110/112, as duplicated by Chen; material of 110 of first adjustment layer different from material of 112 of second adjustment layer).
Regarding claim 13, Burke in view of Chen teaches the semiconductor device according to claim 9, wherein the second bonding pad, the third cap layer, the second adjustment layer, the fourth cap layer and the second topmost conductive layer form a second capacitor (Chen, ¶ 0031: 172a/242/246/244 and related elements form a second capacitor) or, a second resistor or a second dummy structure.
Regarding claim 14, Burke teaches a method of fabricating a semiconductor device, comprising:
forming a first die (¶ 0017: 102), wherein the first die comprises a first interconnection structure (¶ 0016: 104);
forming a first adjustment layer (¶ 0018: composite structure including elements 110 and 112) between a first bonding pad of a bonding structure (¶ 0016: 118, including a bonding surface) and a first topmost conductive layer (¶ 0017: 104a) of the first interconnection structure (fig. 2F: 110/112 located between pad portion of 118 and 104a);
forming a first cap layer (¶ 0018: 108), the first cap layer covering a first dielectric layer (¶ 0021: 124) and an entirety of a topmost surface of the first topmost conductive layer of the first interconnection structure (fig. 2F: 108 covers a portion of 124 and entirety of a top surface of 104a); and
forming a second cap layer (¶ 0027: 114), the second cap layer covering and in contact with a top surface and a sidewall of the first cap layer and the first adjustment layer (fig. 2F: 114 covers and contacts top and sidewall surfaces of 108 and 110/112).
Burke does not teach the method further comprising:
forming a second die, wherein the second die comprises a second interconnection structure; and
bonding the first die and the second die through the bonding structure.
Chen teaches a method of forming a semiconductor device (¶ 0012 & fig. 10) including:
forming a first die (¶ 0054: 100, similar to 102 of Burke) comprising a first interconnection structure (¶ 0056: 130, similar to 104 of Burke);
forming a second die (¶ 0054: 200), comprising a second interconnection structure (¶ 0048: 230); and
bonding the first die and the second die through a bonding structure (¶ 0054, fig. 1L: 100 and 200 bonded through structure 170).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device fabrication method of Burke with the second die and second interconnection structure of Chen, as a means to increase functionality and/or capacity of memory and/or logic in a single package (Chen, ¶¶ 0055, 0083 among others).
Regarding claim 16, Burke in view of Chen teaches the method according to claim 14, wherein the first bonding pad, the first cap layer, the first adjustment layer, the second cap layer and the first topmost conductive layer form a first passive device (Burke, ¶ 0024-0026: pad portion of 118, 108, 110/112, 114 and 104a form a capacitor structure) or a first dummy structure.
Regarding claim 17, Burke in view of Chen teaches the method according to claim 14, comprising a bonding structure (Chen, 170) and a second topmost conductive layer (Chen, ¶ 0030: 232) of a second interconnection structure (fig. 1: 230 includes topmost 232).
Burke in view of Chen as modified above fails to teach the method further comprising:
forming a second adjustment layer, located between a second bonding pad of the bonding structure and a second topmost conductive layer of the second interconnection structure.
However, Chen does teach forming a second adjustment layer (Chen, ¶ 0031: 246), located between a second bonding pad (Chen, ¶ 0023: 272a) of the bonding structure (Chen, 170/270) and a second topmost conductive layer of a second interconnection structure (Chen, fig. 1L: 246 located between 272a and second conductive pad 232 of 230).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Burke in view of Chen with a second adjustment layer, a second bonding pad, and a second topmost conductive layer, as a means to provide a plurality of passive structures (Chen, ¶ 0029), increasing functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, forming the second adjustment layer, second bonding pad, and second topmost conductive layer are merely duplication of the essential working parts of Burke and Chen.
Regarding claim 18, Burke in view of Chen teaches the method according to claim 17, comprising forming a second interconnection structure (Chen, e.g. second portion of 270) and a second adjustment layer (Chen, 244).
Burke in view of Chen as applied to claim above does not explicitly teach the method further comprising:
forming a third cap layer, covering a second dielectric layer and a second topmost conductive layer of the second interconnection structure; and
forming a fourth cap layer, covering the third cap layer and the second adjustment layer.
However, Chen does teach a method including:
forming a third cap layer (¶ 0023: 172a), covering a second dielectric layer (¶¶ 0030, 0033: 234 and/or 274) and a second topmost conductive layer of the second interconnection structure (second 232 of second portion of 230); and
forming a fourth cap layer (¶ 0031: 242), covering the third cap layer and the second adjustment layer (fig. 1L: 242 covers 172a and 244).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Burke in view of Chen with third and fourth cap layers, as a means to provide a plurality of passive structures (Chen, ¶ 0029), increasing functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, forming third and fourth cap layers, second dielectric layer, and second topmost conductive layer are merely duplication of the essential working parts of Burke and Chen.
Regarding claim 19, Burke in view of Chen teaches the method according to claim 17, wherein each of the first adjustment layer and the second adjustment layer comprises a conductive layer, a semiconductor layer, an insulating layer or a combination thereof (Burke, ¶ 0018: 110/112 comprises a combination of conductive and insulating layers, as modified with the duplication of Chen).
Regarding claim 20, Burke in view of Chen teaches the method according to claim 17, wherein the second bonding pad, the third cap layer, the second adjustment layer, the fourth cap layer and the second topmost conductive layer form a second passive device (Chen, ¶ 0031: 172a/242/246/244 and related elements form a second capacitor) or a second dummy structure.
Response to Arguments
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 1, 3-5, 7-14 and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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