Prosecution Insights
Last updated: April 19, 2026
Application No. 18/350,839

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Jul 12, 2023
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
645 granted / 715 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
63 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 715 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of claims 1-10 in the reply filed on 11/17/25 is acknowledged. The traversal is on the ground(s) that that there is no serious burden in examining the listed inventions simultaneously. This is not found persuasive because classification is one avenue where a search may pose a burden. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chan Arguedas (USPGPUB DOCUMENT: 20210020537, hereinafter Chan Arguedas) in view of Huang (USPGPUB DOCUMENT: 2020/0168523, hereinafter Huang). Re claim 1 Chan Arguedas discloses in Fig 3 an electronic package, comprising: an electronic structure(305); a heat conducting layer(350) formed on the electronic structure(305); and a heat dissipation element(325) covering the electronic structure(305), and the heat conducting layer(350), wherein the heat dissipation element(325) has a heat dissipation body(body of 325) bonded to the heat conducting layer(350) and has a plurality of supporting legs(legs of 325) disposed on the heat dissipation body(body of 325) Chan Arguedas does not disclose a carrier structure; a wall structure disposed on the carrier structure; an electronic structure(305) disposed on the carrier structure; a heat dissipation element(325) disposed on the carrier structure, the wall structure, wherein the heat dissipation element(325) has a heat dissipation body(body of 325) bonded the wall structure and bonded to the carrier structure, and the wall structure is located between the supporting legs(legs of 325) and the electronic structure(305). Huang discloses in Fig 4A a carrier structure(24 of Huang); a wall structure(203/43a of Huang) disposed on the carrier structure; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Huang to the teachings of Chan Arguedas in order to avoid the semiconductor chip will likely be damaged and product reliability issues occur [0002, Huang]. In doing so, a heat dissipation element(325) disposed on the carrier structure(24 of Huang), the wall structure(203/43a of Huang), wherein the heat dissipation element(325) has a heat dissipation body(body of 325) bonded the wall structure(203/43a of Huang) and bonded to the carrier structure(24 of Huang), and the wall structure(203/43a of Huang) is located between the supporting legs(legs of 325) and the electronic structure(305). Re claim 2 Chan Arguedas and Huang disclose the electronic package of claim 1, wherein the wall structure(203/43a of Huang) is a frame surrounding the electronic structure(305). Re claim 3 Chan Arguedas and Huang disclose the electronic package of claim 1, wherein the wall structure(203/43a of Huang) is an adhesive structure. Re claim 4 Chan Arguedas and Huang disclose the electronic package of claim 1, wherein the wall structure(203/43a of Huang) is formed with a protruding platform(since 203/43a sticks or juts out this may be interpreted as protruding) on a side corresponding to the electronic structure(305). Re claim 5 Chan Arguedas and Huang disclose the electronic package of claim 4, wherein the protruding platform(since 203/43a sticks or juts out this may be interpreted as protruding) abuts against the electronic structure(305). Re claim 6 Chan Arguedas and Huang disclose the electronic package of claim 4, wherein the protruding platform(since 203/43a sticks or juts out this may be interpreted as protruding) and the heat dissipation body(body of 325) have an air space(S of Huang) formed therebetween. Re claim 7 Chan Arguedas and Huang disclose the electronic package of claim 4, wherein the protruding platform(since 203/43a sticks or juts out this may be interpreted as protruding) is disposed with a porous structure thereon. Re claim 8 Chan Arguedas and Huang disclose the electronic package of claim 1, wherein the electronic structure(305) is of an electronic module specification or an electronic element specification. Re claim 9 Chan Arguedas and Huang disclose the electronic package of claim 1, wherein the heat conducting layer(350) is made of a liquid metal. Re claim 10 Chan Arguedas and Huang disclose the electronic package of claim 1, further comprising a heat dissipation layer formed between the heat conducting layer(350) and the heat dissipation body(body of 325). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 12, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604686
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604749
SEMICONDUCTOR PACKAGE
2y 5m to grant Granted Apr 14, 2026
Patent 12598990
ELECTRICALLY ISOLATED DISCRETE PACKAGE WITH HIGH PERFORMANCE CERAMIC SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
Patent 12598986
METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)
2y 5m to grant Granted Apr 07, 2026
Patent 12593675
RETICLE STITCHING TO ACHIEVE HIGH-CAPACITY INTEGRATED CIRCUIT
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 715 resolved cases by this examiner. Grant probability derived from career allow rate.

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