Attorney’s Docket Number: 252056-2480
Filing Date: 07/12/2023
Claimed Foreign Priority Date: none
Applicant: Lin
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 11/01/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group Invention I, directed to a method of making a semiconductor structure, in the reply filed on 11/01/2025, is acknowledged. Applicant cancelled claims 17-20, added new claims 21-14, and indicated that claims 1-16 and 21-24 read on the elected Group Invention I. The examiner agrees. Accordingly, pending in the application are claims 1-16 and 21-24.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 10, and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mochizuki et al. (US2024/0421191).
Regarding Claim 1, Mochizuki (see, e.g., Figs. 2-9) shows all aspects of the instant invention, including a method for forming a semiconductor device structure (e.g., semiconductor IC device 100), comprising:
- forming a fin structure over a substrate (e.g., nanolayer stack 103 over substrate structure 102), wherein the fin structure has a plurality of sacrificial layers (e.g., sacrificial nanolayers 106) and a plurality of semiconductor layers (e.g., active nanolayers 108) laid out in an alternating manner (see, e.g., Figs. 2-3 and Par. [0052]-[0058])
- partially removing the fin structure to form a recess (e.g., source/drain recess 127) exposing side surfaces of the semiconductor layers and the sacrificial layers (see, e.g., Fig. 4 and Par. [0067]-[0068])
- forming a plurality of inner spacers (e.g., inner spacers 122.1) covering the side surfaces of the sacrificial layers (see, e.g., Figs. 5-6 and Par. [0069]-[0072])
- recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Fig. 7 and Par. [0073]-[0077]: indents 131 are formed by a directional etch of the vertical exposed portions of 108)
- partially removing the inner spacers so that each of the inner spacers becomes thinner (see, e.g., Fig. 8 and Par. [0078]-[0083]: external corner regions 133 of inner spacers 122.1 are recessed resulting in inner spacers 122 having a funneled shape)
- forming an epitaxial structure (e.g., epi S/D region 134) on the side surfaces of the semiconductor layers (see, e.g., Fig. 9 and Par. [0091]-[0093]).
Regarding Claim 2, Mochizuki (see, e.g., Fig. 3) shows steps of:
- forming a dummy gate stack (e.g., sacrificial gate structure 121) wrapped around the fin structure (see, e.g., Par. [0061]: 121 is formed upon and around 103)
- forming gate spacers (e.g., gate spacers 120) over sidewalls of the dummy gate stack before the recess is formed (see, e.g., Par. [0065])
Regarding Claim 10, Mochizuki (see, e.g., Figs. 5-6 and Par. [0069]-[0072]) shows a step of:
- recessing the sacrificial layers (e.g., 106) from the side surfaces of the sacrificial layers before the inner spacers are formed (e.g., indents 129 are first formed by removing respective portions of sacrificial nanolayers 106, then said indent are filled with inner spacer material 122.1)
Regarding Claim 21, Mochizuki (see, e.g., Figs. 2-9) shows all aspects of the instant invention, including a method for forming a semiconductor device structure (e.g., semiconductor IC device 100), comprising:
- forming a plurality of sacrificial layers (e.g., sacrificial nanolayers 106) and a plurality of semiconductor layers (e.g., active nanolayers 108) laid out in an alternating manner (see, e.g., Figs. 2-3 and Par. [0052]-[0058])
- forming a plurality of inner spacers (e.g., inner spacers 122.1) covering the side surfaces of the sacrificial layers (see, e.g., Figs. 5-6 and Par. [0069]-[0072])
- recessing the semiconductor layers from side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Fig. 7 and Par. [0073]-[0077]: indents 131 are formed by a directional etch of the vertical exposed portions of 108)
- trimming the inner spacers after the recessing of the semiconductor layers (see, e.g., Fig. 8 and Par. [0078]-[0083]: external corner regions 133 of inner spacers 122.1 are recessed resulting in inner spacers 122 having a funneled shape)
- forming an epitaxial structure (e.g., epi S/D region 134) on the side surfaces of the semiconductor layers (see, e.g., Fig. 9 and Par. [0091]-[0093])
Claims 1-3, 8-10, and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al. (US2022/0208967).
Regarding Claim 1, Ko (see, e.g., Figs. 1 and 5-14) shows all aspects of the instant invention, including a method for forming a semiconductor device structure (e.g., semiconductor device), comprising:
- forming a fin structure over a substrate (e.g., stacked structure 10 over substrate 100), wherein the fin structure has a plurality of sacrificial layers (e.g., semiconductor layers 11) and a plurality of semiconductor layers (e.g., semiconductor layers 12) laid out in an alternating manner (see, e.g., Fig. 5 and Par. [0079])
- partially removing the fin structure to form a recess (e.g., recess SR1) exposing side surfaces of the semiconductor layers and the sacrificial layers (see, e.g., Fig. 6 and Par. [0083])
- forming a plurality of inner spacers (e.g., inner spacers 131-133) covering the side surfaces of the sacrificial layers (see, e.g., Figs. 7-8 and Par. [0085]-[0086])
- recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Fig. 9 and Par. [0087]-[0088]: recess SR2 is formed by widening SR1 into parts of the sidewalls of 12)
- partially removing the inner spacers so that each of the inner spacers becomes thinner (see, e.g., Figs. 10,14 and Par. [0089],[0097]-[0104]: all inner spacers can have their S/D-facing portion etched to define an L-shape, with widths W2 smaller than W1)
- forming an epitaxial structure (e.g., source/drain region 140) on the side surfaces of the semiconductor layers (see, e.g., Fig. 11 and Par. [0091]).
Regarding Claim 2, Ko (see, e.g., Figs. 1 and 5) shows steps of:
- forming a dummy gate stack (e.g., dummy gate 110D) wrapped around the fin structure (see, e.g., Par. [0081]: 110D is formed on 10)
- forming gate spacers (e.g., gate spacer 112D) over sidewalls of the dummy gate stack before the recess is formed (see, e.g., Par. [0082])
Regarding Claim 3, Ko (see, e.g., Figs. 5, 6, and 10) shows a step of:
- partially removing the gate spacers (e.g., 112D) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0084]: part of 112D sidewalls is etched while SR1 is being formed; Par. [0090]: part of 112D is etched during the etching of inner spacers 131-133).
Regarding Claim 8, Ko (see, e.g., Fig. 6) shows a step of:
- partially removing the gate spacers (e.g., 112D) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0084]: part of 112D sidewalls is etched while SR1 is being formed), wherein the gate spacers are partially removed before the inner spacers are partially removed.
Regarding Claim 9, Ko (see, e.g., Fig. 10) shows a step of:
- partially removing the gate spacers (e.g., 112D) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0090]: part of 112D is etched during the etching of inner spacers 131-133), wherein the gate spacers and the inner spacers are partially removed simultaneously.
Regarding Claim 10, Ko (see, e.g., Fig. 7 and Par. [0085]) shows a step of:
- recessing the sacrificial layers (e.g., 11) from the side surfaces of the sacrificial layers before the inner spacers are formed (e.g., a part of the sidewalls of 11 exposed through SR1 are etched)
Regarding Claim 21, Ko (see, e.g., Figs. 1 and 5-14) shows all aspects of the instant invention, including a method for forming a semiconductor device structure (e.g., semiconductor device), comprising:
- forming a plurality of sacrificial layers (e.g., semiconductor layers 11) and a plurality of semiconductor layers (e.g., semiconductor layers 12) laid out in an alternating manner (see, e.g., Fig. 5 and Par. [0079])
- forming a plurality of inner spacers (e.g., inner spacers 131-133) covering the side surfaces of the sacrificial layers (see, e.g., Figs. 7-8 and Par. [0085]-[0086])
- recessing the semiconductor layers from side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Fig. 9 and Par. [0087]-[0088]: recess SR2 is formed by widening SR1 into parts of the sidewalls of 12)
- trimming the inner spacers after the recessing of the semiconductor layers (see, e.g., Figs. 10,14 and Par. [0089],[0097]-[0104]: all inner spacers can have their S/D-facing portion etched to define an L-shape, with widths W2 smaller than W1)
- forming an epitaxial structure (e.g., source/drain region 140) on the side surfaces of the semiconductor layers (see, e.g., Fig. 11 and Par. [0091])
Regarding Claim 22, Ko (see, e.g., Figs. 1, 5-6, and 10) shows steps of:
- forming a dummy gate stack (e.g., dummy gate 110D) wrapped around the sacrificial layers and the semiconductor layers (see, e.g., Par. [0081]: 110D is formed on 10)
- forming gate spacers (e.g., gate spacer 112D) over sidewalls of the dummy gate stack before the inner spacers are formed (see, e.g., Par. [0082])
- partially removing the gate spacers (e.g., 112D) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0084]: part of 112D sidewalls is etched while SR1 is being formed; Par. [0090]: part of 112D is etched during the etching of inner spacers 131-133).
Regarding Claim 23, Ko (see, e.g., Fig. 6) shows that the gate spacers (e.g., 112D) are partially removed before the inner spacers are trimmed.
Regarding Claim 24, Ko (see, e.g., Fig. 10) shows that the partial removal of the gate spacers (e.g., 112D) and the trimming of the inner spacers are performed simultaneously (see, e.g., Par. [0090]: part of 112D is etched during the etching of inner spacers 131-133).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US2022/0367622) in view of Mochizuki et al. (US2024/0421191).
Regarding Claim 1, Lin (see, e.g., Figs. 2-20) shows most aspects of the instant invention, including a method for manufacturing a semiconductor device (e.g., CMOS GAAFET device), comprising:
- forming a fin structure (e.g., fin stack comprising 62,64,66 in the p-type region 50P) over a substrate (e.g., substrate 50), wherein the fin structure has a plurality of sacrificial layers (e.g., semiconductor layers 54/64) and a plurality of semiconductor layers (e.g., semiconductor layers 56/66) laid out in an alternating manner (see, e.g., Figs. 2-3 and Par. [0022]-[0023],[0026]-[0028])
- partially removing the fin structure to form a recess (e.g., source/drain recess 92 in 50P) exposing side surfaces of the semiconductor layers and the sacrificial layers (see, e.g., Fig. 8A and Par. [0043])
- forming a plurality of inner spacers (e.g., inner spacers 96 in 50P) covering the side surfaces of the sacrificial layers (see, e.g., Fig. 9A and Par. [0044]-[0046])
- recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Figs. 11A, 13 and Par. [0058]: sidewall recesses 92S are formed by recessing portions of 66 sidewalls exposed to 92)
- forming an epitaxial structure (e.g., epitaxial source/drain region 98 in 50P) on the side surfaces of the semiconductor layers (see, e.g., Fig. 11A and Par. [0048]-[0051]).
However, Lin is silent about a step of partially removing the inner spacers so that each of the inner spacers becomes thinner. Mochizuki (see, e.g., Figs. 8-9 and Par. [0107]), on the other hand and in the same field of endeavor, teaches a step of partially removing portions of inner spacers 122.1 so as to define funneled inner spacers 122, to advantageously decrease a parasitic resistance between active nanolayer 108 and later formed S/D region 134.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a step of partially removing the inner spacers so that each of the inner spacers becomes thinner in the method of Lin, as taught by Mochizuki, to advantageously decrease a parasitic resistance between the semiconductor layer and the epitaxial structure.
Regarding Claim 2, Lin (see, e.g., Figs. 6-7) shows steps of:
- forming a dummy gate stack (e.g., dummy gate 84) wrapped around the fin structure (see, e.g., Par. [0038])
- forming gate spacers (e.g., gate spacer 88) over sidewalls of the dummy gate stack before the recess is formed (see, e.g., Par. [0040])
Regarding Claim 3, Lin (see, e.g., Fig. 9A) shows a step of:
- partially removing the gate spacers (e.g., 88) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0046]: the widths of gate spacers 88 are reduced by the etching process used to form 96).
Regarding Claim 4, Lin (see, e.g., Figs. 3-11) shows steps of:
- forming a second fin structure (e.g., fin stack comprising 62,64,66 in the n-type region 50N) over the substrate, wherein the second fin structure has a plurality of second sacrificial layers (e.g., semiconductor layers 54/64) and a plurality of second semiconductor layers (e.g., semiconductor layers 56/66) laid out in an alternating manner, and the dummy gate stack (e.g., 84) is wrapped around the second fin structure (see, e.g., Figs. 6-7)
- partially removing the second fin structure to form a second recess (e.g., source/drain recess 92 in 50N) exposing side surfaces of the second semiconductor layers and the second sacrificial layers (see, e.g., Fig. 8A and Par. [0043])
- forming a plurality of second inner spacers (e.g., inner spacers 96 in 50N) covering the side surfaces of the second sacrificial layers (see, e.g., Fig. 9A and Par. [0044]-[0046])
- forming a second epitaxial structure on the side surfaces of the second semiconductor layers (e.g., epitaxial source/drain region 98 in 50N), wherein the epitaxial structure and the second epitaxial structure have opposite conductivity types (see, e.g., Fig. 11A and Par. [0048]-[0051]: epi 98 in 50N may include any acceptable material appropriate for n-type devices and implanted n-type impurities; epi 98 in 50P may include any acceptable material appropriate for p-type devices, and is implanted with p-type impurities).
Regarding Claim 10, Lin (see, e.g., Figs. 9A and Par. [0045]) shows a step of:
- recessing the sacrificial layers (e.g., 64) from the side surfaces of the sacrificial layers before the inner spacers are formed (e.g., portions of the sidewalls of 64 exposed by 92 are recessed; subsequently inner spacers 96 are formed by conformally forming an etching an insulating material).
Regarding Claim 21, Lin (see, e.g., Figs. 2-20) shows most aspects of the instant invention, including a method for manufacturing a semiconductor device (e.g., CMOS GAAFET device), comprising:
- forming a plurality of sacrificial layers (e.g., semiconductor layers 54/64) and a plurality of semiconductor layers (e.g., semiconductor layers 56/66) laid out in an alternating manner (see, e.g., Figs. 2-3 and Par. [0022]-[0023],[0026]-[0028])
- forming a plurality of inner spacers (e.g., inner spacers 96 in 50P) covering the side surfaces of the sacrificial layers (see, e.g., Fig. 9A and Par. [0044]-[0046])
- recessing the semiconductor layers from side surfaces of the semiconductor layers after the inner spacers are formed (see, e.g., Figs. 11A, 13 and Par. [0058]: sidewall recesses 92S are formed by recessing portions of 66 sidewalls exposed to 92)
- forming an epitaxial structure (e.g., epitaxial source/drain region 98 in 50P) on the side surfaces of the semiconductor layers (see, e.g., Fig. 11A and Par. [0048]-[0051]).
However, Lin is silent about a step of trimming the inner spacers after the recessing of the semiconductor layers. Mochizuki (see, e.g., Figs. 8-9 and Par. [0107]), on the other hand and in the same field of endeavor, teaches a step of partially removing portions of inner spacers 122.1 so as to define funneled inner spacers 122, to advantageously decrease a parasitic resistance between active nanolayer 108 and later formed S/D region 134.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a step of trimming the inner spacers after the recessing of the semiconductor layers in the method of Lin, as taught by Mochizuki, to advantageously decrease a parasitic resistance between the semiconductor layer and the epitaxial structure.
Regarding Claim 22, Lin (see, e.g., Figs. 6-9) shows steps of:
- forming a dummy gate stack (e.g., dummy gate 84) wrapped around the sacrificial layers and the semiconductor layers (see, e.g., Par. [0038])
- forming gate spacers (e.g., gate spacer 88) over sidewalls of the dummy gate stack before the inner spacers are formed (see, e.g., Par. [0040])
- partially removing the gate spacers (e.g., 88) so that portions of the gate spacers become thinner before the epitaxial structure is formed (see, e.g., Par. [0046]: the widths of gate spacers 88 are reduced by the etching process used to form 96).
Allowable Subject Matter
Claims 11-16 are allowable.
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 11, the prior art fails to show or suggest a method for forming a semiconductor device structure, comprising: recessing the semiconductor layers of the second fin structure after the n-type doped epitaxial structures are formed; trimming the inner spacers covering the side surfaces of the sacrificial layers of the second fin structure; and forming p-type doped epitaxial structures on the side surfaces of the semiconductor layers of the second fin structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose methods of forming GAA transistors with inner spacer structures, and comprising a step of recessing channel semiconductor layers after the inner spacers are formed, similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814