DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-2, 6, 8-9, 21-23, and 25 are pending in the application and are currently being examined. No claims have been amended. Claims 11-20 have been cancelled. Claims 3-5, 7, 10, 24, and 26-30 have been withdrawn per the 4/7/2026 restriction election (see below). No new claims have been added.
Election/Restrictions
Claims 3-5, 7, 10, 24, and 26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/7/2026.
However, claims 27-30 read on Species C (Figs. 14-1 through 14-6) and Species D (Figs. 15-1 through 15-6) and do not read on Species A, as it is unknown how the annealing process to drive dopants into the lower gate dielectric shown in Figs. 12-1 to 12-7 would lead to the upper gate dielectric having a higher atomic percentage of the dipole dopant than the lower gate dielectric. Species C depicts an ex-situ process resulting in the upper gate dielectric having a higher atomic percentage of the dipole dopant than the lower gate dielectric. Species D depicts an in-situ process resulting in the upper gate dielectric having a higher atomic percentage of the dipole dopant than the lower gate dielectric. For this reason, claims 27-30 are withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/2/2024 and 8/8/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 6, 8-9, 21-23, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US 2022/0199620 A1, hereafter Thomas).
Regarding claim 1, Fig. 5 of Thomas teaches a method comprising:
forming a first semiconductor channel region (215A, [0066]) and a second semiconductor channel region (215B, [0066]), wherein the second semiconductor channel region (215B) overlaps the first semiconductor channel region (215A);
forming a first gate dielectric (315 in 151, [0042]) on the first semiconductor channel region (215A);
forming a second gate dielectric (315 in 152, [0042]) on the second semiconductor channel region (215B);
incorporating a dipole dopant (an anneal process is done to incorporate a dipole dopant into the high-k dielectric material 315 in step 525, [0067]) into a first one of the first gate dielectric (315 in 151) and the second gate dielectric (315 in 152) to a higher atomic percentage wherein a second one of the first gate dielectric and the second gate dielectric (315 in 152) has a lower atomic percentage of the dipole dopant (as the dipole dopant contained in layer 515, [0066], is diffused only into the high-k dielectric material, 315, in the first semiconductor region, 151, the atomic percentage is inherently higher in the first gate dielectric (315 in 151) compared to the second gate dielectric); and
forming a gate electrode (510A/510B, [0068], or 510 in Fig. 6, [0073], here will only be referenced as 510, see note below) on both of the first gate dielectric (315 in 151) and the second gate dielectric (315 in 152), wherein the gate electrode (510) and the first gate dielectric (315 in 151) form parts of a first transistor (151, [0025]), and the gate electrode (510) and the second gate dielectric (315 in 152) form parts of a second transistor (152, [0025]). While Fig. 5 depicts two separate gate electrodes in the final device, Thomas states that only one gate may be formed in [0038] and as shown in Figs. 1, 6, 7A, and 7C-7F.
Regarding claim 2, Fig. 5 of Thomas teaches the method of claim 1, wherein the incorporating the dipole dopant comprises:
depositing a dipole film (515, [0066]) on the first gate dielectric (315 in 151, [0042]) and the second gate dielectric (315 in 152, [0042]) (depicted in [0066]);
removing the dipole film (515) from the second gate dielectric (315 in 152) (depicted in [0067]);
driving the dipole dopant into the first gate dielectric (315 in 151) (depicted in [0067]); and
removing the dipole film (Fig. 5 describes step 525 as “Anneal & Strip Dipole V-t Shifter(s)” and the next shown step depicts the device without layer 515 indicating the dipole film has been removed).
Regarding claim 6, Fig. 5 of Thomas teaches the method of claim 1, wherein the gate electrode comprises a p-type metal (Thomas states that only one gate may be formed in [0038] and as shown in Figs. 1, 6, 7A, and 7C-7F. The gate electrode 510A [0068] is depicted as a p-type and Thomas further teaches that a single material for a continuous gate electrode may be a p-type [0038]), and wherein the dipole dopant is an n-type dipole dopant (while Fig. 5 depicts 515, [0066], as a p-type dopant, Thomas states in [0028] that an NMOS transistor would utilize an n-type dopant. So if one of ordinary skill in the art needed to make transistor 151 an NMOS transistor, as Thomas states is another embodiment in [0026], the dopant used would be an n-type dopant).
Regarding claim 8, Fig. 5 of Thomas teaches the method of claim 1. While Thomas does not explicitly show in Fig. 5 the first transistor (151, [0025]) is an n-type transistor, and the second transistor (152, [0025]) is a p-type transistor, Thomas discloses in [0026] that the first transistor (151) may be a first conductivity type and the second transistor (152) having the opposite conductivity type. Thus, the first transistor (151) being an n-type transistor, and the second transistor (152) being a p-type transistor is an obvious variant of what is depicted in Fig. 5.
Regarding claim 9, Thomas teaches the method of claim 1. While Thomas does not teach in Fig. 5 the dipole dopant layer 515, [0066], as an n-type dopant (layer 515 contains a p-type dopant), Thomas states in [0028] that an NMOS transistor would utilize an n-type dopant. So if one of ordinary skill in the art needed to make transistor 151 an NMOS transistor, as Thomas states is another embodiment in [0026], the dopant used would be an n-type dopant. Further, in [0044] that a metal M2 is a dipole metal used in the dipole shifter (meaning layer 515). Paragraph [0047] states that M2 may Mg when forming an NMOS transistor. Thus, Thomas teaches the dipole dopant is an n-type dopant selected from the group consisting of La, Sr, Y, Er, Sc, Mg, and combinations thereof.
Regarding claim 21, Thomas teaches a method comprising:
forming a lower transistor (151, [0025]) comprising:
forming a first channel region (215A, [0066]);
forming a first gate dielectric (315 in 151, [0042]) on the first channel region (215A), wherein the forming the first gate dielectric (315 in 151) comprises incorporating a dipole dopant (dopants are diffused into the first gate dielectric after deposition of layer 515, [0066] in step 475 [0057]) into the first gate dielectric (315 in 151) and to a first atomic percentage (as the layers 515 in 151 stay during the annealing step, there is a first atomic percentage of the dopant greater than zero); and
forming a first gate electrode (510A, [0068]) on the first gate dielectric (315 in 151); and
forming an upper transistor (152, [0025]), wherein a first transistor of the lower transistor and the upper transistor is an n-type transistor, and wherein a second transistor of the lower transistor and the upper transistor is a p-type transistor (Thomas states in [0026] that either transistor 151 can be an n-type or p-type transistor and 152 would have the opposite polarity), and wherein the upper transistor (152) comprises:
forming a second channel region (215B, [0066]) overlapping the first channel region (215A);
forming a second gate dielectric (315 in 152, [0042]) on the second channel region (215B), wherein the forming the second gate dielectric (315 in 152) comprises incorporating the dipole dopant (dopants are diffused into the first gate dielectric after deposition of layer 515, [0066] in step 475 [0057]) into the second gate dielectric (315 in 152) and to a second atomic percentage, and wherein the second atomic percentage is different from the first atomic percentage (as the layers 515 is removed before the annealing step in area 152, there is a second atomic percentage that is lower than the first atomic percentage as less dopants are able to diffuse, the second atomic percentage either being zero or near zero); and
forming a second gate electrode (510B, [0068]) on the second gate dielectric (315 in 152), wherein the first gate electrode (510A) and the second gate electrode (510B) are parts of a same continuous gate electrode. While Fig. 5 depicts two separate gate electrodes in the final device, Thomas states that only one gate may be formed in [0038] and as shown in Figs. 1, 6, 7A, and 7C-7F.
Regarding claim 22, Fig. 5 of Thomas teaches the method of claim 21. While Thomas does not explicitly show in Fig. 5 the first transistor (151, [0025]) is an n-type transistor, and the second transistor (152, [0025]) is a p-type transistor, Thomas discloses in [0026] that the first transistor (151) may be a first conductivity type and the second transistor (152) having the opposite conductivity type. Thus, the first transistor (151) being an n-type transistor, and the second transistor (152) being a p-type transistor is an obvious variant of what is depicted in Fig. 5.
Regarding claim 23, Thomas teaches the method of claim 21. While Thomas does not teach in Fig. 5 the dipole dopant layer 515, [0066], as an n-type dopant (layer 515 contains a p-type dopant), Thomas states in [0028] that an NMOS transistor would utilize an n-type dopant. So if one of ordinary skill in the art needed to make transistor 151 an NMOS transistor, as Thomas states is another embodiment in [0026], the dopant used would be an n-type dopant. Further, in [0044] that a metal M2 is a dipole metal used in the dipole shifter (meaning layer 515). Paragraph [0047] states that M2 may Mg when forming an NMOS transistor. Thus, Thomas teaches the dipole dopant is an n-type dopant selected from the group consisting of La, Sr, Y, Er, Sc, Mg, and combinations thereof.
Regarding claim 25, Fig. 5 of Thomas teaches the method of claim 21. While Thomas does not explicitly show in Fig. 5 the first gate dielectric (315 in 152, [0042]) and the second gate dielectric (315 in 152, [0042]) are formed in a same formation process, Thomas does teach in Fig. 4 and in paragraphs [0057-0058] that at step 470, the gate dielectric is deposited on the channel regions. Thus, Thomas teaches that the first gate dielectric (315 in 152) and the second gate dielectric (315 in 152) are formed in a same formation process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chu et al. (US 2021/0366783 A1) teaches a method of selective ex-situ doping in adjacent transistor devices.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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