DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Invention (b) and species II(A)(1) in the reply filed on 19 January 2026 is acknowledged. The restriction and species election requirements are deemed proper and made final.
Response to Amendment
The Office acknowledges receipt on 19 January 2026 of Applicants’ amendments in which claims 1-15 and 19 are cancelled and claims 21-36 are newly added.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 28, lines 2-4, recites “forming an additional field plate overlying a first sidewall of the gate electrode that faces the field plate and laterally offset from a second sidewall of the gate electrode that faces away from the field plate,” which is not illustrated by the drawings. Instead, the drawings (e.g., 49A) illustrates an additional field plate (e.g., 204) neither: (1) overlies a sidewall of a gate electrode (118) or (2) faces a sidewall of the gate electrode (e.g., 118), but instead overlies one sidewall of a gate field plate (202).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 28 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 28, lines 2-4, recites “forming an additional field plate overlying a first sidewall of the gate electrode that faces the field plate and laterally offset from a second sidewall of the gate electrode that faces away from the field plate,” which is new matter because the application (e.g., Fig. 49A) does not disclose an additional field plate (e.g., 204) that: (1) overlies a sidewall of a gate electrode (118) and/or (2) faces a sidewall of the gate electrode (e.g., 118). Instead, the application discloses an additional field plate (e.g., 204) overlies one (and only lateral) sidewall of a gate field plate (202).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 28 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 28, lines 2-7, recites “forming an additional field plate overlying a first sidewall of the gate electrode that faces the field plate and laterally offset from a second sidewall of the gate electrode that faces away from the field plate; and forming an interconnect structure overlying the additional field plate and electrically coupling the additional field plate to an electrode of the pair of source/drain electrodes that is on the same side the gate electrode as the second sidewall,” which is indefinite because the application (e.g., Fig. 49A) does not disclose an additional field plate (e.g., 204) that: (1) overlies a sidewall of a gate electrode (118) and/or (2) faces a sidewall of the gate electrode (e.g., 118). Instead, the application discloses an additional field plate (e.g., 204) overlies one sidewall of a gate field plate (202); and the other sidewall of the gate field plate is integrally formed with a gate electrode (e.g., 118). For the purpose of compact prosecution and to better comport with the specification and drawings, the claim will be interpreted to recite “forming an additional field plate overlying a first sidewall of the gate field plate; and forming an interconnect structure overlying the additional field plate and electrically coupling the additional field plate to an electrode of the pair of source/drain electrodes that is on a side of the gate electrode that is laterally opposite the first sidewall.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US20230019799A1) in view of Guenard (WO2017182739A1), English translation enclosed.
Regarding claim 16, Park teaches in Fig. 1A a method comprising:
forming a channel layer (10) and a barrier layer (20), wherein the channel layer (10) accommodates a two-dimensional carrier gas (2DCG) (2DEG) {[0063]};
forming a cap structure (33) overlying the channel (10) and barrier (20) layers {[0077]};
forming a source electrode (40) and a drain electrode (50) overlying the channel (10) and barrier layers (20), respectively on opposite sides of the cap structure (33) {[0061]};
forming a gate electrode (31) atop the cap structure (33) {[0071]}; and
forming a plurality of field plates (110) laterally between the gate electrode (31) and the drain electrode (50) {Fig. 3/4/5/6/7; [0099]}, wherein
the plurality of field plates (110) are spaced from the gate electrode (31) in a direction (horizontal) and are spaced from each other laterally in a line extending orthogonal to the direction (horizontal) {Fig. 3/4/5/6/7}.
Park does not teach the channel layer and the barrier layer stacked on the substrate.
In an analogous art, Guenard teaches in Figs. 6a and 6b and paragraph [0025] a substrate (not shown); and a channel layer (11) and a barrier layer (12) stacked on the substrate (not shown). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method based on the teachings of Guenard – to include a substrate; with Park’s channel layer and barrier layer stacked on the substrate – so as to provide a reliable foundation for the mechanical support/stability, crystal quality, and/or lattice constant compatibility for the overlying layers of the semiconductor device. See, e.g., Guenard [0025]. Moreover, all the claimed elements (e.g., substrate, channel layer, barrier layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Guenard) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard as applied to claim 16 above, and further in view of More et al. (US20190244864A1) and Abiko et al. (US20230420556A1).
Regarding claim 17, Park as modified by Guenard teaches the method according to claim 16, but Park does not teach further comprising:
depositing a dielectric layer overlying the cap structure;
performing a first etch into the dielectric layer to form an opening exposing the cap structure;
depositing a conductive layer overlying the dielectric layer and filling the opening; and
performing a second etch into the conductive layer to form the gate electrode and the plurality of field plates.
In an analogous art reasonably pertinent to a problem (of electrically connecting a conductive contact with a semiconductor through a cap structure) faced by the inventors, More teaches depositing a dielectric layer (88 and/or 100) overlying a cap structure (84) {Fig. 16B; [0043]}; performing a first etch into the dielectric layer (88 and/or 100) to form an opening (112) exposing the cap structure (84) {Fig. 16B; [0043]}; and depositing a conductive layer (118 or {114 and 118}) overlying the dielectric layer (88 and/or 100) and filling the opening (112) {Fig. 19B; [0051]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard based on the teachings of More – to include depositing a dielectric layer overlying the cap structure; performing a first etch into the dielectric layer to form an opening exposing the cap structure; and depositing a conductive layer overlying the dielectric layer and filling the opening – to electrically connect a conductive contact with a semiconductor through a cap structure through an opening formed in a dielectric material. More [0052].
Park as modified by Guenard and More does not teach performing a second etch into the conductive layer to form the gate electrode and the plurality of field plates.
In an analogous art, Abiko teaches in claim 8 performing an etch into a conductive layer to form a gate electrode and a field plate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard and More based on the teachings of Abiko – to include performing a second etch into the conductive layer to form the gate electrode and a field plate – because the skilled artisan could have applied Abiko’s technique in the same way to the method taught by Park, Guenard, and More and the results (e.g., formation of a gate electrode and a field plate) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Park as modified by Guenard, More, and Abiko does not teach the etch into the conductive layer forms a plurality of field plates.
However, as discussed in the preceding paragraph, Abiko teaches the etch into the conductive layer forms one field plate and the mere duplication of parts [(e.g., field plates)] has no patentable significance unless a new and unexpected result is produced. MPEP 2144.04(VI)(B).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Abiko as applied to claim 17 above, and further in view of Haynie et al. (US20230352580A1).
Regarding claim 18, Park as modified by Guenard, More, and Abiko teaches the method according to claim 17, and Park further teaches wherein the plurality of field plates (110) are between the gate electrode (31) and the drain electrode (50) {Fig. 3/4/5/6/7; [0099]}.
Park does not teach the second etch further forms a gate field plate (GFP) integrated with and protruding from a top of the gate electrode.
In an analogous art, Haynie teaches in Fig. 7 and paragraph [0058] an etch forms a gate field plate (GFP) (132) integrated with and protruding from a top of a gate electrode (130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the teachings of Haynie – to include forming a gate field plate (GFP) integrated with and protruding from a top of the gate electrode – because the skilled artisan could have applied Haynie’s technique in the same way to the method taught by Park, Guenard, More, and Abiko and the results (e.g., formation of an integrated gate electrode and gate field plate) would have been predictable to the skilled artisan. MPEP §2143(I)(C). A consequence of this modification is that Park’s plurality of field plates are disposed between Park’s modified gate field plate (integrated with the gate electrode) and Park’s drain electrode.
Claim(s) 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard as applied to claim 16 above, and further in view of More and Wong (US20200350399A1).
Regarding claim 20, Park as modified by Guenard teaches the method according to claim 16, but Park does not teach further comprising:
depositing a dielectric layer overlying the cap structure; and
selectively implanting oxygen into the channel layer and the barrier layer through the dielectric layer to form an isolation structure surrounding and demarcating an active region individual to a semiconductor device defined by the source and drain electrodes and the gate electrode.
More teaches depositing a dielectric layer (88 and/or 100) overlying a cap structure (84) {Fig. 16B; [0043]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard based on the teachings of More – to include depositing a dielectric layer overlying the cap structure – because the skilled artisan could have applied Mores technique in the same way to the method taught by Park and Guenard and the results (e.g., formation of a dielectric layer on a cap structure) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Park as modified by Guenard and More does not teach selectively implanting oxygen into the channel layer and the barrier layer through the dielectric layer to form an isolation structure surrounding and demarcating an active region individual to a semiconductor device defined by the source and drain electrodes and the gate electrode.
In an analogous art, Wong teaches in Fig. 8H and paragraph [0098] selectively implanting oxygen into a channel layer (104) and a barrier layer (106) through a dielectric layer (152) to form an isolation structure (128) surrounding and demarcating an active region (region of 105 between adjacent portions of 128 in Fig. 8H) individual to a semiconductor device (left semiconductor component/right semiconductor component) defined by source (118) and drain (120) electrodes and a gate electrode (112) {Fig. 1}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard and More based on the teachings of Wong – to include selectively implanting oxygen into the channel layer and the barrier layer through the dielectric layer to form an isolation structure surrounding and demarcating an active region individual to a semiconductor device defined by the source and drain electrodes and the gate electrode – to separate the source contact … and the drain contact … of the left and right [semiconductor] components. Wong [0098].
Regarding claim 21, Park as modified by Guenard, More, and Wong teaches the method according to claim 20, but Park does not teach wherein the dielectric layer is further deposited overlying the source electrode and the drain electrode.
More teaches in Fig. 15B and paragraph [0042] a dielectric layer (88 and/or 100) is deposited overlying a source electrode (e.g., 84 disposed on leftmost 82) and a drain electrode (e.g., 84 disposed on leftmost 82). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Wong based on the further teachings of More – such that the dielectric layer is further deposited overlying the source electrode and the drain electrode – to insulate the underlying materials from undesired electrical signals. Moreover, the skilled artisan could have applied Mores technique in the same way to the method taught by Park, Guenard, More, and Wong and the results (e.g., formation of a dielectric layer overlying a source electrode and a drain electrode) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Wong as applied to claim 20 above, and further in view of Le et al. (US20230369422A1).
Regarding claim 22, Park as modified by Guenard, More, and Wong teaches the method according to claim 20, but Park does not teach wherein a field plate of the plurality of field plates is formed overlying and straddling a sidewall boundary between the isolation structure and the barrier layer.
In an analogous art, Le teaches in Figs. 1 and 2 and paragraph [0007, 0008, 0044] a field plate (6) is formed overlying and straddling a sidewall boundary between an isolation structure (T) and a barrier layer (3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Wong based on the teachings of Le – such that Park’s plurality of field plates comprises a field plate overlying and straddling a sidewall boundary between the isolation structure and the barrier layer – so: (1) the electric field strength [of the field plate] … can be dispersed at the boundary between the isolation area and the channel {Le [0008]}, (2) an electric field peak [of the field plate] … can be reduced {Le [0008]}, and/or (3) the electric field of the field plate may be more uniformly distributed throughout the active region. Moreover, all the claimed elements (e.g., isolation structure, barrier layer, field plate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Le) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard as applied to claim 16 above, and further in view of Yasumoto et al. (US20150076506A1).
Regarding claim 23, Park as modified by Guenard teaches the method according to claim 16, but Park does not teach further comprising:
patterning the barrier layer and the channel layer to form a trench extending in a closed path to surround and demarcate a semiconductor device region individual to a semiconductor device defined by the source and drain electrodes and the gate electrode; and
filling the trench with dielectric material before forming the cap structure.
In an analogous art, Yasumoto teaches in Figs. 1A and 1B and paragraph [0044] patterning a barrier layer (12c) and a channel layer (12b) to form a trench (trench filled by 20) extending in a closed path to surround and demarcate a semiconductor device region (region of 12b and 12c surrounded by 20) individual to a semiconductor device defined by source (14) and drain (16) electrodes and a gate electrode (18); and filling the trench (trench filled by 20) with dielectric material (silicon oxide). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard based on the teachings of Yasumoto – to include patterning the barrier layer and the channel layer to form a trench extending in a closed path to surround and demarcate a semiconductor device region individual to a semiconductor device defined by the source and drain electrodes and the gate electrode; and filling the trench with dielectric material – so as to isolate and insulate the active region from undesired electrical signals and define/demarcate the boundaries of the active region. Yasumoto [0043]. Moreover, all the claimed elements (e.g., barrier layer, channel layer, trench, semiconductor device region, source electrode, drain electrode, gate electrode, and dielectric material) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yasumoto) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by Guenard and Yasumoto do not teach filling the trench with a dielectric material before forming the cap structure. However, the instant application does not identify a new or unexpected result occurring from the recited sequence of operations and the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Claim(s) 24, 25, 29, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Abiko.
Regarding claim 24, Park teaches in Fig. 1A a method, comprising:
forming a channel layer (10) and a barrier layer (20), wherein the channel (10) and barrier layers (20) comprise group III-V semiconductor material (e.g., Al, Ga) {[0062-0064]};
forming a cap structure (33) overlying the channel (10) and barrier layers (20) {[0077]};
forming a gate electrode (31) and a field plate (110) {Fig. 3/4/5/6/7; [0071, 0099]}; and
forming a pair of source/drain electrodes (40, 50) overlying the channel (10) and barrier (20) layers, wherein the gate electrode (31) and the field plate (110) are between the pair of source/drain electrodes (40, 50) after the pair of source/drain electrodes (40, 50), the gate electrode (31), and the field plate (110) are formed {[0061]}.
Park does not teach the channel layer and the barrier layer are stacked on the substrate.
In an analogous art, Guenard teaches in Figs. 6a and 6b and paragraph [0025] a substrate (not shown); and a channel layer (11) and a barrier layer (12) stacked on the substrate (not shown). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method based on the teachings of Guenard – to include a substrate; with Park’s channel layer and barrier layer stacked on the substrate – so as to provide a reliable foundation for the mechanical support/stability, crystal quality, and/or lattice constant compatibility for the overlying layers of the semiconductor device. See, e.g., Guenard [0025]. Moreover, all the claimed elements (e.g., substrate, channel layer, barrier layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Guenard) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by Guenard does not teach:
forming a dielectric layer overlying the cap structure and the channel and barrier layers;
performing a first etch into the dielectric layer to form an opening exposing the cap structure;
depositing a conductive layer overlying the dielectric layer and filling the opening.
More teaches forming a dielectric layer (88 and/or 100) overlying a cap structure (84) and channel (within fins 56; [0026]) and barrier layers (liner with no reference character; [0045]) {Fig. 16,A, 16B; [0043]}; performing a first etch into the dielectric layer (88 and/or 100) to form an opening (112) exposing the cap structure (84) {Fig. 16B; [0043]}; and depositing a conductive layer (118 or {114 and 118}) overlying the dielectric layer (88 and/or 100) and filling the opening (112) {Fig. 19B; [0051]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard based on the teachings of More – to include forming a dielectric layer overlying the cap structure and the channel and barrier layers; performing a first etch into the dielectric layer to form an opening exposing the cap structure; depositing a conductive layer overlying the dielectric layer and filling the opening – to electrically connect a conductive contact with a semiconductor through a cap structure through an opening formed in a dielectric material. More [0052].
Park as modified by Guenard and More does not teach performing a second etch into the conductive layer to concurrently form the gate electrode and the field plate.
Abiko teaches in claim 8 performing an etch into a conductive layer to concurrently form a gate electrode and a field plate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard and More based on the teachings of Abiko – to include performing a second etch into the conductive layer to concurrently form the gate electrode and a field plate – because the skilled artisan could have applied Abiko’s technique in the same way to the method taught by Park, Guenard, and More and the results (e.g., formation of a gate electrode and a field plate) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Regarding claim 25, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, but Park does not teach wherein the gate electrode is formed filling the opening and overlying the dielectric layer.
More teaches a conductive layer (118 or {114 and 118}) is formed filling an opening (112) and overlying a dielectric layer (88 and/or 100 {Fig. 19B; [0051]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the further teachings of More – such that the conductive layer is formed filling the opening and overlying the dielectric layer – to electrically connect a conductive contact with a semiconductor through a cap structure through an opening formed in a dielectric material. More [0052]. A consequence of this modification is that More’s conductive layer is subjected to the second etching operation identified in base claim 24 that transforms the conductive layer into a gate electrode.
Regarding claim 29, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, and Park further teaches a plurality of field plates (110) spaced from each other in a line {Fig. 3/4/5/6/7; [0099]}.
Park does not teach the second etch forms the field plate.
Abiko teaches in claim 8 performing an etch into a conductive layer to form a field plate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the further teachings of Abiko – to include performing a second etch into the conductive layer to form a field plate – because the skilled artisan could have applied Abiko’s technique in the same way to the method taught by Park, Guenard, and More and the results (e.g., formation of a field plate) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Park as modified by Guenard, More, and Abiko does not teach the etch into the conductive layer concurrently forms a plurality of field plates.
However, as discussed in the preceding paragraph, Abiko teaches the etch into the conductive layer forms one field plate and the mere duplication of parts [(e.g., field plates)] has no patentable significance unless a new and unexpected result is produced. MPEP 2144.04(VI)(B). And forming the multiplicity of field plates concurrently saves manufacturing resources (e.g., time, manufacturing operations, materials, etc.).
Regarding claim 30, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, but Park does not teach wherein the pair of source/drain electrodes are formed inset into the dielectric layer before the first etch.
More teaches in Fig. 18B and paragraphs [0042, 0043] that a pair of source/drain electrodes (116) are formed inset into a dielectric layer (88 or 88, 100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the further teachings of More – such that the pair of source/drain electrodes are formed inset into the dielectric layer – to electrically connect a conductive contact with source/drain electrodes through an opening formed in a dielectric material. More [0052]. Moreover, all the claimed elements (e.g., source/drain electrodes, dielectric layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by More) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by More above does not teach the pair of source/drain electrodes are formed before the first etch. However, the instant application does not identify a new or unexpected result occurring from the recited sequence of operations and the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Abiko as applied to claim 24 above, and further in view of Wong.
Regarding claim 26, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, but Park does not teach further comprising: selectively implanting oxygen into the channel layer and the barrier layer through the dielectric layer to form an implant isolation region surrounding the cap structure.
Wong teaches in Fig. 8H and paragraph [0098] selectively implanting oxygen into a channel layer (104) and a barrier layer (106) through a dielectric layer (152) to form an isolation region (128) surrounding a cap structure (108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the teachings of Wong – to include selectively implanting oxygen into the channel layer and the barrier layer through the dielectric layer to form an implant isolation region surrounding the cap structure – to separate the source contact … and the drain contact … of the left and right [semiconductor] components.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Abiko as applied to claim 24 above, and further in view of You et al. (US20210384319A1).
Regarding claim 27, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, but Park does not teach further comprising: depositing an etch stop layer over the dielectric layer, wherein the first etch further extends into the etch stop layer and the conductive layer is deposited overlying the etch stop layer.
In an analogous art, You teaches in Figs. 8 and 13 and paragraphs [0025, 0027], depositing an etch stop layer (photoresist layer within 150) over a dielectric layer (150), wherein an etch extends into the etch stop layer (photoresist layer within 150) and a conductive layer (160) is deposited overlying the etch stop layer (photoresist layer within 150) {photoresist layer must necessarily be disposed in top portion of 150; otherwise, the top portion of 150 would be etched away by subsequent etching operation, which etching away is neither illustrated nor described by You}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the teachings of You – to include depositing an etch stop layer over the dielectric layer, wherein the first etch further extends into the etch stop layer and the conductive layer is deposited overlying the etch stop layer – to form a gate electrode. You [0035]. Moreover, all the claimed elements (e.g., etch stop layer, dielectric layer, conductive layer, protrusion) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by You) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Abiko as applied to claim 24 above, and further in view of Zhu et al. (US20240266406A1).
Regarding claim 28, as interpreted in view of the indefiniteness rejection, Park as modified by Guenard, More, and Abiko teaches the method according to claim 24, but Park does not teach further comprising:
forming an additional field plate overlying a first sidewall of the gate field plate; and
forming an interconnect structure overlying the additional field plate and electrically coupling the additional field plate to an electrode of the pair of source/drain electrodes that is on a side of the gate electrode that is laterally opposite the first sidewall.
In an analogous art, Zhu teaches in Fig. 1 and paragraph [0043], forming an additional field plate (135) overlying a first sidewall of a gate field plate (rightmost portion of 128 overlying 116) and forming an interconnect structure (137, 140) overlying the additional field plate (135) and electrically coupling the additional field plate (135) to an electrode (134) of a pair of source/drain electrodes (134, 136) that is on a side of a gate electrode (portion of 128 not overlying 116) that is laterally opposite the first sidewall. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Abiko based on the teachings of Zhu – to include forming an additional field plate overlying a first sidewall of the gate field plate; and forming an interconnect structure overlying the additional field plate and electrically coupling the additional field plate to an electrode of the pair of source/drain electrodes that is on a side of the gate electrode that is laterally opposite the first sidewall – because all the claimed elements (e.g., field plate, gate electrode, gate field plate, source/drain electrodes, interconnect structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhu) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 31 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Lien et al. (US20240178285A1).
Regarding claim 31, Park teaches in Fig. 1A a method, comprising:
forming a semiconductor heterojunction structure (10, 20) overlying and having a material composition (implicit) {[0004, 0063]; 10 and 20 form a semiconductor heterojunction structure};
forming a cap structure (33) overlying the semiconductor heterojunction structure (10, 20) {[0077]};
forming a source electrode (40) and a drain electrode (50) on opposite sides of the cap structure (33) {[0061]}; and form[ing] a gate electrode (31) overlying the cap structure (33) and a plurality of field plates (110) between the cap structure (33) and the drain electrode (50) {Fig. 3/4/5/6/7; [0070, 0099]}.
Park does not teach a semiconductor heterojunction structure overlying and spaced from a semiconductor substrate and having a material composition different than a material composition of the semiconductor substrate.
Guenard teaches in Figs. 6a and 6b and paragraph [0025] a semiconductor heterojunction structure (11, 12) overlying and spaced from a semiconductor substrate (not shown) and having a material composition (e.g., GaN, AlGaN) different than a material composition of the semiconductor substrate (e.g., sapphire). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method based on the teachings of Guenard – to include a semiconductor heterojunction structure overlying and spaced from a semiconductor substrate and having a material composition different than a material composition of the semiconductor substrate – so as to provide a reliable foundation for the mechanical support/stability, crystal quality, and/or lattice constant compatibility for the overlying layers of the semiconductor device. See, e.g., Guenard [0025]. Moreover, all the claimed elements (e.g., substrate, semiconductor heterojunction structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Guenard) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by Guenard does not teach:
depositing a dielectric layer overlying the cap structure;
the source electrode and drain electrode inset into the dielectric layer;
extending the dielectric layer over the source electrode and the drain electrode;
forming a conductive layer overlying the dielectric layer and the cap structure and having a protrusion extending to the cap structure.
More teaches depositing a dielectric layer (88 and/or 100) overlying a cap structure (116) {Fig. 19B}; a source electrode (leftmost 84) and a drain electrode (rightmost 84) inset into the dielectric layer (88 and/or 100); extending the dielectric layer (88 and/or 100) over the source electrode (leftmost 84) and the drain electrode (rightmost 84); forming a conductive layer (114 and/or 118) overlying the dielectric layer (88 and/or 100) and the cap structure (116) and having a protrusion extending to the cap structure (116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard based on the teachings of More – to include depositing a dielectric layer overlying the cap structure; the source electrode and drain electrode inset into the dielectric layer; extending the dielectric layer over the source electrode and the drain electrode; and forming a conductive layer overlying the dielectric layer and the cap structure and having a protrusion extending to the cap structure – to electrically connect a conductive contact with a semiconductor through a cap structure and through an opening formed in a dielectric material. More [0052].
Park as modified by Guenard and More does not teach patterning the conductive layer to concurrently form a gate electrode overlying the cap structure and a plurality of field plates between the cap structure and the drain electrode.
In an analogous art, Lien teaches in Figs. 1, 8, and 9 and paragraph [0042], patterning a conductive layer (140) to concurrently form a gate electrode (118) overlying a cap structure (109) and a field plate (119) between the cap structure (109) and a drain electrode (114). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard and More based on the teachings of Lien – to include patterning the conductive layer to concurrently form a gate electrode overlying the cap structure and a field plate between the cap structure and the drain electrode – because the skilled artisan could have applied Lien’s technique in the same way to the method taught by Park, Guenard, and More and the results (e.g., formation of a gate electrode and a field plate) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Park as modified by Guenard, More, and Lien does not teach patterning the conductive layer to concurrently form a plurality of field plates.
However, as discussed in the preceding paragraph, Lien teaches patterning the conductive layer to form one field plate and the mere duplication of parts [(e.g., field plates)] has no patentable significance unless a new and unexpected result is produced. MPEP 2144.04(VI)(B). And forming the multiplicity of field plates concurrently saves manufacturing resources (e.g., time, manufacturing operations, materials, etc.).
Regarding claim 35, Park as modified by Guenard, More, and Lien teaches the method according to claim 31, and Park further teaches wherein the cap structure (33) is closer to the source electrode (40) than to the drain electrode (50), and wherein the plurality of field plates (110) are closer to the drain electrode (50) than to the cap structure (33) {Fig. 3}.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Lien as applied to claim 31 above, and further in view of You.
Regarding claim 32, Park as modified by Guenard, More, and Lien teaches the method according to claim 31, but Park does not teach further comprising: depositing an etch stop layer overlying the dielectric layer, wherein the conductive layer is formed overlying the etch stop layer with the protrusion extending through the etch stop layer.
You teaches in Figs. 8 and 13 and paragraphs [0025, 0027], depositing an etch stop layer (photoresist layer within 150) overlying a dielectric layer (150), wherein a conductive layer (160) is formed overlying the etch stop layer (photoresist layer within 150) with a protrusion (portion of 160 extending through 150) extending through the etch stop layer (photoresist layer within 150) {photoresist layer must necessarily be disposed in top portion of 150; otherwise, the top portion of 150 would be etched away by subsequent etching operation, which etching away is neither illustrated nor described by You}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Lien based on the teachings of You – to include depositing an etch stop layer overlying the dielectric layer, wherein the conductive layer is formed overlying the etch stop layer with the protrusion extending through the etch stop layer – to form a gate electrode. You [0035]. Moreover, all the claimed elements (e.g., etch stop layer, dielectric layer, conductive layer, protrusion) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by You) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Lien as applied to claim 31 above, and further in view of Yasumoto.
Regarding claim 33, Park as modified by Guenard, More, and Lien teaches the method according to claim 31, and Park further teaches wherein the source electrode (40), the drain electrode (50), the cap structure (33), the gate electrode (31), and the plurality of field plates (110) are formed on the device region (region illustrated by Fig. 1A) {Figs. 1 and 3/4/5/6/7}.
Park as modified by Guenard, More, and Lien does not teach:
patterning the semiconductor heterojunction structure to form a trench demarcating a device region; and
filling the trench with dielectric material.
Yasumoto teaches in Figs. 1A and 1B and paragraph [0044] patterning a semiconductor heterojunction structure (12b, 12c) to form a trench (trench filled by 20) demarcating a device region (region of 12b and 12c surrounded by 20); and filling the trench (trench filled by 20) with dielectric material (silicon oxide). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Lien based on the teachings of Yasumoto – to include patterning the semiconductor heterojunction structure to form a trench demarcating a device region; and filling the trench with dielectric material – so as to isolate and insulate the device region from undesired electrical signals and define/demarcate the boundaries of the device region. Yasumoto [0043]. Moreover, all the claimed elements (e.g., semiconductor heterojunction structure, patterning, trench, device region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yasumoto) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by Guenard, More, Lien, and Yasumoto does not teach the drain electrode, the cap structure, the gate electrode, and the plurality of field plates are formed on the device region after the filling. However, the instant application does not identify a new or unexpected result occurring from the recited sequence of operations and the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Lien as applied to claim 31 above, and further in view of Le.
Regarding claim 34, Park as modified by Guenard, More, and Lien teaches the method according to claim 31, and Park further teaches further comprising:
a device region (region illustrated by Fig. 1A) on which the source electrode (40), the drain electrode (50), the cap structure (33), the gate electrode (31), and the plurality of field plates (110) are formed {Figs. 1 and 3/4/5/6/7}.
Park does not teach forming an isolation structure extending into the semiconductor heterojunction structure and surrounding and demarcating a device region, wherein a field plate of the plurality of field plates is formed overlying and straddling a sidewall of the isolation structure that contacts the device region.
Le teaches in Figs. 1-4 and paragraph [0007, 0008, 0040, 0044] forming an isolation structure (T) extending into a semiconductor heterojunction structure (2’, 3’) and surrounding and demarcating a device region (A1), wherein a field plate (61/62) of field plates (61, 62) is formed overlying and straddling a sidewall of the isolation structure (T) that contacts the device region (A1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Lien based on the teachings of Le – to include forming an isolation structure extending into the semiconductor heterojunction structure and surrounding and demarcating a device region, wherein a field plate of the plurality of field plates is formed overlying and straddling a sidewall of the isolation structure that contacts the device region – so: (1) the electric field strength [of the field plate] … can be dispersed at the boundary between the isolation area and the channel {Le [0008]}, (2) an electric field peak [of the field plate] … can be reduced {Le [0008]}, and/or (3) the electric field of the field plate may be more uniformly distributed throughout the active region. Moreover, all the claimed elements (e.g., isolation structure, active region, field plate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Le) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Guenard, More, and Lien as applied to claim 31 above, and further in view of Zhu.
Regarding claim 36, Park as modified by Guenard, More, and Lien teaches the method according to claim 31, but Park does not further teach further comprising:
forming a wire and a via overlying the source electrode with the via extending from the wire to the source electrode, wherein the gate electrode has a sidewall facing towards the drain electrode, and wherein the wire has a sidewall facing the same direction as the sidewall of the gate electrode and closer to the drain electrode than the sidewall of the gate electrode when viewed top down.
Zhu teaches in Fig. 1 and paragraph [0043], forming a wire (135) and a via (137) overlying a source electrode (134) with the via (137) extending from the wire (135) to a source electrode (134), wherein a gate electrode (128) has a sidewall facing towards a drain electrode (136), and wherein the wire (135) has a sidewall facing the same direction as the sidewall of the gate electrode (128) and closer to the drain electrode (136) than the sidewall of the gate electrode (128) when viewed top down. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s method as modified by Guenard, More, and Lien based on the teachings of Zhu – to include forming a wire and a via overlying the source electrode with the via extending from the wire to the source electrode, wherein the gate electrode has a sidewall facing towards the drain electrode, and wherein the wire has a sidewall facing the same direction as the sidewall of the gate electrode and closer to the drain electrode than the sidewall of the gate electrode when viewed top down – because all the claimed elements (e.g., wire; via; source, gate, and drain electrodes) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhu) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US20130082277A1) teaches a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891