DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 3/10/2026 is acknowledged.
Applicant amended claims 18 and 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (US 2021/0257261) (hereafter Chu).
Regarding claim 18, Chu discloses a method of forming a semiconductor structure, comprising:
forming a first epitaxial source/drain (S/D) feature 252c (Fig. 25, paragraph 0045) over a first protruding portion 204c (Fig. 25, paragraph 0045) of a substrate 202 (Fig. 25, paragraph 0042);
forming a second epitaxial S/D feature 252d (Fig. 25, paragraph 0045) over a second protruding portion 204d (Fig. 25, paragraph 0045) of the substrate 202 (Fig. 25);
forming a third epitaxial S/D feature 252a (Fig. 25, paragraph 0031) over a third protruding portion 204a (Fig. 25, paragraph 0015) of the substrate 202 (Fig. 25);
forming a fourth epitaxial S/D feature 252b (Fig. 25, paragraph 0031) over a fourth protruding portion 204b (Fig. 25, paragraph 0015) of the substrate 202 (Fig. 25); and
forming an isolation structure (206, 214, and 260 in Fig. 25) over the substrate 202 (Fig. 25), the isolation structure (206, 214, and 260 in Fig. 25) having a base portion 206 (Fig. 25) over a top surface of the substrate 202 (Fig. 25) and sidewall portions (214 and 260 in Fig. 25) over sidewalls of the first 204c (Fig. 25), second 204d (Fig. 25), third 204a (Fig. 25), and fourth protruding portions 204b (Fig. 25) of the substrate 202 (Fig. 25),
wherein the first 252c (Fig. 25) and second epitaxial S/D features 252d (Fig. 25) do not merge,
wherein the third 252a (Fig. 25) and fourth epitaxial S/D features 252b (Fig. 25) merge by laterally breaking through the sidewall portions (214 and 260 in Fig. 25) of the isolation structure (206, 214, and 260 in Fig. 25).
Regarding claim 20, Chu further discloses the method of claim 18, wherein the first 252c (Fig. 25) and second epitaxial S/D features 252d (Fig. 25) are p-type S/D features (see Fig. 25 and paragraph 0015, wherein “p-type FinFETs to form in the region 220b”), and the third 252a (Fig. 25) and fourth epitaxial S/D features 252b (Fig. 25) are n-type S/D features (see Fig. 25 and paragraph 0015, wherein “n-type FinFETs to form in the region 220a”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chu as applied to claim 18 above, and further in view of Ching et al. (US 2017/0207126) (hereafter Ching).
Regarding claim 19, Chu further discloses the method of claim 18, wherein the third 252a (Fig. 25) and fourth epitaxial S/D features 252b (Fig. 25) merge at lower portions of the third 252a (Fig. 25) and fourth epitaxial S/D features 252b (Fig. 25).
Chu does not disclose the lower portions have bottom surfaces below bottom surfaces of the first and second epitaxial S/D features.
Ching disclose the lower portions (portion of 2202 connecting between 306a and 306b in Fig. 22B) have bottom surfaces below bottom surfaces (bottom surfaces of lateral corners of 1008 and 1010 in Fig. 22B) of the first 1008 (Fig. 22B, paragraph 0086) and second epitaxial S/D features 1010 (Fig. 22B, paragraph 0086).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chu to form the lower portions have bottom surfaces below bottom surfaces of the first and second epitaxial S/D features, as taught by Ching, since an epitaxial source/drain feature (Ching, paragraph 0159) of a fin does not excessively protrude out of the fin and merge with epitaxial source/drain features of neighboring fins, thereby avoiding shortening with the neighboring devices and ensuring device density.
Allowable Subject Matter
Claims 1-17 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Chen et al. (US 2020/0118820), discloses performing (see Figs. 3F and 3G) an etching process to the hard mask layer (306a and 306b in Fig. 3F) and the dummy gate layer 304 (Fig. 3F) using the patterned photoresist 308a (Fig. 3E), thereby forming patterned hard mask structures (306a and 306b in Fig. 3G) and patterned dummy gate structures 304 (Fig. 3G); and wherein the protruding portion of each of the patterned hard mask structures (306a and 306b in Fig. 3G) has a first width, wherein each of the patterned dummy gate structures 304 (Fig. 3G) has a second width but fails to disclose the patterned hard mask structures are formed with an uneven profile having a protruding portion, and the first width is greater than the second width. Additionally, the prior art does not teach or suggest a method of forming a semiconductor structure, comprising: the patterned hard mask structures are formed with an uneven profile having a protruding portion, and the first width is greater than the second width in combination with other elements of claim 1.
In addition, a closest prior art, Chen et al. (US 2020/0118820), discloses depositing a hard mask layer (306a and 306b in Fig. 3A, paragraph 0027) over the dummy gate layer 304 (Fig. 3A), the hard mask layer (306a and 306b in Fig. 3A) including a first dielectric film 306a (Fig. 3A, paragraph 0027) and a second dielectric film 306b (Fig. 3A, paragraph 0027) over the first dielectric film 306a (Fig. 3A); performing (see Figs. 3F and 3G) a patterning process to the hard mask layer (306a and 306b in Fig. 3F) and the dummy gate layer 304 (Fig. 3F), wherein the patterning process includes a first etching process having multiple etching steps (13 and 15 in see Figs. 3F and 3G) but fails to disclose one of the etching steps is a cyclic etch process designed to form patterned stacks of the hard mask layer and the dummy gate layer with an uneven profile such that the first dielectric film of each of the patterned stacks spans a first width w1, and the dummy gate layer of each of the patterned stacks span a second width w2 less than the first width; and recessing source/drain regions of the active region by a second etching process impacted by the uneven profile of the patterned stacks. Additionally, the prior art does not teach or suggest a method of forming a semiconductor structure, comprising: one of the etching steps is a cyclic etch process designed to form patterned stacks of the hard mask layer and the dummy gate layer with an uneven profile such that the first dielectric film of each of the patterned stacks spans a first width w1, and the dummy gate layer of each of the patterned stacks span a second width w2 less than the first width; and recessing source/drain regions of the active region by a second etching process impacted by the uneven profile of the patterned stacks in combination with other elements of claim 11.
A closest prior art, Chen et al. (US 2020/0118820), discloses a method of forming a semiconductor structure, comprising: forming an active region (104a and 104b in Fig. 3A, paragraph 0024) over a substrate 102 (Fig. 3A, paragraph 0024); forming a dummy gate layer 304 (Fig. 3A, paragraph 0027) over the active region (104a and 104b in Fig. 3A); forming a hard mask layer (306a and 306b in Fig. 3A, paragraph 0027) over the dummy gate layer 304 (Fig. 3A); forming a patterned photoresist (308a and 308b in Fig. 3B, paragraph 0030) over the hard mask layer (306a and 306b in Fig. 3A); and performing (see Figs. 3F and 3G) an etching process to the hard mask layer (306a and 306b in Fig. 3F) and the dummy gate layer 304 (Fig. 3F) using the patterned photoresist 308a (Fig. 3E), thereby forming patterned hard mask structures (306a and 306b in Fig. 3G) and patterned dummy gate structures 304 (Fig. 3G), wherein the protruding portion of each of the patterned hard mask structures (306a and 306b in Fig. 3G) has a first width, wherein each of the patterned dummy gate structures 304 (Fig. 3G) has a second width but fails to teach the patterned hard mask structures are formed with an uneven profile having a protruding portion, and the first width is greater than the second width as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-10 depend on claim 1.
In addition, a closest prior art, Chen et al. (US 2020/0118820), discloses a method of forming a semiconductor structure, comprising: depositing a dummy gate layer 304 (Fig. 3A, paragraph 0027) over an active region (104a and 104b in Fig. 3A, paragraph 0024) of a semiconductor substrate 102 (Fig. 3A, paragraph 0024); depositing a hard mask layer (306a and 306b in Fig. 3A, paragraph 0027) over the dummy gate layer 304 (Fig. 3A), the hard mask layer (306a and 306b in Fig. 3A) including a first dielectric film 306a (Fig. 3A, paragraph 0027) and a second dielectric film 306b (Fig. 3A, paragraph 0027) over the first dielectric film 306a (Fig. 3A); performing (see Figs. 3F and 3G) a patterning process to the hard mask layer (306a and 306b in Fig. 3F) and the dummy gate layer 304 (Fig. 3F), wherein the patterning process includes a first etching process having multiple etching steps (13 and 15 in see Figs. 3F and 3G) but fails to teach one of the etching steps is a cyclic etch process designed to form patterned stacks of the hard mask layer and the dummy gate layer with an uneven profile such that the first dielectric film of each of the patterned stacks spans a first width w1, and the dummy gate layer of each of the patterned stacks span a second width w2 less than the first width; and recessing source/drain regions of the active region by a second etching process impacted by the uneven profile of the patterned stacks as the context of claim 11. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 12-17 depend on claim 11.
Response to Arguments
1. Applicant's arguments filed 3/10/2026 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 9) that “In rejecting claim 18, the Office Action on page 3 referred to Chu's Fig. 25 (reproduced below) to identify the epitaxial features 252a and 252b as corresponding to the claimed "third and fourth epitaxial S/D features" and the isolation feature 206 and gate spacers 214 as corresponding to the claimed "isolation structure." However, without conceding to the Examiner's mappings, the Office Action is silent about the epitaxial features "merge by laterally breaking through the sidewall portions of the isolation structure" (emphasis added).” However, Chu et al. (US 2021/0257261) disclose the third 252a (Fig. 25) and fourth epitaxial S/D features 252b (Fig. 25) merge by laterally breaking through the sidewall portions (214 and 260 in Fig. 25) of the isolation structure (206, 214, and 260 in Fig. 25).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights