DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: the text “one island-shaped conductive layer” is suggested to be changed to “the island-shaped conductive layer” for clarity. The text “one MRAM cell” is suggested to be changed to “the MRAM cell” for clarity. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: the text “one island portion” is suggested to be changed to “the island portion” for clarity. The text “one MRAM cell” is suggested to be changed to “the MRAM cell” for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oka (US 2018/0033476).
Regarding claim 1, Oka discloses, in FIG. 12 and in related text, a semiconductor structure, comprising:
a circuit layer (308), disposed on a substrate (310);
an island-shaped conductive layer (303), disposed on the circuit layer;
a magnetoresistance random access memory (MRAM) cell (282), disposed between the island-shaped conductive layer and the circuit layer, and electrically connected to the island-shaped conductive layer and the circuit layer;
a bit line (BL2), disposed on the island-shaped conductive layer; and
a conductive via (302), disposed between the bit line and the island-shaped conductive layer,
wherein the island-shaped conductive layer (303) is in contact with a top surface of the MRAM cell (282) (See Oka, [0061], [0097]).
Regarding claim 2, Oka discloses the structure of claim 1.,
Oka discloses wherein a projection area of the island-shaped conductive layer (303) on the substrate (310) is larger than a projection area of the MRAM cell (282) on the substrate (see Oka, FIG. 12).
Regarding claim 3, Oka discloses the structure of claim 1.,
Oka discloses wherein one island-shaped conductive layer (303) is connected to the top surface of one MRAM cell (282) (see Oka, FIG. 12, [0097]).
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 11,238,912).
Regarding claim 1, Wu discloses, in FIG. 7 and in related text, a semiconductor structure, comprising:
a circuit layer (M2), disposed on a substrate (including NFET);
an island-shaped conductive layer (M4), disposed on the circuit layer;
a magnetoresistance random access memory (MRAM) cell (MTJ and vias above and below MTJ), disposed between the island-shaped conductive layer and the circuit layer, and electrically connected to the island-shaped conductive layer and the circuit layer;
a bit line (M5 BL), disposed on the island-shaped conductive layer; and
a conductive via (VIA), disposed between the bit line (M5 BL) and the island-shaped conductive layer (M4),
wherein the island-shaped conductive layer is in contact with a top surface of the MRAM cell (see Wu, column 1, lines 29-36; column 2, line 53 to column 3, line2; column 6, lines 17-31).
Regarding claim 2, Wu discloses the structure of claim 1.
Wu discloses wherein a projection area of the island-shaped conductive layer (M4) on the substrate (including NFET) is larger than a projection area of the MRAM cell (MTJ and vias above and below MTJ) on the substrate (see Wu, FIG. 7).
Regarding claim 3, Wu discloses the structure of claim 1.
Wu discloses wherein one island-shaped conductive layer (M4) is connected to the top surface of one MRAM cell (MTJ and vias above and below MTJ) (see Wu, FIG. 7, column 6, lines 17-31).
Regarding claim 4, Wu discloses the structure of claim 1.
Wu discloses wherein the island-shaped conductive layer (M4) comprises a metal layer (see Wu, column 6, lines 17-31).
Regarding claims 5 and 6, Wu discloses the structure of claim 1.
Wu discloses wherein a semiconductor device (NFET) is disposed on a surface of the substrate, and the circuit layer (M2) is electrically connected to the semiconductor device, wherein the semiconductor device comprises a transistor (see Wu, FIG. 7, column 2, lines 53 to column 3, line 2; column 6, lines 17-31).
Regarding claim 7, Wu discloses the structure of claim 1.
Wu discloses wherein the MRAM cell (MTJ and vias above and below MTJ) comprises a top electrode (via about MTJ), a bottom electrode (via below MTJ) and a magnetic tunnel junction (MTJ) structure (MTJ) disposed between the top electrode and the bottom electrode (see Wu, FIG. 7, column 2, lines 29-36; column 6, lines 17-31).
Claims 8 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 2012/0032287).
Regarding claim 8, Li discloses, in FIG. 3 and in related text, a semiconductor structure, comprising:
a substrate, having a memory region and a peripheral region;
a circuit layer, disposed on the substrate, and comprising a memory circuit portion (Mx-1) located in the memory region and a peripheral circuit portion (M’x-1) located in the peripheral region that are separated from each other;
a first conductive layer, disposed on the circuit layer, and comprising an island portion (Mx) located in the memory region and a first circuit portion (M’x) located in the peripheral region that are separated from each other;
a MRAM cell (BE, MTJ, TE), disposed between the island portion and the memory circuit portion, and electrically connected to the island portion and the memory circuit portion;
a first conductive via (V’x), disposed between said first circuit portion and the peripheral circuit portion;
a second conductive layer, disposed on the first conductive layer, and comprising a bit line portion (Mx+1) located in the memory region and a second circuit portion (M’x+1) located in the peripheral region that are separated from each other;
a second conductive via (Vx+1), disposed between the bit line portion and the island portion; and
a third conductive via (V’x+1), disposed between the first circuit portion and the second circuit portion,
wherein the island portion is in contact with a top surface of the MRAM cell (see Li, [0015], [0030]-[0032], [0043]).
Regarding claim 18, Li discloses the structure of claim 8.
Li discloses wherein the MRAM cell (BE, MTJ, TE) comprises a top electrode, a bottom electrode and a MTJ structure disposed between the top electrode and the bottom electrode (see Li, FIG. 3, [0015], [0030]-[0032]).
Claims 8-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tan (US 2017/0092693).
Regarding claim 8, Tan discloses, in FIG. 1a and in related text, a semiconductor structure, comprising:
a substrate (105), having a memory region (110a) and a peripheral region (110b);
a circuit layer, disposed on the substrate, and comprising a memory circuit portion (135 in 110a) located in the memory region and a peripheral circuit portion (135 in 110b) located in the peripheral region that are separated from each other;
a first conductive layer, disposed on the circuit layer, and comprising an island portion (166) located in the memory region and a first circuit portion (175) located in the peripheral region that are separated from each other;
a MRAM cell (164), disposed between the island portion and the memory circuit portion, and electrically connected to the island portion and the memory circuit portion;
a first conductive via (174), disposed between said first circuit portion (175) and the peripheral circuit portion (135 in 110b);
a second conductive layer, disposed on the first conductive layer, and comprising a bit line portion (185 in 110a) located in the memory region and a second circuit portion (185 in 110b) located in the peripheral region that are separated from each other;
a second conductive via (184 in 110a), disposed between the bit line portion (185 in 110a) and the island portion (166); and
a third conductive via (184 in 110b), disposed between the first circuit portion (175) and the second circuit portion (185 in 110b),
wherein the island portion (166) is in contact with a top surface of the MRAM cell (164) (see Tan, [0014]-[0015], [0032], [0035], [0041]-[0042], [0052]).
Regarding claim 9, Tan discloses the structure of claim 8,
Tan discloses wherein a projection area of the island portion (166) on the substrate (105) is larger than a projection area of the MRAM cell (164) on the substrate (see Tan, FIG. 1a).
Regarding claim 10, Tan discloses the structure of claim 8,
Tan discloses wherein one island portion (166) is connected to the top surface of one MRAM cell (164) (see Tan, FIG. 1a).
Regarding claims 11 and 12, Tan discloses the structure of claim 8,
Tan discloses wherein the island portion (166) and the first circuit portion (175) are located at the same level, wherein a top surface of the island portion is coplanar with a top surface of the first circuit portion (see Tan, FIGS. 1a and 3e-3f, [0079]-[0081]).
Regarding claims 13 and 14, Tan discloses the structure of claim 8,
Tan discloses wherein the bit line portion (185 in 110a) and the second circuit portion (185 in 110b) are located at the same level, wherein a top surface of the bit line portion is coplanar with a top surface of the second circuit portion (see Tan, FIGS. 1a and 3g, [0084]-[0086]).
Regarding claim 15, Tan discloses the structure of claim 8,
Tan discloses wherein a height of the second conductive via (184 in 110a) is the same as a height of the third conductive via (184 in 110b) (see Tan, FIGS. 1a and 3g, [0084]).
Regarding claims 16 and 17, Tan discloses the structure of claim 8,
Tan discloses wherein a semiconductor device is disposed on a surface of the substrate (105), and the circuit layer (135) is electrically connected to the semiconductor device, wherein the semiconductor device comprising a transistor (see Tan, FIG. 1a, [0019], [0030]-[0031]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811