Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-7 and 15-27 are pending in this application.
Applicant elected without traverse of Group I (claims 1-7, 15-20, and new claims 21-27) in the reply filed on November 12, 2025.
All nonelected claims were cancelled in the amendment dated November 12, 2025.
The Examiner notes claims 1-7 and 15-27 are examined.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed November 12, 2025. Claims 1, 3, 15, 21, and 23 are amended. The Examiner notes that claims 1-7 and 15-27 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 19, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 2 recites:
“a silicon nitride layer disposed between the sidewall of the first semiconductor die and the sidewall of the first polymer buffer, wherein the silicon nitride layer has a fourth top surface planar with both the first top surface and the third top surface.” Claim 2 depends on claim 1, which recites:
“a silicon nitride layer having a first sidewall contacting the sidewall of the first insulating material on a first side of the first semiconductor die, the silicon nitride layer further having a second sidewall contacting a sidewall of the first polymer buffer on the first side of the first semiconductor die, wherein the silicon nitride layer has a fourth top surface planar with both the second top surface and the third top surface.”
The Examiner understands the description of the silicon nitride layer in claim 1 to direct to the embodiments of Figs. 1-12 and the description of the silicon nitride layer of claim 2 to direct to the embodiments of Figs. 13-23. The Examiner does not understand the written description to enable an embodiment with the combined limitations indicated above.
Claim 19 recites:
“further comprising a silicon nitride layer disposed between the first polymer buffer and the first insulating layer, wherein the silicon nitride layer encircles the first semiconductor die.”
Claim 15 upon which claim 19 depends recites:
“a first barrier layer encircling the first polymer buffer”
The Examiner understands both the “first barrier layer” and the “silicon nitride layer” to refer to element 401. The Examiner does not understand an embodiment that includes a barrier layer and an additional silicon nitride layer.
Claim 20 recites:
“further comprising a silicon nitride layer disposed between the first semiconductor die and the first polymer buffer, wherein the silicon nitride layer encircles the first semiconductor die.”
Claim 15 upon which claim 19 depends recites:
“a first barrier layer encircling the first polymer buffer”
The Examiner understands both the “first barrier layer” and the “silicon nitride layer” to refer to element 401. The Examiner does not understand an embodiment that includes a barrier layer and an additional silicon nitride layer. The Examiner understands the description of the barrier layer in claim 1 to direct to the embodiments of Figs. 1-12 and the description of the silicon nitride layer of claim 20 to direct to the embodiments of Figs. 13-23. The Examiner does not understand the written description to enable an embodiment with the combined limitations indicated above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 2, both claim 2 and claim 1 upon which claim 2 depends recite “a silicon nitride layer.” It is unclear if both recitations refer to the same silicon nitride layer or different silicon nitride layers.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the silicon nitride layer having the configurations described in both claim 2 and claim 1 upon which it depends, and the silicon nitride layers described in claims 19 and 20 in combination with the barrier layer described in claim 15 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 15-19, and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2017/0038214 A1).
With respect to claim 1, Uzoh teaches in Fig. 6E:
A semiconductor device comprising:
a first semiconductor die (die 3a);
a dielectric layer (BEOL dielectric layer that makes up the routing layer 34, see para. 19) on the first semiconductor die (on bottom of 3a), wherein the first semiconductor die has a first top surface (top surface) opposite the dielectric layer;
a first insulating material (third filler layer 45) encapsulating the first semiconductor die and the oxide layer,
wherein the first insulating material has a second top surface planar with the first top surface (see Fig. 6E, top surface of 3a and 45 are coplanar); and
a first polymer buffer (first filler layer 12, para. 33 “the first layer 12 may comprise a polyimide or polyimide-amide”) disposed between a sidewall of the first semiconductor die (3a) and a sidewall of the first insulating material (45),
wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface (see Fig. 6E, top surface of 12 is coplanar with top surfaces of 3a and 45); and
a silicon nitride layer (second layer 15, which may be silicon nitride, see para. 52) having a first sidewall contacting the sidewall of the first insulating material (45) on a first side of the first semiconductor die (see annotated Fig. 6E below),
the silicon nitride layer further having a second sidewall contacting a sidewall of the first polymer buffer on the first side of the first semiconductor die (see annotated Fig. 6E below),
wherein the silicon nitride layer has a fourth top surface planar with both the second top surface and the third top surface (top surface of 15 is coplanar with top surfaces of 3a, 45, and 12).
Uzoh fails to teach:
an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer;
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a dielectric oxide such as silicon oxide for the dielectric portion of the BEOL dielectric layer 34, since the Examiner takes Official Notice that silicon oxide is a commonly used dielectric material known for its use in the semiconductor packaging art and the selection of an oxide as the dielectric material would be within the level of ordinary skill in the art. See MPEP 2144.
With respect to claim 3, Uzoh further teaches:
and further wherein the bottommost surface of the first insulating material (45) is vertically displaced from the respective bottommost surfaces of the first polymer buffer (12) and the silicon nitride layer (15) (see Fig. 6E, bottommost surfaces are at different heights)
Uzoh does not teach:
wherein respective bottommost surfaces of the first polymer buffer and the silicon nitride layer are coplanar,
Uzoh differs from the invention as claimed because the polymer buffer of Uzoh is conformally deposited in the gap between the semiconductor dies and includes a bottom surface below second filler layer 15. The purpose of layer 12 is described in para. 43 of Uzoh: “The first layer 12 of protective material thus protects the edges of the die from chipping during the die thinning process.” The Examiner takes the position that the difference in shape between the polymer layer 12 of Uzoh and the polymer buffer layer as claimed is a design choice due to choice of method for depositing the layer that does not change the function of the layer because if the bottom portion of layer 12 were removed from the device of Uzoh the sidewalls of the dies would still be covered and protected from chipping. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 4, Uzoh further teaches:
wherein the first polymer buffer has a first width, the first width being in a range of 1 microns to 30 microns (para. 29, the thickness of the applied first layer 12 may be in a range of 5 microns to 15 microns, which is within the claimed range).
With respect to claim 5, Uzoh further teaches:
wherein the first polymer buffer comprises a polyimide (para. 33 “the first layer 12 may comprise a polyimide or polyimide-amide”) having a first toughness,
and wherein the first insulating material comprises an oxide (para. 66 “For example, the third layer 45 can comprise any suitable material described above for the first layer 12 or the second layer 15”, para. 33 “the first layer 12 can comprise silicon, inorganic oxide, inorganic nitride, inorganic carbide, or carbonate, for example, silicon oxide,”) having a second toughness less than the first toughness (toughness is an inherent property of the claimed materials materials).
With respect to claim 15, Uzoh teaches:
A semiconductor device (structure 1) comprising:
a first semiconductor die (die 3a);
a first polymer buffer (first filler layer 12, para. 33 “the first layer 12 may comprise a polyimide or polyimide-amide”) encircling the first semiconductor die (3a);
and a first barrier layer (second layer 15) encircling the first polymer buffer (12);
and a first insulating layer (third layer 45) encircling the first barrier layer (15),
wherein the first polymer buffer extends along a sidewall of the first semiconductor die from a level of a first planar top surface of the first semiconductor die to a level of a bottom surface of the first semiconductor die (see Fig. 6E),
Uzoh does not teach:
and further wherein the first polymer buffer and the first barrier layer have respective bottom surfaces that are coplanar with the bottom surface of the first semiconductor die.
Uzoh differs from the invention as claimed because the polymer buffer of Uzoh is conformally deposited in the gap between the semiconductor dies and includes a bottom surface below second filler layer 15. The purpose of layer 12 is described in para. 43 of Uzoh: “The first layer 12 of protective material thus protects the edges of the die from chipping during the die thinning process.” The Examiner takes the position that the difference in shape between the polymer layer 12 of Uzoh and the polymer buffer layer as claimed is a design choice due to choice of method for depositing the layer that does not change the function of the layer because if the bottom portion of layer 12 were removed from the device of Uzoh the sidewalls of the dies would still be covered and protected from chipping. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 16, Uzoh teaches that the embodiment of Fig. 6E can be combined with the structures of Figs. 1-5 (para. 68). Adding a second layer of the structure of 6E similar to the stack of semiconductor dies shown in Fig. 4 teaches:
a second semiconductor die (die 4a) bonded to the first semiconductor die (3a);
a second polymer buffer (12 around 4a) encircling the second semiconductor die;
and a second insulating layer (45 in second layer) encircling the second polymer buffer (12 in second layer), wherein the second insulating layer (45), the second polymer buffer (12), and the second semiconductor die (4a) share a second planar top surface, the second planar top surface being parallel to the first planar top surface (see Fig. 6E).
With respect to claim 17, Uzoh does not specify if the polyimide used is photosensitive. However, the Examiner takes Official Notice that photosensitive polyimides are a well-known material in the art of semiconductor packaging and that photosensitive properties are useful in polyimides because photosensitive polyimides can be easily patterned using light. In the event that the polyimides of Uzoh are not photosensitive, it would be obvious to modify the polymer to be photosensitive for the purpose of more easily patterning the polymer layers during the manufacturing process, meeting the limitation:
wherein the first polymer buffer comprises a photosensitive polyimide.
With respect to claim 18, Uzoh further does not specify the brittleness of the buffer layer or insulating layer and is silent to:
wherein the first polymer buffer is less brittle than the first insulating layer.
However, it would be obvious to choose a polyimide with a brittleness lower than the insulating material because the purpose of a protective layer is to prevent damage when stress is applied and brittleness is a material property that measures how readily a material fractures from stress. Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose a polyimide with a lower brittleness than the insulating layers, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 19, Uzoh further teaches:
further comprising a silicon nitride layer (15) disposed between the first polymer buffer and the first insulating layer (45), wherein the silicon nitride layer encircles the first semiconductor die (3a).
With respect to claim 21, Uzoh teaches in Fig. 6E:
A semiconductor device comprising:
a first semiconductor die (semiconductor die 3a) and a second semiconductor die (semiconductor die 3b) on a common plane with the first semiconductor die (3a), the second semiconductor die being laterally displaced from the first semiconductor die by a gap (gap that includes second layer 15, liner 12, and third filler layer 45, with portions of layers labeled 48 and 13 in Fig. 6E);
and a first gap-fill structure (liner layer 12) between the first semiconductor die and the second semiconductor die,
the first gap-fill structure including a polymer (the first layer 12 may comprise a polyimide or polyimide-amide) extending along respective sidewalls of the first semiconductor die (3a) and the second semiconductor die (3b),
a barrier layer (second layer 15) having a first portion lining a first inner sidewall of the polymer (left side of portion of 15 on the sidewall opposite die 3a),
and having a second portion lining a second inner sidewall of the polymer (see annotated Fig. 6E below),
and a gap fill material (portion 48 of third filler layer 45) extending from the first portion of the barrier layer to the second portion of the barrier layer,
wherein respective top surfaces of the first semiconductor die, the second semiconductor die, the polymer, the barrier layer, and the gap fill material are coplanar (see Fig. 6E).
Uzoh does not teach:
and wherein respective bottom surfaces of the first semiconductor die, the second semiconductor die, the polymer, and the barrier layer are coplanar.
Uzoh differs from the invention as claimed because the polymer buffer of Uzoh is conformally deposited in the gap between the semiconductor dies and includes a bottom surface below second filler layer 15. The purpose of layer 12 is described in para. 43 of Uzoh: “The first layer 12 of protective material thus protects the edges of the die from chipping during the die thinning process.” The Examiner takes the position that the difference in shape between the polymer layer 12 of Uzoh and the polymer buffer layer as claimed is a design choice due to choice of method for depositing the layer that does not change the function of the layer because if the bottom portion of layer 12 were removed from the device of Uzoh the sidewalls of the dies would still be covered and protected from chipping. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
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With respect to claim 22, Uzoh further teaches:
wherein the barrier layer (15) comprises silicon nitride (para. 53 “ the second layer 15 can comprise silicon, inorganic oxide, inorganic nitride, inorganic carbide, or carbonate, for example, silicon oxide, silicon nitride, silicon carbide”)
With respect to claim 23, Uzoh further teaches:
wherein the gap fill material (45) has greater stiffness than the polymer (12).
Uzoh teaches in Fig. 34 that the first layer 12 which may be made from a polymer may have its stiffness increased by filler particles of oxide or nitride. Uzoh teaches that the gap fill material (45) may be made of silicon oxide or silicon nitride. Therefore, the gap fill material is implicitly stiffer than the polymer as it may be made of the material that may be added to the polymer to increase the stiffness.
With respect to claim 24 Uzoh further teaches:
wherein the gap fill material (45) comprises silicon oxide (para. 67 “For example, the third layer 45 can comprise any suitable material described above for the first layer 12 or the second layer 15.” Para. 53 “the second layer 15 can comprise silicon, inorganic oxide, inorganic nitride, inorganic carbide, or carbonate, for example, silicon oxide, silicon nitride, silicon carbide”).
With respect to claim 25, Uzoh teaches that “any of the processes, materials, functionalities, and structures disclosed in connection with FIGS. 1A-5I may be used in the embodiment of FIGS. 6A-6E.” Uzoh teaches in Fig. 4K:
a third semiconductor die (4a) bonded to the first semiconductor die (3a),
and a fourth semiconductor die (4b) bonded to the second semiconductor die (3b);
and a second gap-fill structure (includes third portion 16 of layer 15 and portion of liner layer12 in Fig. 4K. When applied to the embodiment of Fig. 6E this would also include layer 45) between the third semiconductor die and the fourth semiconductor die.
With respect to claim 26, Uzoh further teaches in Fig. 4K:
wherein the second gap-fill structure comprises the same materials as the first gap-fill structure. (both include layers 12 and 16)
With respect to claim 27, Uzoh further teaches:
wherein the barrier layer (15) includes a third portion (portion below 45/48) extending parallel to the common plane (plane that is top surface of the bonded structure) and connecting the first portion of the barrier layer to the second portion of the barrier layer (see annotated Fig. 6E as applied to claim 21 above).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2017/0038214 A1) in view of Chiou (US 2022/0068856 A1).
With respect to claim 6, Uzoh teaches in Fig. 4K:
further comprising:
a first bonding layer (redistribution layer 36) over the first top surface, the second top surface and the third top surface (over the top surfaces of 3a, 3b, 15, 12);
a second bonding layer bonded to the first bonding layer (Fig. 4K shows that dies 4a and 4b also include a bonding layer similar to bonding layer 11 of 3a and 3b as labeled in Fig. 4a);
a second semiconductor die (4a) over the second bonding layer;
Uzoh teaches that the structure of Fig. 6E can be applied to the teachings of the embodiment of Fig. 4 according to para. 69. Using the stack structure of Fig. 4 with the layer of Fig. 6E teaches:
a second insulating material encapsulating the second semiconductor die (insulating layer 45 of Fig. 6E applied to both top and bottom layers of the stack);
and a second polymer buffer (15) between a sidewall of the second insulating material (45) and a sidewall of the second semiconductor die (4a or 4b or Fig. 4K of Uzoh).
Uzoh fails to teach:
a second bonding layer bonded to the first bonding layer with metal-to-metal and dielectric-to-dielectric bonds;
Chiou teaches:
a second bonding layer bonded to the first bonding layer with metal-to-metal and dielectric-to-dielectric bonds (78 is bonded to 58 with dielectric-to-dielectric and metal-to-metal bonds, para. 32 “he dielectric layers 58 of the integrated circuit devices 50 are bonded to the dielectric layer 78 of the wafer 70 through dielectric-to-dielectric bonding, without using any adhesive material (e.g., die attach film), and the die connectors 56 of the integrated circuit devices 50 are bonded to the die connectors 76 of the wafer 70 through metal-to-metal bonding,”);
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute bonding method of Chiou for the bonding method of Uzo because they are known equivalents and it would have yielded the predictable result of bonding stacked semiconductor dies. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 7, Uzoh teaches all limitations of claim 1 upon which claim 7 depends. Uzoh further teaches:
conductive features (die connectors 56 which may be conductive pillars or pads) within the oxide layer (58);
Uzoh fails to teach:
and a redistribution structure over the oxide layer opposite the first semiconductor die ,
wherein the redistribution structure is electrically coupled to the first semiconductor die through the conductive features.
Chiou teaches:
and a redistribution structure (interconnect structure 54) over the oxide layer (58) opposite the first semiconductor die (52),
wherein the redistribution structure is electrically coupled to the first semiconductor die through the conductive features (para. 19 “The interconnect structure 54 is over the active surface of the semiconductor substrate 52, and is used to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit.”)
Uzoh discloses the claimed invention except for the redistribution structure over the oxide layer. Chiou discloses that it is known in the art to provide a redistribution structure under the oxide layer connected to the die through the conductive features. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Uzoh with the redistribution structure of Chiou, in order to connect the die to other portions of the package. See MPEP 2144.
Response to Arguments
Applicant’s arguments with respect to claims 1, 15, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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