DETAILED ACTION
This Office action is in response to the election filed on 24 October 2025. Claims 1-14 and 21-26 are pending in the application. Claims 15-20 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of the invention of Group I, on which claims 1-14 and 21-26 are readable, in the reply filed on 24 October 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the sacrificial structure" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Chen et al., US 2023/0197802.
With respect to claim 8, Chen et al. disclose a method for fabricating a semiconductor device, the method comprising:
forming structures 230 over a semiconductor substrate 202, wherein the structures 230 extend in an X-direction and are distanced apart from one another in a Y-direction perpendicular to the X-direction, as shown in Fig. 12;
removing a portion of at least one structure 230 to form a trench 250, as shown in Fig. 16;
forming an insulation material 256 in the trench 250, wherein the insulation material terminates at a first end wall, terminates at a second end wall, and extends in the Y-direction from the first end wall to the second end wall, as shown in Fig. 17;
forming a first element 258 adjacent to the first end wall, wherein a first terminal portion of the first element contacts the first end wall, as shown in annotated Fig. 17 below (see paragraphs [0042]-[0044]);
forming a second element 258 adjacent to the second end wall, wherein a second terminal portion of the second element contacts the second end wall, as shown in annotated Fig. 17 below (see paragraphs [0042]-[0044]); and
removing the first terminal portion to form a first opening and the second terminal portion to form a second opening, see Fig. 18 and paragraph [0045].
With respect to claim 9, the method of Chen et al. further comprises forming a first insulation region 264 in the first opening; and forming a second insulation region 264 in the second opening, as shown in Fig. 18, see paragraph [0046].
With respect to claim 10, in the method of Chen et al., the first terminal portion is a high-K dielectric; and the second terminal portion is a high-K dielectric, since 256 is a high-k dielectric, as disclosed in paragraphs [0042]-[0043].
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With respect to claim 12, in the method of Chen et al., the portion of the at least one structure 230 is located between a first remaining structure 215 and a second remaining structure 215;
forming the first element 258 comprises forming a first metal gate (see paragraph [0044]) over the first remaining structure 215; and
forming the second element 258 comprises forming a second metal gate (see paragraph [0044]) over the second remaining structure 215,
wherein the first metal gate 258 and the second metal gate 258 are aligned in a first gate line extending in the Y-direction, as shown in Fig. 17.
With respect to claim 13, the method of Chen et al. further comprises: forming a second gate line (gates of the transistors shown in Fig. 2) extending in the Y-direction and distanced from the first gate line in the X-direction; wherein the first opening extends through the second gate line, wherein the second opening extends through the second gate line, and wherein a second gate structure is defined between the first opening and the second opening, as shown in Figs. 1, 2, and 3, see paragraphs [0017]-[0023].
With respect to claim 14, in the method of Chen et al., the structures 230 comprise fins 212, as shown in Figs. 11 and 12;
the method further comprises forming a sacrificial gate 230 over the fins 212, as shown in Figs. 11 and 12;
removing the portion of at least one structure 230 to form the trench 250 comprises etching a selected portion of at least one fin 212 and a portion of the sacrificial gate 230 over the selected portion, as shown in Figs. 15 and 16;
the method further comprises removing an adjacent portion of the sacrificial structure 252 to form a gate cavity after forming the insulation material 256 in the trench 250;
the first element is a first metal gate 258; and
forming the first element adjacent to the first end wall comprises forming the first metal gate 258 in the gate cavity 250, as shown in Fig. 17.
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Claims 21-24 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Xie et al., US 2021/0234018.
With respect to claim 21, Xie et al. disclose a method comprising:
forming a first metal gate 950 extending in a Y-direction to a first end in a first device area, wherein the first device area is distanced from a second device area in an X-direction perpendicular to the Y-direction, see annotated Figs. 2 and 9 below;
forming an insulation structure 575 abutting the first device area and the second device area and located between the first device area and the second device area, wherein the insulation structure 575 extends in the Y-direction to a first end, see Fig. 5 and paragraph [0083]; and
forming a dielectric structure 224 extending in the X-direction, wherein the dielectric structure 224 abuts the first end of the first metal gate and the first end of the insulation structure 575.
With respect to claim 22, in the method of Xie et al., the second device area comprises a second metal gate 950 extending in a Y-direction to a first end; the dielectric structure 224 abuts the first end of the first metal gate, the first end of the insulation structure 575, and the first end of the second metal gate., as shown in annotated Figs. 2C and 9 below.
With respect to claim 23, in the method of Xie et al., the first metal gate extends in the Y-direction from a second end to the first end; the second metal gate extends in the Y-direction from a second end to the first end; the insulation structure 575 extends in the Y-direction from a second end to the first end; the dielectric structure 224 is a first dielectric structure; the semiconductor device further comprises a second dielectric structure 224 extending in the X-direction; and the second dielectric structure abuts the second end of the first metal gate 950, the second end of the insulation structure 575, and the second end of the second metal gate 950, see annotated Figs. 2C and 9 below.
With respect to claim 24, the method of Xie et al. further comprises forming a third metal gate 950 extending in a Y-direction to a first end in a third device area, wherein the third metal gate 950 is co-linear with the insulation structure 575, and wherein the dielectric structure 224 abuts the first end of the third metal gate 950, see annotated Figs. 2C and 9 below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al., US 2021/0234018, as applied to claim 24 above, and further in view of Liu et al., US 2015/0372104.
With respect to claim 25, in the method of Xie et al., the third metal gate 950 comprises a high-k gate dielectric 930 and a metal layer 925, see paragraphs [0102]-[0108]. However, Xie et al. lack anticipation of the high-K gate dielectric 930 not being located between the metal layer and the dielectric structure 224, since Xie et al. teach the high-k dielectric 930 covers the dielectric structure 224 (see paragraph [0103]), as shown in Fig. 9. In the same field of endeavor, Liu et al. disclose a method of fabricating a gate-all-around field effect transistor (GAAFET) in which the high-k gate dielectric 239 is formed only on the exposed channels within the gate region, see paragraph [0047]. As shown in Fig. 10B of Liu et al., the high-k dielectric 239 is not located between the metal gate layer 241 and a dielectric structure 223. In light of the teaching of Liu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the high-k dielectric only in the bottom of voids 625 and not on the sidewalls of the void in the known method of Xie et al., since this is a known alternate method of forming a high-k gate dielectric in a GAAFET. Forming the high-k dielectric 930 only in the bottom of voids 625 would result in the
With respect to claim 26, Xie et al. disclose that the third metal gate comprises a high-K gate dielectric 930 and a metal layer 925, as shown in Fig. 9. Xie et al. lack anticipation of the metal layer 925 directly contacting the dielectric structure 224, since Xie et al. teach the high-k dielectric 930 covers the dielectric structure 224 (see paragraph [0103]), as shown in Fig. 9. In the same field of endeavor, Liu et al. disclose a method of fabricating a gate-all-around field effect transistor (GAAFET) in which the high-k gate dielectric 239 is formed only on the exposed channels within the gate region, see paragraph [0047]. As shown in Fig. 10B of Liu et al., the high-k dielectric 239 is not located between the metal gate layer 241 and a dielectric structure 223. In light of the teaching of Liu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the high-k dielectric only in the bottom of voids 625 and not on the sidewalls of the void in the known method of Xie et al., since this is a known alternate method of forming a high-k gate dielectric in a GAAFET. Forming the high-k dielectric 930 only in the bottom of voids 625 would result in the metal layer 925 directly contacting the dielectric structure 224 in the known method of Xie et al. high-K gate dielectric 930 not being located between the metal layer and the dielectric structure 224 in the known method of Xie et al.
Allowable Subject Matter
Claims 1-7 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest a method comprising: forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing at least a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion of the sacrificial layer to form a cavity, wherein the cavity is partially defined by the end wall of the insulation structure; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 11, the closest prior art of record is Chen et al. Although Chen et al. teach forming a shallow trench isolation layer 214 over the semiconductor substrate 202 and between the structures 230, wherein the first element 258 is located over the shallow trench isolation layer 214, and the second element 258 is located over the shallow trench isolation layer 214, as shown in Fig. 10. However, Chen et al. fail to teach or suggest removing the first terminal portion to form the first opening comprises etching into the shallow trench isolation layer; and removing the second terminal portion to form the second opening comprises etching into the shallow trench isolation layer.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various methods of fabricating nanosheet transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898