DETAILED ACTION
This Office action is in response to the election filed on 24 October 2025. Claims 1-14 and 27-32 are pending in the application. Claims 15-26 have been cancelled. Claims 27-32 are newly submitted.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of the invention of Group I, on which claims 1-14 and 21-26 are readable, in the reply filed on 24 October 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
In light of the amendment made to dependent claim 14, the rejection of claim 14 under 35 U.S.C. 112(b) has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 9, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Balakrishnan et al., US 2018/0233502, newly cited.
With respect to claim 8, Balakrishnan et al. disclose a method for fabricating a semiconductor device, shown in Figs. 13-25, the method comprising:
forming structures 42A and 42B over a semiconductor substrate 10, wherein the structures 42A and 42B extend extending in an X-direction and are distanced apart from one another in a Y-direction perpendicular to the X-direction, as shown in Figs. 11-13;
removing a portion of at least one structure 42A and 42B to form a trench, as shown in Fig. 14;
forming an insulation material 54 in the trench, wherein the insulation material 54 terminates at a first end wall 44P, terminates at a second end wall 46P, and extends in the Y-direction from the first end wall 44P to the second end wall 46P, as shown in Fig. 15;
removing material located outside of the trench to form a first cavity adjacent to the first end wall 44P and a second cavity adjacent to the second end wall 46P, as shown in Fig. 23;
forming a first element 72/74/78 in the first cavity adjacent to the first end wall 44P, wherein a first terminal portion of the first element 72/74/78 contacts the first end wall 44P, as shown in Fig. 24;
forming a second element 72/76/78 in the second cavity adjacent to the second end wall 46P, wherein a second terminal portion of the second element 72/76/78 contacts the second end wall 44P, as shown in Fig.24; and
removing the first terminal portion to form a first opening (adjacent 60A (sic)) and removing the second terminal portion to form a second opening (adjacent 66B), as shown in Fig. 25.
With respect to claim 9, the method of Balakrishnan et al. further comprises removing the material located outside of the trench to form the first cavity adjacent to the first end wall 44P and the second cavity adjacent to the second end wall 46P comprises uncovering a first portion of the first end wall 44P and a second portion of the second end wall 46P, as shown in Fig. 23.
With respect to claim 13, the method of Balakrishnan et al. further comprises: forming a dielectric layer 36/38 over a semiconductor material 34, wherein removing the portion of at least one structure 42A and 42B to form the trench comprises etching through the dielectric layer 36/38 to the semiconductor material 34, as shown in Figs. 13-14 and paragraphs [0066]-[0068].
With respect to claim 14, the method of Balakrishnan et al. further comprising forming a first isolation feature 72 in the first opening, see Fig. 24.
Claims 27, 30, and 32 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Chen et al., US 2023/0197802, of record.
With respect to claim 27, Chen et al. disclose a method, shown in Figs. 9-17, the method comprising:
forming an insulation structure 234 extending in a length direction (z-direction) to a first end, as shown in Fig. 15;
forming a metal gate 252 co-linear with the insulation structure 234 and having a first end facing the first end of the insulation structure 234, as shown in Fig. 17 (see annotated Fig. 17 below);
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forming a dielectric structure 214/220/221/222 (see Fig. 9) extending transverse (x-direction) to the length direction (z-direction) and located between the insulation structure 234 and the metal gate 252, as shown in Fig. 17, wherein:
the metal gate 252 comprises a gate dielectric 256 and a metal layer 258 (see paragraph [0056]);
the dielectric structure 214/220/221/222 defines a first interface with the insulation structure 234 and a second interface with the metal layer 258 of the metal gate 252;
the first interface and the second interface are transverse to the length direction (z-direction); and
the metal layer 258 of the metal gate 252 directly contacts the dielectric structure 214/220/221/222 at the second interface, as shown in annotated Fig. 17 below.
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With respect to claim 30, in the method of Chen et al., the gate dielectric 256 of the metal gate 252 is a high-K dielectric having a dielectric constant greater than that of silicon dioxide, see paragraph [0043].
With respect to claim 32, in the method of Chen et al., the metal gate 252 further comprises: a first sidewall extending in the length direction (z-direction); a second sidewall extending in the length direction (z-direction), as shown in Fig. 17; a first portion of the gate dielectric 256 located between the metal layer 258 and the first sidewall; and a second portion of the gate dielectric located between the metal layer and the second sidewall, wherein the gate dielectric 256 is absent at the second interface, as shown in annotated Fig. 17 below.
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Allowable Subject Matter
Claims 1-7 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest a method comprising: forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing at least a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion of the sacrificial layer to form a cavity, wherein the cavity is partially defined by the end wall of the insulation structure; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening, as required in independent claim 1.
Claims 10-12, 28, 29, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Balakrishnan et al.is applied as above. However, Balakrishnan et al. lack anticipation of removing the first terminal portion to form a first opening comprises removing the first end wall and removing the second terminal portion to form a second opening comprises removing the second end wall, as required in dependent claim 10..
Although Balakrishnan et al. teaches to form an isolation layer 16 between the structures, Balakrishnan et al. fails to teach or suggest removing the first terminal portion to form the first opening comprises etching into the shallow trench isolation layer; and removing the second terminal portion to form the second opening comprises etching into the shallow trench isolation layer, as required in dependent claim 11.
With respect to claim 12, although Balakrishnan et al. teaches forming the structures 42A and 42B extending in the X-direction and distanced apart from one another in the Y-direction perpendicular to the X-direction over a semiconductor substrate 10; Balakrishnan et al. fail to teach or suggest removing the portion of at least one structure to form the trench comprises removing a portion of the semiconductor substrate under the portion of at least one structure.
With respect to claim 28, the closest prior art of record is Chen et al. Chen et al. disclose the insulation structure 234 extends to a second end; the method further comprises forming a second metal gate co-linear with the insulation structure 234 and having a first end facing the second end of the insulation structure 234, as shown in Fig. 17. However, Chen et al. lack anticipation of forming a second dielectric structure extending transverse to the length direction and located between the insulation structure and the second metal gate, wherein: the second metal gate comprises a second gate dielectric 256 and a second metal layer 258;the second dielectric structure defines a third interface with the insulation structure and a fourth interface with the second metal layer of the second metal gate; the third interface and the fourth interface are transverse to the length direction; and the second metal layer of the second metal gate directly contacts the second dielectric structure at the fourth interface, as required in dependent claim 28.
Claim 29 is objected to by virtue of its dependence on claim 28.
With respect to claim 31, Chen et al. is the closest prior art of record. .Chen et al. disclose forming the metal gate 252 comprises: forming a cavity bounded at least in part by the first end of the insulation structure 234, as shown in Fig. 16; depositing the gate dielectric 256 in the cavity, wherein an end portion of the gate dielectric is located on the first end of the insulation structure 234; and depositing the metal layer 258 over the gate dielectric 256 in the cavity, see Fig. 16 and paragraphs [0041]-[0044]. However, Chen et al. do not teach or suggest forming the dielectric structure comprises removing the end portion of the gate dielectric such that the metal layer directly contacts the dielectric structure at the second interface, as required in dependent claim 31.
Response to Arguments
Applicant's arguments filed 15 June 2026 have been fully considered but they are not persuasive. The method of independent claim 8 is not deemed patentable over the prior art method of Balakrishnan et al., as applied herein. Newly submitted independent claim 27 is not patentable in light of Chen et al., as applied in the rejection above.
.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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