DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1 in Figs. 20A-20B, 45A-45B in the reply filed on 11/04/2025 is acknowledged. Claim 4 has been canceled. Claim 21 is added.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3, 7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-4, 7 of copending Application No. 19/295268 (hereinafter referred to as Hsiung), respectively. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 2 of Hsiung teaches a device comprising:
a source/drain contact (lines 11-12 of claim 1 of Hsiung) over a source/drain region (lines 9-10) of a transistor;
an etch stop layer (line 13 of claim 1 of Hsiung) over the source/drain contact;
an interlayer dielectric (ILD) layer (line 14 of claim 1 of Hsiung) over the etch stop layer; and
a source/drain via (lines 16-19 of claim 1 of Hsiung) extending through the ILD layer and the etch stop layer to the source/drain contact, wherein the etch stop layer has an oxidized region in contact with the source/drain via and an un-oxidized region (claim 2 of Hsiung) separating the oxidized region from the source/drain contact.
Claim 2 reads on claim 3 of Hsiung.
Claim 3 reads on claim 4 of Hsiung.
Claim 7 reads on claim 7 of Hsiung.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2019/0131430 A1) in view of Jangjian et al. (US 2016/0111325 A1).
Regarding claim 1, Xie teaches a device (device in Fig. 14 of Xie) comprising:
a source/drain contact (42 in Fig. 142) over a source/drain region of a transistor;
an etch stop layer (46) over the source/drain contact;
an interlayer dielectric (ILD) layer (48) over the etch stop layer; and
a source/drain via (60) extending through the ILD layer and the etch stop layer to the source/drain contact.
But Xie does not teach that wherein the etch stop layer has an oxidized region in contact with the source/drain via and an un-oxidized region separating the oxidized region from the source/drain contact.
Jangjian teaches a multilayer etch stop layer (40 in Fig. 10 of Jangjian) comprising: a contact (36 in Fig. 10); an etch stop layer (40) over the contact; an ILD layer (42) over the etch stop layer; a conductive via (54) through the ILD layer and the etch stop layer to the contact, wherein the etch stop layer has an oxidized region (40c, as described in [0032]) in contact with the conductive via and an un-oxidized region (40a-40b, as described in [0023] of Jangjian) separating the oxidized region from the contact.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the multilayer etch stop of Jangjian in place of the etch stop layer 46 of Xie in order to be more effective as stopping the etching of the ILD layer (see [0037] of Jangjian).
As incorporated, etch stop layer 36 of Xie is replaced by etch stop layer 40a-40c of Jangjian. And layer 40c of Jangjian is the oxidized region of the etch stop layer, the layer 40a-40b is the un-oxidized region of the etch stop layer.
Regarding claim 2, Xie in view of Jangjian teaches all limitations of the device of claim 1, and also teaches wherein the un-oxidized region of the etch stop layer is in contact with the source/drain contact (as shown in Fig. 11 of Jangjian and Fig. 14 of Xie).
Regarding claim 3, Xie in view of Jangjian teaches all limitations of the device of claim 1, and also teaches wherein the source/drain via forms a first interface (interface of source/drain via 60 of Xie and etch stop layer 40c of Jangjian) with the oxidized region and a second interface (interface of source/drain via 60 of Xie and etch stop layer 40a-b of Jangjian) with the un-oxidized region, and the second interface is aligned with the first interface (as shown in Fig. 10 of Jangjian).
Regarding claim 5, Xie in view of Jangjian teaches all limitations of the device of claim 1, and also teaches wherein the source/drain via has a linear sidewall in contact with the oxidized region and the un-oxidized region of the etch stop layer (as shown in Fig. 10 of Jangjian).
Regarding claim 6, Xie in view of Jangjian teaches all limitations of the device of claim 5, and also teaches wherein the linear sidewall of the source/drain via has a top segment above the oxidized region and the un-oxidized region of the etch stop layer (as shown in Fig. 14 of Xie and Fig. 10 of Jangjian).
Claims 8-11, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Jangjian.
Regarding claim 8, Xie teaches a device (device in Fig. 14 of Xie), comprising:
a gate structure (34 in Fig. 14 of Xie) over a substrate;
source/drain regions (18) at opposite sides of the gate structure;
source/drain contacts (42. It is implicit that each S/D region 18 has its own contact 34) over the source/drain regions, respectively;
a gate dielectric cap (30-36 in Fig. 14) over the gate structure and having opposite sidewalls interfacing the source/drain contacts;
an etch stop layer (46) over the source/drain contacts and the gate dielectric cap; and
a source/drain via (60) extending through the etch stop layer to one of the source/drain contacts.
But Xie does not teach that wherein the etch stop layer has an oxidized region interfacing opposite sidewalls of the source/drain via.
Jangjian teaches a multilayer etch stop layer (40 in Fig. 10 of Jangjian) comprising: a contact (36 in Fig. 10); an etch stop layer (40) over the contact; an ILD layer (42) over the etch stop layer; a conductive via (54) through the ILD layer and the etch stop layer to the contact, wherein the etch stop layer has an oxidized region (40c, as described in [0032]) in contact with the conductive via and an un-oxidized region (40a-40b, as described in [0023] of Jangjian) separating the oxidized region from the contact.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the multilayer etch stop of Jangjian in place of the etch stop layer 46 of Xie in order to be more effective as stopping the etching of the ILD layer (see [0037] of Jangjian).
As incorporated, etch stop layer 36 of Xie is replaced by etch stop layer 40a-40c of Jangjian. And layer 40c of Jangjian is the oxidized region of the etch stop layer, the layer 40a-40b is the un-oxidized region of the etch stop layer.
Regarding claim 9, Xie in view of Jangjian teaches all limitations of the device of claim 8, and also teaches wherein an interface formed by the oxidized region of the etch stop layer and the source/drain via is slant (as shown in Fig. 14 of Xie and Fig. 10 of Jangjian).
Regarding claim 10, Xie in view of Jangjian teaches all limitations of the device of claim 8, and also teaches wherein an interface formed by the oxidized region of the etch stop layer and the source/drain via is vertical (“vertical” is interpreted as any angle close to 90⁰. As such, the angle of the sidewall of contact via 60 of Xie is close to this).
Regarding claim 11, Xie in view of Jangjian teaches all limitations of the device of claim 8, and also teaches wherein the oxidized region of the etch stop layer is separated from the gate dielectric cap (as combined in claim 8 above).
Regarding claim 15, Xie in view of Jangjian teaches all limitations of the device of claim 8, and also teaches wherein the gate dielectric cap includes silicon nitride (as described in [0026] and [0030] of Xie).
Regarding claim 16, Xie in view of Jangjian teaches all limitations of the device of claim 8, and also teaches wherein the device is a fin field-effect transistor (FinFET) (device in Fig. 14 is a finfet) or a gate-all-around (GAA) transistor.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Jangjian, as applied to claim 8 above and further in view of Hsieh et al. (US 10083863 B1).
Regarding claim 12, Xie in view of Jangjian teaches all limitations of the device of claim 8, but does not teach further comprising: a metal cap between the gate dielectric cap and the gate structure.
Hsieh teaches a device (Fig. 2 of Hsieh) comprising: a gate structure (209) over a substrate; a gate contact structure extending through an etch stop (244) and an ILD layer (246); a metal cap (242) made of tungsten (column 17 line 29 of Hsieh).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have included a metal gate cap from tungsten in order to increase the performance of the device.
Regarding claim 13, Xie-Jangjian-Hsieh teaches all limitations of the device of claim 12, but does not teach wherein the metal cap is fluorine-free tungsten.
Hsieh discloses that the tungsten in a gate structure is a fluorine-free tungsten (column 14 lines 60-62 of Hsieh).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the metal gate cap with fluorine-free tungsten in order to increase reliability.
Claims 8, 14, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of You (US 2006/0084275 A1).
Regarding claim 8, Xie teaches a device (device in Fig. 14 of Xie), comprising:
a gate structure (34 in Fig. 14 of Xie) over a substrate;
source/drain regions (18) at opposite sides of the gate structure;
source/drain contacts (42. It is implicit that each S/D region 18 has its own contact 34) over the source/drain regions, respectively;
a gate dielectric cap (30-36 in Fig. 14) over the gate structure and having opposite sidewalls interfacing the source/drain contacts;
an etch stop layer (46) over the source/drain contacts and the gate dielectric cap; and
a source/drain via (60) extending through the etch stop layer to one of the source/drain contacts.
But Xie does not teach that wherein the etch stop layer has an oxidized region interfacing opposite sidewalls of the source/drain via.
You teaches a multilayer etch stop layer (215 in Figs. 4C of You) comprising: a contact (205 in Fig. 4C); an etch stop layer (215) over the contact; an ILD layer (220) over the etch stop layer; a conductive via (235) through the ILD layer and the etch stop layer to the contact, wherein the etch stop layer has an oxidized region (metal oxide layer 245, as described in [0048] of You) interfacing opposite sidewalls of the conductive via, and an un-oxidized region (silicon nitride layer 240, as described in [0048] of You).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the multilayer etch stop of Jangjian in place of the etch stop layer 46 of Xie in order to be more effective as stopping the etching of the ILD layer.
As incorporated, etch stop layer 36 of Xie is replaced by etch stop layer 215 of You. And layer 245 of You is the oxidized region of the etch stop layer, the layer 240 is the un-oxidized region of the etch stop layer.
Regarding claim 14, Xie in view of You teaches all limitations of the device of claim 8, and also teaches wherein the etch stop layer includes silicon nitride (as described in [0048] of You).
Regarding claim 17, Xie teaches a device (device in Fig. 14 of Xie), comprising:
a source region (left S/D region 18 in Fig. 14) and a drain region (right S/D region 18) over a substrate (fin 10);
a channel region (region of fin 10 under the gate 34 at the middle of Fig. 14) between the source region and the drain region;
a source contact (42) over the source region;
a gate structure (34) over the channel region;
a dielectric cap (30 and 36) over the gate structure;
a etch stop layer (46) over the dielectric cap; and
a first via (60) extending through the nitride-based etch stop layer to the source contact.
But Xie does not teach that the etch stop layer is nitride-based and the nitride-based etch stop layer having a first oxidized region over the source contact, the first via extending through the first oxidized region of the nitride-based etch stop layer.
You teaches a multilayer etch stop layer (215 in Figs. 4C of You) comprising: a contact (205 in Fig. 4C); an etch stop layer (215) over the contact; an ILD layer (220) over the etch stop layer; a conductive via (235) through the ILD layer and the etch stop layer to the contact, wherein the etch stop layer has an oxidized region (metal oxide layer 245, as described in [0048] of You) interfacing opposite sidewalls of the conductive via, and an un-oxidized region (silicon nitride layer 240, as described in [0048] of You).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the multilayer etch stop of Jangjian in place of the etch stop layer 46 of Xie in order to be more effective as stopping the etching of the ILD layer.
As incorporated, etch stop layer 36 of Xie is replaced by etch stop layer 215 of You. And layer 245 of You is the oxidized region of the etch stop layer, the layer 240 is the un-oxidized region of the etch stop layer.
Regarding claim 18, Xie in view of You teaches all limitations of the device of claim 17, and further comprising: a drain contact (it is implicit that the drain region 18 also has a contact 60 to it in order to obtain electrical signal from the transistor) over the drain region, the nitride-based etch stop layer having a second oxide region (region of etch stop layer 245 surrounding the drain contact 60) over the drain contact.
But Xie in view of You does not teach that the device comprising: a second via extending through the second oxide region of the nitride-based etch stop layer to the drain contact.
However, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have duplicated the contact structure to the source region to make the contact structure to the drain region in order to simplify manufacturing process.
Regarding claim 19, Xie in view of You teaches all limitations of the device of claim 18, and also teaches wherein the second oxide region is spaced apart from the first oxide region (as shown in Fig. 14 of Xie, the region surrounding the first via 60 to the source is separated from the region surrounding the second via 60).
Regarding claim 20, Xie in view of You teaches all limitations of the device of claim 17, and also teaches wherein the first oxide region is spaced apart from the source contact (as combined in claim 17 above).
Allowable Subject Matter
Claims 7 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art of record does not disclose or fairly suggest a device comprising: “a gate structure over a channel region of the transistor, wherein the oxidized region non-overlaps the gate structure” along with other limitations of the claim 1.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898