DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 and 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-13 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0165730 A1, hereinafter Chen ‘730) in view of Chung et al. (US 2022/0037497 A1, hereinafter Chung ‘497) in view of the following arguments.
With respect to Claim 1 Chen ‘730 discloses a semiconductor device (Fig 1-27), comprising:
a substrate (101, Fig 21B, Para [0023]);
a first lower source/drain feature (leftmost 1602, Fig 21A, Para [0057]) and a second lower source/drain feature (rightmost 1602, Fig 21A, Para [0057]) disposed over the substrate (101);
a first plurality of nanostructures (106b, Fig 21B of Chen ‘730, Para [0054]) extending between (disclosed in Fig 21B and Para [0054]) the first lower source/drain feature (leftmost 1602) and the second lower source/drain feature (rightmost 1602);
at least one channel layer (uppermost 106c/2602/1504/lowermost 106c, Fig 26, Para [0066], hereinafter CL) over the first plurality of nanostructures (106b);
a first gate structure (2502, Fig 25, Para [0065]) wrapping (disclosed in Fig 25) around each of the first plurality of nanostructures (106b);
a first contact etch stop layer (CESL) (1802 on leftmost 1602, Fig 21B, Para [0055]) and a first dielectric layer (1902 on leftmost 1602, Fig 21B, Para [0056]) over the first lower source/drain feature (leftmost 1602);
a second CESL (1802 on rightmost 1602, Fig 21B, Para [0055]) and a second dielectric layer (1902 on rightmost 1602, Fig 21B, Para [0056]) over the second lower source/drain feature (rightmost 1602);
a first upper source/drain feature (leftmost 2102, Fig 21B, Para [0058]);
a second upper source/drain feature (rightmost 2102, Fig 21B, Para [0058]);
a second plurality of nanostructures (106d, Fig 21B, Para [0058]) disposed over (disclosed in Fig 21B) the at least one channel layer (lowermost 106c) and extending between the first upper source/drain feature (leftmost 2102) and the second upper source/drain feature (rightmost 2102); and
a second gate structure (2702, Fig 27, Para [0067]) wrapping around (disclosed in Fig 27) each of the second plurality of nanostructures (106d) wherein the first CESL (1802 on leftmost 1602) and the second CESL (1802 on rightmost 1602) interface sidewalls of the at least one channel layer (CL) (Fig 21B and Para [0057] disclose liners 1802 in contact with layers 106c and 104c, 104c is replaced with dielectric layer 2602, as disclosed in Para [0066] which would then have 1802 interface with CL).
But Chen ‘730 fails to explicitly disclose a first etch stop layer (ESL) over and in contact with the first CESL and the first dielectric layer; a second ESL over and in contact with the second CESL and the second dielectric layer.
Nevertheless, in a related endeavor (Fig 1-16C of Chung ‘497), Chung ‘497 teaches a first etch stop layer (ESL) (leftmost 242, Fig 12A of Chung ‘497, Para [0041]) over and in contact with (Fig 12A of Chung ‘497 discloses leftmost 242 over and in contact with 230 and 232) the first CESL (leftmost 230, Fig 11A of Chung ‘497, Para [0039]) and the first dielectric layer (leftmost 232, Fig 11A of Chung ‘497, Para [0039]); a second ESL (rightmost 242, Fig 12A of Chung ‘497, Para [0041]) over and in contact with (Fig 12A of Chung ‘497 discloses rightmost 242 over and in contact with 230 and 232) the second CESL (rightmost 230, Fig 11A, Para [0039]) and a second dielectric layer (rightmost 232, Fig 11A, Para [0039]);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s teaching of a first etch stop layer (ESL) over and in contact with the first CESL and the first dielectric layer; a second ESL over and in contact with the second CESL and the second dielectric layer into Chen ‘730’s device. Chen ‘730 discloses a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer. Chung ‘497 also teaches a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer and further teaches an etch stop layer over the top of the contact etch stop layer and dielectric layer. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because this additional etch stop layer can provide additional protection to the dielectric layer during etching steps to remove sacrificial layers as the upper gate features are formed and it will act as an additional dielectric layer to reduce parasitic capacitance in the device.
As incorporated, the teaching of an etch stop layer (leftmost 242 and rightmost 242) of Chung ‘497 would be used over and in contact with the first and second CESL (1802 on leftmost 1602 and 1802 on rightmost 1602) and the first and second dielectric layer (1902 on leftmost 1602 and rightmost 1602) of Chen ‘730 so that first upper source/drain feature (leftmost 2102 of Chen ‘730) would be over the first ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) and a second upper source/drain feature (rightmost 2102 of Chen ‘730) would be over the second ESL (rightmost 242 of Chung ‘497 as incorporated in Chen ‘730).
With respect to Claim 2 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chen ‘730 further discloses wherein the first CESL (1802 on leftmost 1602) and the second CESL (1802 on rightmost 1602) but Chen ‘730 fails to explicitly disclose the CESL comprise silicon nitride or silicon oxynitride.
and Chung ‘497 further discloses wherein the first CESL (leftmost 230) and the second CESL (rightmost 230) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 is silicon nitride or silicon oxynitride).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s further teaching of a CESL comprises silicon nitride or silicon oxynitride into Chen ‘730’s device. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because Chung ‘497 is open to the composition of the CESL and Chen ‘730 teaches a well-known material to act as an etch to achieve the well-known advantage of protecting layers of a device during etch process steps.
As incorporated, the teaching of silicon nitride or silicon oxynitride as a contact etch stop layer of Chung ‘497 would be used as the material of the first CESL (1802 on leftmost 1602) and the second CESL (1802 on rightmost 1602) of Chen ‘730 as modified by Chung ‘497.
With respect to Claim 3 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chen ‘730 as modified by Chung ‘497 further discloses
wherein the first ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) and the second ESL (rightmost 242 of Chung ‘497 as incorporated in Chen ‘730) comprise silicon nitride (Para [0041] of Chung ‘497 discloses 242 as silicon nitride),
and Chen ‘730 further discloses wherein the first dielectric layer (1902 on leftmost 1602) and the second dielectric layer (1902 on rightmost 1602) comprise silicon oxide (Para [0056] discloses 1902 as the same material as layer 402 and Para [0036] discloses 402 as silicon oxide).
With respect to Claim 4 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chen ‘730 further discloses
wherein the first gate structure (2502) and the second gate structure (2702) are vertically spaced apart from one another (Fig 27 discloses 2502 and 2702 separated by 2602) by a middle dielectric layer (2602/1504, Fig 27, Para [Para 0063 and 0066] discloses dielectric spacers 1504 with dielectric layer 2602 formed between, 2602/1504 hereinafter MDL),
wherein the at least one channel layer (CL) comprises two channel layers (two layers 106c, Fig 27, Para [0066] disclose two channel layers 106c, hereinafter 2CL),
wherein the middle dielectric layer (MDL) is disposed between (MDL between layers 106c disclosed in Para [0066] and Fig 27) the two channel layers (2CL).
With respect to Claim 5 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 4, and Chen ‘730 further discloses wherein a sidewall (1504 which, as disclosed above are sidewalls of 2602) of the middle dielectric layer (MDL) is in contact with the first CESL (1802 on leftmost 1602) (Fig 21B and Para [0057] disclose liner leftmost 1802 in contact with layer 104c/1504, 104c which is replaced with dielectric layer 2602, as disclosed in Para [0066] which would then have leftmost 1802 interface with MDL (1504/2602)).
With respect to Claim 9 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chen ‘730 as modified by Chung ‘497
wherein the first plurality of nanostructures (106b) are interleaved (disclosed in Fig 15 and Para [0052]) by a first plurality of inner spacer features (1504 on 104b layers, Fig 15, Para [0051 and 0052]),
wherein the second plurality of nanostructures (106d) are interleaved by a second plurality of inner spacer features (1504 on 104d layers, Fig 15, Para [0051 and 0052]),
wherein the first CESL (1802 on leftmost 1602) is in contact with at least one (Fig 20B discloses 1802 on leftmost 1602 in contact with at least one 1504 on 104b) of the first plurality of inner spacer features (1504 on 104b layers),
wherein the first ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730 as described above) is in contact with at least one (as described above, leftmost 242 of Chung ‘497 as incorporated in Chen ‘730 is over structure 1902 and 1802, therefore it would be in contact with at least one 1504 on 104d, reference Fig 21B) of the second plurality of inner spacer features (1504 on 104d layers).
With respect to Claim 10 Chen ‘730 discloses a semiconductor structure (Fig 1-27), comprising:
a substrate (101, Fig 21B, Para [0023]);
a first source/drain feature (leftmost 1602, Fig 21A, Para [0057]) disposed on the substrate (101);
bottom channel members (106b, Fig 21B, Para [0063]) over the substrate (101), the first source/drain feature (leftmost 1602, Fig 21A, Para [0057]) interfacing end sidewalls (sidewalls of 106b) (Fig 21B and Para [0054] disclose sidewalls of 106b interfacing leftmost 1602) of the bottom channel members (106b);
a first channel layer (lowermost 106c, Fig 26, Para [0066]) over (disclosed in Fig 21B) the bottom channel members (106b);
a middle dielectric layer (2602/1504, Fig 27, Para [Para 0063 and 0066] discloses dielectric spacers 1504 with dielectric layer 2602 formed between, 2602/1504 hereinafter MDL) over (disclosed in Fig 26) the first channel layer (106c);
a second channel layer (uppermost 106c, Fig 26, Para [0066]) over (disclosed in Fig 26) the middle dielectric layer (MDL);
a first contact etch stop layer (CESL) (1802 on leftmost 1602, Fig 21B, Para [0055]) disposed on the first source/drain feature (leftmost 1602) and interfacing with sidewalls (sidewalls of 106c) of the first channel layer (lowermost 106c), the middle dielectric layer (MDL), and the second channel layer (sidewalls of uppermost 106c) (Fig 21B and Para [0057] disclose 1802 on leftmost 1602 interface with sidewalls of lowermost and uppermost layers 106c and with sidewalls of 104c. Layer 104c is replaced with dielectric layer 2602, as disclosed in Para [0066] which means 1802 on leftmost 1602 would also interface with sidewalls (1504) of MDL (1504/2602));
a first dielectric layer (1902 on leftmost 1602, Fig 21B, Para [0056]) disposed over the first CESL (1802 on leftmost 1602) and spaced apart from (Fig 21B discloses 1902 on leftmost 1602 over 1802 and spaced apart from 1602 by 1802) the first source/drain feature (leftmost 1602);
a second source/drain feature (leftmost 2102, Fig 21B, Para [0058]);
a second (CESL) (2202, Fig 22, Para [0060]) disposed on (disclosed in Fig 22 and Para [0060]) the second source/drain feature (leftmost 2102); and a second dielectric layer (2204, Fig 22, Para [0060]) disposed over the second CESL (2202) and spaced apart from (Fig 22 and Para [0060] disclose 2204 spaced apart from 2102 by 2202) the second source/drain feature (2102),
wherein the first source/drain feature (leftmost 1602) comprises silicon and an n-type dopant (Para [0053] discloses 1602 as n-type and comprising Si),
wherein the second source/drain feature (leftmost 2102) comprises silicon germanium and a p- type dopant (Para [0058] discloses leftmost 2102 as p-type and comprising SiGe).
But Chen ‘730 fails to explicitly disclose an etch stop layer (ESL) disposed on and in contact with the first CESL and the first dielectric layer.
Nevertheless, in a related endeavor (Fig 1-16C of Chung ‘497), Chung ‘497 teaches a first etch stop layer (ESL) (leftmost 242, Fig 12A of Chung ‘497, Para [0041]) on and in contact with (Fig 12A of Chung ‘497 discloses leftmost 242 over and in contact with 230 and 232) the first CESL (leftmost 230, Fig 11A of Chung ‘497, Para [0039]) and the first dielectric layer (leftmost 232, Fig 11A of Chung ‘497, Para [0039]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s teaching of a first etch stop layer (ESL) on and in contact with the first CESL and the first dielectric layer into Chen ‘730’s device. Chen ‘730 discloses a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer. Chung ‘497 also teaches a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer and further teaches an etch stop layer over the top of the contact etch stop layer and dielectric layer. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because this additional etch stop layer can provide additional protection to the dielectric layer during etching steps to remove sacrificial layers as the upper gate features are formed and it will act as an additional dielectric layer to reduce parasitic capacitance in the device.
As incorporated, the teaching of an etch stop layer (leftmost 242) of Chung ‘497 would be used on and in contact with the first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602) of Chen ‘730 so that second source/drain feature (leftmost 2102 of Chen ‘730) would be disposed over the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730).
With respect to Claim 11 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, and Chen ‘730 as modified by Chung ‘497 further discloses
wherein the first CESL (1802 on leftmost 1602) and the second CESL (2202) comprise silicon nitride or silicon oxynitride (Para [0060] of Chen ‘730 discloses 2202 comprises silicon nitride or silicon oxynitride),
wherein the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) comprise silicon nitride (Para [0041] of Chung ‘497 discloses 242 as silicon nitride),
wherein the first dielectric layer (1902 on leftmost 1602) and the second dielectric layer (1902 on rightmost 1602) comprise silicon oxide (Para [0056] of Chen ’730 discloses 1902 as the same material as layer 402 and Para [0036] discloses 402 as silicon oxide).
And Chung ‘497 further discloses wherein the first CESL (leftmost 230) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 is silicon nitride or silicon oxynitride).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s further teaching of a CESL comprises silicon nitride or silicon oxynitride into Chen ‘730’s device. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because Chung ‘497 is open to the composition of the CESL and Chen ‘730 teaches a well-known material to act as an etch to achieve the well-known advantage of protecting layers of a device during etch process steps.
As incorporated, the teaching of silicon nitride or silicon oxynitride as a contact etch stop layer of Chung ‘497 would be used as the material of the first CESL (1802 on leftmost 1602) of Chen ‘730 as modified by Chung ‘497.
With respect to Claim 12 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor structure of claim 11, and Chen ‘730 as modified by Chung ‘497 further discloses wherein the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) is in contact with (as incorporated, leftmost 242 of Chung ‘497 is on and in contact with the first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602) of Chen ‘730 therefore it is in contact with top surfaces of first CESL and first dielectric layer)
top surfaces of the first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602).
With respect to Claim 13 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, and Chung ‘730 further teaches wherein the first source/drain feature (leftmost 1602) partially extends into the substrate (101)(Fig 16A discloses 1602 is below the top level of 101 as it is below the top level of 402 which is shown in Fig 14 to be at the top level of substrate 101).
With respect to Claim 21 Chen ‘730 discloses a semiconductor device (Fig 1-27), comprising:
a substrate (101, Fig 21B, Para [0023]);
a lower source/drain feature (leftmost 1602, Fig 21A, Para [0057]) disposed over the substrate (101);
bottom nanostructures (106b, Fig 21B, Para [0063] discloses 106b as nanostructures) disposed over the substrate (101) and interfacing (disclosed in Fig 21B) the lower source/drain feature (leftmost 1602, Fig 21A, Para [0057]);
bottom inner spacer features (1504 on 104b/1504 on 2502 after 104b removal, Fig 15, Para [0051 and 0052 and 0063-0065]) interleaving (disclosed in Fig 21B and Para [0051]) the bottom nanostructures (106b);
a first channel layer (lowermost 106c, Fig 21B, Para [0066]) over (disclosed in Fig 21B) the bottom nanostructures (106b) and the bottom inner spacer features (1504 on 104b);
a second channel layer (uppermost 106c, Fig 21B, Para [0066]) over (disclosed in Fig 21B) the first channel layer (lowermost 106c);
a first gate structure (2502, Fig 25, Para [0065]) wrapping (disclosed in Fig 25) each of the bottom nanostructures (106b) and spaced apart (Fig 24-25 and Para [0063-0065] disclose 104b removed and replaced with 2502, therefore the inner spacers 1504 will exist on 2502 and space apart 106b from leftmost 1602) from the lower source/drain feature (leftmost 1602) by the bottom inner spacer features (1504 on 104b, as described above 1504 on 2502 after 104b removal);
a first contact etch stop layer (CESL) (1802 on leftmost 1602, Fig 21B, Para [0055]) and a first dielectric layer (1902 on leftmost 1602, Fig 21B, Para [0056]) over (disclosed in Fig 21B) the lower source/drain feature (leftmost 1602);
an upper source/drain feature (leftmost 2102, Fig 21B, Para [0058]);
top nanostructures (106d, Fig 21B of Chen ‘730, Para [0058]) disposed over (disclosed in Fig 21B) the second channel layer (uppermost 106c) and interfacing (disclosed in Fig 21B) the upper source/drain feature (leftmost 2102);
top inner spacer features (1504 on 104d/1504 on 2702 after 104d removal, Fig 15, Para [0051 and 0052, 0063-0064 and 0067]) interleaving (disclosed in Fig 21B and Para [0051]) the top nanostructures (106d);
a second gate structure (2702, Fig 27, Para [0067]) wrapping around (disclosed in Fig 27) each of the top nanostructures (106d) and spaced apart (Fig 24-25 and Para [0063-0064 and 0067] disclose 104d removed and replaced with 2702, therefore the inner spacers 1504 will exist on 2702 and space apart 106d from leftmost 2102) from the upper source/drain feature (leftmost 2102) by the top inner spacer features (1504 on 104d, as described above 1504 on 2702 after 104d removal); and
a second CESL (2202, Fig 22, Para [0060]) and a second dielectric layer (2204, Fig 22, Para [0060]) over the upper source/drain feature (leftmost 2102),
wherein the first CESL (1802 on leftmost 1602) interfaces sidewalls (Fig 21B discloses first CESL interfaces sidewalls of lowermost 106c and uppermost 106c) of the first channel layer (lowermost 106c) and the second channel layer (uppermost 106c),
But Chen ‘730 fails to explicitly disclose an etch stop layer (ESL) over and in contact with the first CESL and the first dielectric layer.
Nevertheless, in a related endeavor (Fig 1-16C of Chung ‘497), Chung ‘497 teaches a first etch stop layer (ESL) (leftmost 242, Fig 12A of Chung ‘497, Para [0041]) over and in contact with (Fig 12A of Chung ‘497 discloses leftmost 242 over and in contact with 230 and 232) first CESL (leftmost 230, Fig 11A of Chung ‘497, Para [0039]) and the first dielectric layer (leftmost 232, Fig 11A of Chung ‘497, Para [0039]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s teaching of an etch stop layer (ESL) over and in contact with the first CESL and the first dielectric layer into Chen ‘730’s device. Chen ‘730 discloses a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer. Chung ‘497 also teaches a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer and further teaches an etch stop layer over the top of the contact etch stop layer and dielectric layer. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because this additional etch stop layer can provide additional protection to the dielectric layer during etching steps to remove sacrificial layers as the upper gate features are formed and it will act as an additional dielectric layer to reduce parasitic capacitance in the device.
As incorporated, the teaching of a first etch stop layer (leftmost 242) of Chung ‘497 would be used over and in contact with the first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602) of Chen ‘730 so that first upper source/drain feature (leftmost 2102 of Chen ‘730) would be over the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730).
Further, as ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) is over and in contact with first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602), Chen ‘730 as modified by Chung ;497 discloses wherein the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) interfaces at least one of the top inner spacer features (1504 on 104d/1504 on 2702 after 104d removal)(Fig 21B discloses the top of 1802 and 1902 interface one of 1504 on 104d/1504 on 2702 after 104d removal, as incorporated ESL leftmost 242 of Chung ‘497 as incorporated in Chen ‘730 would interface with one 1504 on 104d/1504 on 2702 after 104d removal).
With respect to Claim 22 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chen ‘730 as modified by Chung ‘497 further discloses
wherein the first CESL (1802 on leftmost 1602) and the second CESL (2202) comprise silicon nitride or silicon oxynitride (Para [0060] of Chen ‘730 discloses 2202 comprises silicon nitride or silicon oxynitride),
wherein the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) comprise silicon nitride (Para [0041] of Chung ‘497 discloses 242 as silicon nitride),
wherein the first dielectric layer (1902 on leftmost 1602) and the second dielectric layer (1902 on rightmost 1602) comprise silicon oxide (Para [0056] of Chen ’730 discloses 1902 as the same material as layer 402 and Para [0036] discloses 402 as silicon oxide).
And Chung ‘497 further discloses wherein the first CESL (leftmost 230) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 is silicon nitride or silicon oxynitride).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s further teaching of a CESL comprises silicon nitride or silicon oxynitride into Chen ‘730’s device. The ordinary artisan would have been motivated to modify Chen ‘730 in the manner set forth above, at least, because Chung ‘497 is open to the composition of the CESL and Chen ‘730 teaches a well-known material to act as an etch to achieve the well-known advantage of protecting layers of a device during etch process steps.
As incorporated, the teaching of silicon nitride or silicon oxynitride as a contact etch stop layer of Chung ‘497 would be used as the material of the first CESL (1802 on leftmost 1602) of Chen ‘730 as modified by Chung ‘497.
With respect to Claim 23 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chen ‘730 further discloses
wherein the first source/drain feature (leftmost 1602) comprises silicon and an n-type dopant (Para [0053] discloses 1602 as n-type and comprising Si),
wherein the second source/drain feature (leftmost 2102) comprises silicon germanium and a p- type dopant (Para [0058] discloses leftmost 2102 as p-type and comprising SiGe).
With respect to Claim 24 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chen ‘730 as modified by Chung ‘497 discloses wherein the ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) is in contact with top surfaces of the first CESL and the first dielectric layer (as described above, relative to the layout shown in Fig 21B of Chen ‘730, ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) is over and in contact with first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602), therefore ESL (leftmost 242 of Chung ‘497 as incorporated in Chen ‘730) is in contact with top surfaces of the first CESL (1802 on leftmost 1602) and the first dielectric layer (1902 on leftmost 1602).
With respect to Claim 25 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chen ‘730 discloses further comprising:
a middle dielectric layer (2602/1504, Fig 27, Para [Para 0063 and 0066] discloses dielectric spacers 1504 with dielectric layer 2602 formed between, 2602/1504 hereinafter MDL) disposed between (MDL disposed between 106b and 106d disclosed in Fig 26) the bottom nanostructures (106b) and the top nanostructures (106d),
wherein the middle dielectric layer (MDL) interfaces the first CESL (1802 on leftmost 1602) (Fig 21B and Para [0057] disclose liner leftmost 1802 in contact with layer 104c/1504, 104c which is replaced with dielectric layer 2602, as disclosed in Para [0066] which would then have leftmost 1802 interface with MDL (1504/2602)).
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘730 in view of Chung ‘497 and in further view of Lee et al. (US 2020/0111714 A1, hereinafter Lee ‘714), in view of the following arguments.
With respect to Claim 6 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chen ‘730 further discloses
wherein the first upper source/drain feature (leftmost 2102) and the second upper source/drain feature (rightmost 2102) comprise silicon germanium and a p-type dopant (Para [0058] disclose leftmost and rightmost 2102 as PFET including SiGe),
wherein each of the first upper source/drain feature (leftmost 2102) and the second upper source/drain feature (rightmost 2102)
But Chen ‘730 as modified by Chung ‘497 fails to explicitly disclose comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces of the first upper source/drain feature and the second upper source/drain feature.
Nevertheless, in a related endeavor (Fig 7 of Lee ‘714), Lee ‘714 teaches wherein each of the first upper source/drain feature (left 181/141, Fig 7 of Lee ‘714, Para [0073]) and the second upper source/drain (right 181/182/141, Fig 7 of Lee ‘714, Para [0073]) feature comprises a concentration gradient of germanium (Para [0046] discloses process of Lee ‘714 produces a Si/Ge gradient and Para [0073] discloses Ge concentration in top layer 181 is greater than 141) with a greatest germanium concentration adjacent surfaces (181, Fig 7 of Lee ‘714, Para [0073]) of the first upper source/drain feature (left 181/182/141) and the second upper source/drain feature (right 181/182/141)(Para [0073] disclose that in the annealing process of 141 Ge concentration in formed layers 181 is increased by up to 20%).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘714’s teaching of wherein each of the first upper source/drain feature and the second upper source/drain feature comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces of the first upper source/drain feature and the second upper source/drain feature into Chen ‘730 as modified by Chung ‘497’s device. Chen ‘730 as modified by Chung ‘497 teaches upper doped source/drain regions of SiGe but does not provide details on the doping concentrations. Lee ‘714 also teaches doped source/drain regions of SiGe and teaches doping concentrations for those regions. The ordinary artisan would have been motivated then, to modify Chen ‘730 as modified by Chung ‘497 in the manner set forth above, at least, firstly, because it teaches the concentration details to create a functional device which would save R&D costs and secondly they would have been motivated because as Lee ‘714 teaches in Para [0045] having a Ge rich surface in a source/drain region lowers the contact resistivity which results in improvement of device performance.
As incorporated, the teaching of Lee ‘714 of the first and second upper source/drain feature (181/141 of Lee ‘714) and comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces (181 of Lee ‘714) of the first and second upper source/drain feature (181/141 of Lee ‘714) would be used in the first and second upper source/drain features (leftmost 2102 and rightmost 2012 respectively) Chen ‘730 as modified by of Chung ‘497.
With respect to Claim 7 Chen ‘730 as modified by Chung ‘497 and further modified by Lee ‘714 discloses all limitations of the semiconductor device of claim 6, and Lee ‘714 further teaches wherein the p-type dopant comprises boron (B) (Para 0062] discloses the p-type dopant used in doping source/drain regions comprises boron).
With respect to Claim 14 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, but Chen ‘730 as modified by Chung ‘497 fails to explicitly disclose
wherein the second source/drain feature comprises a surface germanium-rich layer,
wherein a germanium content of the surface germanium-rich layer is greater than a germanium content of a rest of the second source/drain feature.
Nevertheless, in a related endeavor (Fig 7 of Lee ‘714), Lee ‘714 teaches wherein the second source/drain feature (141, Fig 7 of Lee ‘714, Para [0073]) comprises a surface germanium-rich layer (Para [0073] of Lee ‘714 discloses the surface of the source/drain structure has a higher germanium concentration (20% higher) than the rest of the structure), wherein a germanium content (Ge content in 181, Para [0073]) of the surface germanium-rich layer (181, Fig 7 of Lee ‘714, Para [0073]) is greater than a germanium content (Ge content in 141, Para [0073]) of a rest of the second source/drain feature (141, Fig 7 of Lee ‘714, Para [0073]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘714’s teaching of wherein the second source/drain feature comprises a surface germanium-rich layer; a germanium content of the surface germanium-rich layer is greater than a germanium content of a rest of the second source/drain feature into Chen ‘730 as modified by Chung ‘497’s device. Chen ‘730 as modified by Chung ‘497 teaches upper doped source/drain regions of SiGe but does not provide details on the doping concentrations. Lee ‘714 also teaches doped source/drain regions of SiGe and teaches doping concentrations for those regions. The ordinary artisan would have been motivated then, to modify Chen ‘730 as modified by Chung ‘497 in the manner set forth above, at least, firstly, because it teaches the concentration details to create a functional device which would save R&D costs and secondly they would have been motivated because as Lee ‘714 teaches in Para [0045] having a Ge rich surface in a source/drain region lowers the contact resistivity which results in improvement of device performance.
As incorporated, the teaching of Lee ‘714 of a germanium content of the surface germanium-rich layer (181) is greater than a germanium content of a rest of the second source/drain feature (141) would be used in the surfaces of second upper source/drain features (leftmost 2102) of Chen ‘730 as modified by Chung ‘497.
With respect to Claim 15 Chen ‘730 as modified by Chung ‘497 and further modified by Lee ‘714 discloses all limitations of the semiconductor structure of claim 14, and Lee ‘714 further discloses wherein the germanium content (Ge content in 181 of Lee ‘714 as incorporated into Chung ‘497 as above) of the surface germanium-rich layer (181 of Lee ‘714 as incorporated into Chung ‘497 as above) is between about 40% and about 100% (Para [0073] discloses source/drain region 141 of Lee ‘714 has a Ge content of 50% Ge and that the surface region has a Ge concentration 20% higher than 141, therefore the Ge concentration of surface of 181 of Lee ‘714 as incorporated in Chung ‘497 (as described above) has a Ge concentration between 40% and 100%).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘730 in view of Chung ‘497 and in further view of Li et al. (US 2019/0214487 A1, hereinafter Li ‘487), in view of the following arguments.
With respect to Claim 8 Chen ‘730 as modified by Chung ‘497 discloses all limitations of the semiconductor device of claim 1, but Chen ‘730 as modified by Chung ‘497 fails to explicitly disclose
wherein the first lower source/drain feature comprises silicon germanium and a p-type dopant,
wherein the second lower source/drain feature comprise silicon and an n-type dopant.
Nevertheless, in a related endeavor (Fig 1-13B of Li ‘487), Li ‘487 teaches wherein the first lower source/drain feature (115, Fig 13A of Li ‘487, Para [0043]) comprises silicon germanium and a p-type dopant (Para [0043] of Li ‘487 discloses 115 as SiGe and is p type),
wherein the second lower source/drain feature (160, Fig 13A of Li ‘487, Para [0056]) comprise silicon and an n-type dopant (Para [0056] discloses 160 as comprising Si (SiC) and is n type).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Li ‘487’s teaching of wherein the first lower source/drain feature comprises silicon germanium and a p-type dopant, wherein the second lower source/drain feature comprise silicon and an n-type dopant into Chen ‘730 as modified by Chung ‘497’s device. Chen ‘730 as modified by Chung ‘497 discloses a semiconductor device with source/drain features for multi-gates and discloses a dielectric layer with a contact etch stop layer around the dielectric layer. Further Chen ‘730 as modified by Chung ‘497 is open to the materials and dopant types of the source and drain structures. The ordinary artisan would have been motivated to modify Chen ‘730 as modified by Chung ‘497 in the manner set forth above, at least, because as Li ‘487 teaches in Para [0001, 0043 and 0056] that in a transistor by using a source or drain region of SiGe with a p-type and the other source or drain comprising silicon and being n type, a band-to-band tunneling (BTBT) mechanism can be created which can improve performance in a low power device as it has a steep subthreshold swing and weak temperature dependence.
As incorporated, the teaching of a Li ‘487 of first lower source/drain feature (115) comprises silicon germanium and a p-type dopant and the second lower source/drain feature (160) comprise silicon and an n-type dopant would be used as the material and dopants of first lower source/drain feature (leftmost 1602) and the second lower source/drain feature (rightmost 1602) in the device of Chen ‘730 as modified by Chung ‘497.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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