DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/16/2025.
Applicant’s election without traverse of Invention I, Device Embodiment 1 in the reply filed on 10/16/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8, 10-13 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US 2022/0037497 A1, hereinafter Chung ‘497).
With respect to Claim 1 Chung ‘497 discloses a semiconductor device (Fig 1-16C), comprising:
a substrate (202, Fig 2A, Para [0026]);
a first lower source/drain feature (228S, Fig 10A, Para [0038]) and a second lower source/drain feature (228D, Fig 10A, Para [0038]) disposed over the substrate (202);
a first plurality of nanostructures (206 in stack 204a, Fig 10A, Para [0029]) extending between the first lower source/drain feature (228S) and the second lower source/drain feature (228D);
a first gate structure (254 in stack 204a, Fig 16A, Para [0046]) wrapping around each (254 wrapping around each layer of 206 in stack 204a disclosed in Para [0046]) of the first plurality of nanostructures (206 in stack 204a);
a first contact etch stop layer (CESL) (leftmost 230, Fig 11A, Para [0039]) and a first dielectric layer (leftmost 232, Fig 11A, Para [0039]) over the first lower source/drain feature (228S);
a first etch stop layer (ESL) (leftmost 242, Fig 12A, Para [0041]) over and in contact with (Fig 12A discloses leftmost 242 over and in contact with 230 and 232) the first CESL (leftmost 230) and the first dielectric layer (leftmost 232);
a second CESL) (rightmost 230, Fig 11A, Para [0039]) and a second dielectric layer (rightmost 232, Fig 11A, Para [0039]) over the second lower source/drain feature (228D);
a second ESL (rightmost 242, Fig 12A, Para [0041]) over and in contact with (Fig 12A discloses rightmost 242 over and in contact with 230 and 232) the second CESL (rightmost 230) and the second dielectric layer (rightmost 232);
a first upper source/drain feature (248S, Fig 13A, Para [0042]) over the first ESL (leftmost 242)(shown in Fig 13A);
a second upper source/drain feature (248D, Fig 13A, Para [0042]) over the second ESL (rightmost 242);
a second plurality of nanostructures (206 in stack 204b, Fig 10A, Para [0027]) extending between the first upper source/drain feature (248S) and the second upper source/drain feature (248D); and
a second gate structure (254 in stack 204b, Fig 16A, Para [0046]) wrapping around each (254 wrapping around each layer of 206 in stack 204b disclosed in Para [0046]) of the second plurality of nanostructures (206 in stack 204b).
With respect to Claim 2 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses wherein the first CESL (leftmost 230) and the second CESL (rightmost 230) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 is silicon nitride or silicon oxynitride).
With respect to Claim 3 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses
wherein the first ESL (leftmost 242) and the second ESL (rightmost 242) comprise silicon nitride (Para [0041] discloses 242 as silicon nitride),
wherein the first dielectric layer (leftmost 232) and the second dielectric layer (rightmost 232) comprise silicon oxide (Para [0039] discloses 232 comprises silicon oxide).
With respect to Claim 4 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses wherein the first gate structure (254 in stack 204a) and the second gate structure (254 in stack 204b) are vertically spaced apart from one another (shown in Fig 14A) by a middle dielectric layer (206M and 226 adjacent to 206M, Fig 14A, Para [0027 and 0035], hereinafter MDL)(Fig 14A discloses MDL separates first and second gate structure).
With respect to Claim 5 Chung ‘497 discloses all limitations of the semiconductor device of claim 4, and Chung ‘497 further discloses wherein a sidewall of the middle dielectric layer (sidewall of MDL) is in contact with the first CESL (leftmost 230)(Fig 14A discloses sidewall of MDL is in contact with leftmost 230).
With respect to Claim 8 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses
wherein the first lower source/drain feature (228S) comprises silicon germanium and a p-type dopant (Para [0038] discloses 228S as comprises silicon germanium and a p-type dopant),
wherein the second lower source/drain feature (228D) comprise silicon and an n-type dopant (Para [0038] discloses 228D as comprises silicon and a n-type dopant).
With respect to Claim 10 Chung ‘497 discloses a semiconductor structure (Fig 1-16C), comprising:
a substrate (202, Fig 2A, Para [0026]);
a first source/drain feature (228S/228D, Fig 10A, Para [0038]) disposed on the substrate (202);
a first contact etch stop layer (CESL) (230, Fig 11A, Para [0039]) disposed on the first source/drain feature (228S/228D);
a first dielectric layer (232, Fig 11A, Para [0039]) disposed over the first CESL (230) and spaced apart from (Fig 11A-11C disclose 232 spaced apart from 228S/228D by 230) the first source/drain feature (228S/228D);
an etch stop layer (ESL) (242, Fig 12A, Para [0041]) disposed on and in contact with (Fig 12A-12C discloses 242 disposed on and in contact with leftmost 230) the first CESL (230) and the first dielectric layer (232);
a second source/drain feature (248S/248D, Fig 13A, Para [0042]) disposed over the ESL (242);
a second (CESL) (250, Fig 14A, Para [0044]) disposed on the second source/drain feature (248S/248D); and
a second dielectric layer (252, Fig 14A, Para [0044]) disposed over the second CESL (250) and spaced apart from (Fig 14A-14C discloses 252 over 250 and 248S/248D) the second source/drain feature (248S/248D),
wherein the first source/drain feature (228S/228D) comprises silicon and an n-type dopant (Para [0038] discloses 228S/228D as silicon and n-type dopant),
wherein the second source/drain feature (248S/248D) comprises silicon germanium and a p- type dopant (Para [0042] discloses 248S/248D as silicon germanium and p-type dopant).
With respect to Claim 11 Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, and Chung ‘497 further discloses
wherein the first CESL (230) and the second CESL (250) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 comprises silicon nitride or silicon oxynitride and Para [0044] discloses 250 comprises silicon nitride or silicon oxynitride),
wherein the ESL (242) comprise silicon nitride (Para [0041] discloses 242 comprises silicon nitride),
wherein the first dielectric layer (232) and the second dielectric layer (252) comprise silicon oxide (Para [0039] discloses 232 comprises silicon oxide and Para [0044] discloses 252 comprises silicon oxide).
With respect to Claim 12 Chung ‘497 discloses all limitations of the semiconductor structure of claim 11, wherein the ESL (242) is in contact with top surfaces (top of 230) of the first CESL (230) and the first dielectric layer (232)(Fig 14A-14C disclose 242 in contact with top of 230 and top of 232).
With respect to Claim 13 Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, and Chung ‘497 further discloses wherein the first source/drain feature (228S/228D) partially extends into the substrate (202)(Fig 14A discloses 228S/228D extends into substrate 202).
With respect to Claim 21 Chung ‘497 discloses a semiconductor device (Fig 1-16C), comprising:
a substrate (202, Fig 2A, Para [0026]);
a lower source/drain feature (228S/228D, Fig 10A, Para [0038]) disposed over the substrate (202);
bottom nanostructures (206 in stack 204a, Fig 10A, Para [0029]) disposed over the substrate (206 in stack 204a, Fig 10A, Para [0029])(202) and interfacing the lower source/drain feature (228S/228D)(Fig 10A discloses 206 interfacing with 228S/228D);
bottom inner spacer features (208 in stack 204a, Fig 10A, Para [0027]) interleaving the bottom nanostructures (206 in stack 204a)(Fig 10A discloses 208 interleaving the layers 206);
a first gate structure (254 in stack 204a, Fig 16A, Para [0046]) wrapping around each of the bottom nanostructures (206 in stack 204a) and spaced apart from the lower source/drain feature (228S/228D) by the bottom inner spacer features (208 in stack 204a)(Fig 15A discloses above orientation);
a first contact etch stop layer (CESL) (230, Fig 11A, Para [0039]) and a first dielectric layer (232, Fig 11A, Para [0039]) over the lower source/drain feature (228S/228D)(Fig 11A-11C discloses orientation above);
an etch stop layer (ESL) (242, Fig 12A, Para [0041]) over and in contact with the first CESL (230) and the first dielectric layer (232)(Fig 12A-12C discloses orientation above);
an upper source/drain feature (248S/248D, Fig 13A, Para [0042]) over the ESL (242);
top nanostructures (206 in stack 204b, Fig 10A, Para [0027]) disposed over the bottom nanostructures (206 in stack 204a) and interfacing the upper source/drain feature (248S/248D)(Fig 13A-C discloses orientation above);
top inner spacer features (208 in stack 204b, Fig 10A, Para [0027]) interleaving the top nanostructures (206 in stack 204b)(Fig 13A discloses above orientation);
a second gate structure (254 in stack 204b, Fig 16A, Para [0046]) wrapping around each of the top nanostructures (206 in stack 204b) and spaced apart from the upper source/drain feature (248S/248D) by the top inner spacer features (208 in stack 204b)(Fig 15A discloses above orientation); and
a second CESL (250, Fig 14A, Para [0044]) and a second dielectric layer (252, Fig 14A, Para [0044]) over the upper source/drain feature (248S/248D)(Fig 15A-C discloses above orientation),
wherein the ESL (242) interfaces at least one of the top inner spacer features (208 in stack 204b)(Fig 15A discloses 242 interfaces with bottom layer 208 in stack 204b).
With respect to Claim 22 Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chung ‘497 further discloses
wherein the first CESL (230) and the second CESL (250) comprise silicon nitride or silicon oxynitride (Para [0039] discloses 230 comprises silicon nitride or silicon oxynitride and Para [0044] discloses 250 comprises silicon nitride or silicon oxynitride),
wherein the ESL (242) comprise silicon nitride (Para [0041] discloses 242 comprises silicon nitride),
wherein the first dielectric layer (232) and the second dielectric layer (252) comprise silicon oxide (Para [0039] discloses 232 comprises silicon oxide and Para [0044] discloses 252 comprises silicon oxide).
With respect to Claim 23 Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chung ‘497 further discloses
wherein the lower source/drain feature (228S/228D) comprises silicon and an n-type dopant (Para [0038] discloses 228S/228D as comprises silicon and a n-type dopant),
wherein the upper source/drain feature (248S/248D) comprises silicon germanium and a p-type dopant (Para [0042] discloses 248S/248D as silicon germanium and p-type dopant).
With respect to Claim 24 Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chung ‘497 further discloses wherein the ESL (242) is in contact with top surfaces of the first CESL (230) and the first dielectric layer (232) (Fig 14A-14C disclose 242 in contact with top of 230 and top of 232).
With respect to Claim 25 Chung ‘497 discloses all limitations of the semiconductor device of claim 21, and Chung ‘497 further discloses further comprising:
a middle dielectric layer (206M and 226 adjacent to 206M, Fig 14A, Para [0027 and 0035], hereinafter MDL) disposed between the bottom nanostructures (206 in stack 204a) and the top nanostructures (206 in stack 204b)(orientation of MDL disposed between top and bottom nanostructures disclosed in Fig 14A),
wherein the middle dielectric layer (MDL) interfaces the first CESL (230)(Fig 14A discloses MDL interfaces with 230).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung ‘497 in view of Lee et al. (US 2020/0111714 A1, hereinafter Lee ‘714), in view of the following arguments.
With respect to Claim 6 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses
wherein the first upper source/drain feature (248S) and the second upper source/drain feature (248D) comprise silicon germanium and a p-type dopant (Para [0042] discloses 248S and 248D as silicon germanium and p-type dopant),
But Chung ‘497 fails to explicitly disclose wherein each of the first upper source/drain feature and the second upper source/drain feature comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces of the first upper source/drain feature and the second upper source/drain feature.
Nevertheless, in a related endeavor (Fig 7 of Lee ‘714), Lee ‘714 teaches wherein each of the first upper source/drain feature (left 181/141, Fig 7 of Lee ‘714, Para [0073]) and the second upper source/drain (right 181/182/141, Fig 7 of Lee ‘714, Para [0073]) feature comprises a concentration gradient of germanium (Para [0046] discloses process of Lee ‘714 produces a Si/Ge gradient and Para [0073] discloses Ge concentration in top layer 181 is greater than 141) with a greatest germanium concentration adjacent surfaces (181, Fig 7 of Lee ‘714, Para [0073]) of the first upper source/drain feature (left 181/182/141) and the second upper source/drain feature (right 181/182/141)(Para [0073] disclose that in the annealing process of 141 Ge concentration in formed layers 181 is increased by up to 20%).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘714’s teaching of wherein each of the first upper source/drain feature and the second upper source/drain feature comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces of the first upper source/drain feature and the second upper source/drain feature into Chung ‘497’s device. Chung ‘497 teaches upper doped source/drain regions of SiGe but does not provide details on the doping concentrations. Lee ‘714 also teaches doped source/drain regions of SiGe and teaches doping concentrations for those regions. The ordinary artisan would have been motivated then, to modify Chung ‘497 in the manner set forth above, at least, firstly, because it teaches the concentration details to create a functional device which would save R&D costs and secondly they would have been motivated because as Lee ‘714 teaches in Para [0045] having a Ge rich surface in a source/drain region lowers the contact resistivity which results in improvement of device performance.
As incorporated, the teaching of Lee ‘714 of the first and second upper source/drain feature (181/141 of Lee ‘714) and comprises a concentration gradient of germanium with a greatest germanium concentration adjacent surfaces (181 of Lee ‘714) of the first and second upper source/drain feature (181/141 of Lee ‘714) would be used in the first and second upper source/drain features (248S/248D) of Chung ‘497.
With respect to Claim 7 Chung ‘497 as modified by Lee ‘714 discloses all limitations of the semiconductor device of claim 6, and Chung ‘497 further discloses wherein the p-type dopant comprises boron (B) (Para [0042] discloses p-type dopant comprises boron).
With respect to Claim 14 Chung ‘497 discloses all limitations of the semiconductor structure of claim 10, and Chung ‘497 further discloses
wherein the second source/drain feature (248S/248D) comprises a surface germanium-rich layer (Para [0042] discloses 248S and 248D as silicon germanium),
But Chung ‘497 fails to explicitly disclose wherein a germanium content of the surface germanium-rich layer is greater than a germanium content of a rest of the second source/drain feature.
Nevertheless, in a related endeavor (Fig 7 of Lee ‘714), Lee ‘714 teaches wherein a germanium content (Ge content in 181, Para [0073]) of the surface germanium-rich layer (181, Fig 7 of Lee ‘714, Para [0073]) is greater than a germanium content (Ge content in 141, Para [0073]) of a rest of the second source/drain feature (141, Fig 7 of Lee ‘714, Para [0073]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘714’s teaching of wherein a germanium content of the surface germanium-rich layer is greater than a germanium content of a rest of the second source/drain feature into Chung ‘497’s device. Chung ‘497 teaches upper doped source/drain regions of SiGe but does not provide details on the doping concentrations. Lee ‘714 also teaches doped source/drain regions of SiGe and teaches doping concentrations for those regions. The ordinary artisan would have been motivated then, to modify Chung ‘497 in the manner set forth above, at least, firstly, because it teaches the concentration details to create a functional device which would save R&D costs and secondly they would have been motivated because as Lee ‘714 teaches in Para [0045] having a Ge rich surface in a source/drain region lowers the contact resistivity which results in improvement of device performance.
As incorporated, the teaching of Lee ‘714 of a germanium content of the surface germanium-rich layer (181) is greater than a germanium content of a rest of the second source/drain feature (141) would be used in the surfaces of first and second upper source/drain features (248S/248D) of Chung ‘497.
With respect to Claim 15 Chung ‘497 discloses all limitations of the semiconductor structure of claim 14, and Lee ‘714 further discloses wherein the germanium content (Ge content in 181 of Lee ‘714 as incorporated into Chung ‘497 as above) of the surface germanium-rich layer (181 of Lee ‘714 as incorporated into Chung ‘497 as above) is between about 40% and about 100% (Para [0073] discloses source/drain region 141 of Lee ‘714 has a Ge content of 50% Ge and that the surface region has a Ge concentration 20% higher than 141, therefore the Ge concentration of surface of 181 of Lee ‘714 as incorporated in Chung ‘497 (as described above) has a Ge concentration between 40% and 100%).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chung ‘497, in view of the following arguments.
With respect to Claim 9 Chung ‘497 discloses all limitations of the semiconductor device of claim 1, and Chung ‘497 further discloses
wherein the first plurality of nanostructures (206 in stack 204a) are interleaved by a first plurality of inner spacer features (208 in stack 204a, Fig 10A, Para [0027]),
wherein the second plurality of nanostructures (206 in stack 204b) are interleaved by a second plurality of inner spacer features (208 in stack 204b, Fig 10A, Para [0027]),
wherein the first ESL (leftmost 242) is in contact with at least one of the second plurality of inner spacer features (208 in stack 204b) (Fig 15A discloses 242 is in contact with inner spacer feature 208 in stack 204b).
But Chung ‘497 fails to explicitly disclose wherein the first CESL is in contact with at least one of the first plurality of inner spacer features,
Nevertheless, in a related embodiment (Fig 66A-66C of Chung ‘497), Chung ‘497 teaches wherein the first CESL (leftmost 230) is in contact with at least one of the first plurality of inner spacer features (top 208 in stack 204a)(Fig 66A discloses leftmost 230 is in contact with top spacer 208 in stack 204a),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘497’s further teaching of wherein the first CESL is in contact with at least one of the first plurality of inner spacer features into Chung ‘497’s device. In the further embodiment of Chung ‘497, Chung ‘497 teaches an additional orientation for the first CESL. The ordinary artisan would have been motivated to modify Chung ‘497 to modify the first CESL in the manner set forth above, at least, because forming the first CESL to contact the top inner spacer 208 in stack 204a would provide and additional layer of dielectric protection between the upper and lower transistor structures of Chang ‘497 which could reduce potential current leakage.
As incorporated, the first CESL (leftmost 230) in contact with top layer of the first plurality of inner spacer features (208) as taught in the further embodiment of Chung ‘497 would be used as the structure for the first CESL of Chung ‘497.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898