DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of claims 1-16 and newly added claims 21-24 in the reply filed on 11/05/25 is acknowledged. By this election, claims 17-20 are cancelled; and claims 1-16 and 21-24 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7 and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamura et al. (2015/0270391).
Regarding claim 1, Tamura (Fig. 7B) discloses an integrated circuit (IC) structure 700, comprising: a semiconductor substrate 112 ([0007]); an isolation structure 116 formed in the semiconductor substrate 112, thereby defining active regions surrounded by the isolation structure feature 116 ([0010]); a first well 140 of a first conductivity type (N- type) formed in the semiconductor substrate 112 ([0008]); a neutral region 314 formed in the semiconductor substrate 112 and laterally surrounding the first well 140 ([0039]); a second well 146 of a second conductivity type (P- type) formed on the semiconductor substrate 112 and laterally surrounding the neutral region 314, the second conductivity type (P- type) being opposite to the first conductivity type (N- type); a source 150 disposed on the second well 146 of the semiconductor substrate 112 ([0009]); a drain 142 disposed on the first well 140 of the semiconductor substrate 112 ([0008]); and a gate structure 162 interposed between the source 150 and the drain 142, the gate structure 162 engaging the first well 140, the neutral region 314 and the second well 146 of the semiconductor substrate 112 ([0011]), wherein the source 150, the drain 142 and the gate structure 162 are configured as a first field-effect transistor (FET) (Fig. 7B, [0005]).
Regarding claim 2, Tamura (Fig. 7B) discloses wherein the isolation structure feature 116 is a shallow trench isolation (STI) feature that includes a portion formed in the first well 140 and disposed between the source 150 and the drain 142 ([0007]).
Regarding claim 6, Tamura (Fig. 7B) discloses further comprising a deep well 322 of the second conductivity type (P-type), wherein the source 150 and the drain 142 are doped features of the first conductivity type (N-type), and the first well 140 and the second well 146 are disposed on the deep well 322 and are overlapped with the deep well 322 in a top view.
Regarding claim 7, Tamura (Fig. 7B) discloses wherein the active regions include planar active regions and fin active regions.
Regarding claim 11, Tamura (Fig. 7B) discloses wherein the gate structure is a first gate structure 162, and the source 150 is a first source, wherein the IC structure further includes a second source 150 disposed in the second well 146 of the semiconductor substrate 112; and a second gate structure 162 interposed between the second source 150 and the drain 142, the gate structure 162 engaging the first well 140, the neutral region 314 and the second well 146 of the semiconductor substrate 112, wherein the second source 150, the drain 142 and the second gate structure 162 are configured as a second FET (Fig. 7B, [0005]).
Regarding claim 12, Tamura (Fig. 7B) discloses an integrated circuit (IC) structure, comprising: a semiconductor substrate 112 ([0007]); a shallow trench isolation (STI) feature 116 formed in the semiconductor substrate 112 ([0010]), thereby defining active regions 114 surrounded by the STI feature 116; a first well 140 of a first conductivity type (N- type) disposed on the semiconductor substrate 112 ([0008]); a neutral region 314 disposed on the semiconductor substrate 112 and laterally surrounding the first well 140 ([0039]); a second well 146 of a second conductivity type (P- type) disposed on the semiconductor substrate 112 and laterally surrounding the neutral region 314, the second conductivity type (P- type) being opposite to the first conductivity type (N-type); and a first field-effect transistor (FET) and a second FET 162 formed on the semiconductor substrate 112 ([0011]), wherein the first FET 162 includes a first source 150 disposed on the second well 146, a drain 142 disposed on the first well 140, and a first gate structure 162 interposed between the first source 150 and the drain 142, the first gate structure 162 landing on the first well 140, the neutral region 314 and the second well 146, and the second FET 162 includes a second source 150 disposed on the second well 146, the drain 142, and a second gate structure 162 interposed between the second source 150 and the drain 142, the second gate structure 162 landing on the first well 140, the neutral region 314 and the second well 146 (see Fig. 7B).
Regarding claim 13, Tamura (Fig. 7B) discloses wherein the STI feature 116 further includes a first portion formed in the first well 140 and disposed between the first source 150 and the drain 142, and a second portion formed in the first well 140 and disposed between the second source 150 and the drain 142 ([0007]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura et al. (2015/0270391).
Regarding claim 8, Tamura discloses all the claimed limitations as discussed above, except for the planar active regions and the fin active regions include an interface having a curved line in a top view. It has been held to be within the general skill of a worker in the art to select the claimed of the planar active regions and the fin active regions include an interface having a curved line in a top view was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the planar surface of the entire upper surface of the layer of material would yield unexpected result. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Tamura by forming the planar active regions and the fin active regions include an interface having a curved line in a top view, because such a forming the curved line in a top view can vary depending upon the device in a particular application.
Regarding claim 9, Tamura (Fig. 7B) discloses wherein the source 150 is formed on the fin active regions 114; the drain 142 is formed on the planar active regions; and the gate structure 162 is formed on both the planar active regions and the fin active regions and is overlapped with the interface of the planar active regions and the fin active regions in the top view.
Regarding claim 10, Tamura (Fig. 7B) discloses wherein the source 150 has multiple portions formed on the fin active regions 114, respectively.
Allowable Subject Matter
Claims 3-5 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose wherein the STI feature has an uneven structure that includes a first segment of a first thickness, a second segment of a second thickness, and a transition segment connecting the first and second segments of the STI features; the second thickness is greater than the first thickness; and the transition segment of the STI feature has a varying thickness and is overlapped with the neutral region in a top view (claim 3); or wherein the gate structure includes a first segment and a second segment interposed by the portion of the STI feature, wherein the first segment of the gate structure is disposed directly on the neutral region and spans between the source and the portion of the STI feature along a first direction, the second segment of the gate structure is disposed directly on the first well and spans between the portion of the STI feature and the drain, the first segment is configured to be electrically connected to a power signal line, and the second segment of the gate structure is configured to be floating (claims 4 and 14).
The dependent claims being further limiting and definite are also allowable.
Claims 21-24 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claim 21. Specifically, the combination of an integrated circuit (IC) structure, comprising: a first field-effect transistor (FET) and a second FET formed on the semiconductor substrate, wherein the first FET includes a first source disposed on the second well, a drain disposed on the first well, and a first gate structure interposed between the first source and the drain, the first gate structure landing on the first well, the neutral region and the second well, and the second FET includes a second source disposed on the second well, the drain, and a second gate structure interposed between the second source and the drain, the second gate structure landing on the first well, the neutral region and the second well, wherein the STI feature further includes a first portion formed in the first well and interposed between the first source and the drain, and a second portion formed in the first well and interposed between the second source and the drain; the first gate structure includes a first segment and a second segment interposed by the first portion of the STI feature; and the second gate structure includes a third segment and a fourth segment interposed by the second portion of the STI feature.
The dependent claims being further limiting and definite are also allowable.
Conclusion
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814