DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 5-6, 8-9, 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “wherein the semiconductor devices with the gate length of 3 nanometers (nm) that are located in a corner of the die have a minimum gate height of 6.2 nanometers (nm)”. Claim 2 is dependent on claim 1 which requires that over 99% of the semiconductor devices with the gate length of 3 nanometer (nm) have a gate height of from 10 to 14 nanometers or minimum gate height is 10nm. Having minimum gate height of 6.2 nm means that some of these device can have gate height greater than 6.2nm and less than 10nm, which falls outside of the range from 10 to 14 nm. So it is unclear how these devices in the corner of the die that have gate height greater than 6.2nm but less than 10nm and still consider to be included in the group of having the gate height with the range of 10 to 14nm. Furthermore, if one is to understand the claim language as the gate height now has minimum gate height of 6.2nm instead of 10nm, then claim 2 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 10nm is greater than 6.2nm, the device have gate height from 10-14nm automatically satisfying the requirement that the gate height is greater than 6.2nm.
Claim 3 recites “wherein the semiconductor devices with the gate length of 3 nanometers (nm) have a maximum gate height of 18.4 nanometers (nm)”. Claim 3 depends on claim 1 which requires that the gate height is from 10 to 14 nm, or maximum gate height of 14nm. Having maximum gate height 18nm means some of these devices can have gate height from 14nm to 18nm, which falls outside of the range from 10 to 14 nm. So it is unclear how these devices that have gate height greater than 14 and less than 18nm can still be considered to be in the group of having the gate height with the range of 10 to 14nm. Furthermore, if one is to understand the claim language as the gate height now has maximum gate height of 18nm instead of 14nm, then claim 3 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 14nm is less than 18nm, the device have gate height from 10-14nm automatically satisfying the requirement that the gate height is less than 18nm.
Claim 5 recites “wherein the semiconductor devices with the gate length of 9 nanometers (nm) that are located in a corner of the die have a minimum gate height of 8.1 nanometers (nm)”. Claim 5 is dependent on claim 4, which requires that the device with gate length of 9nm have gate height in the range of 10 to 13nm. Having minimum gate height of 8.1 nm means that some of these device can have gate height greater than 8.1 nm and less than 10 nm, which falls outside of the range from 10 to 13 nm. So it is unclear how these devices in the corner of the die that have gate height greater than 8.1 nm but less than 10nm and still consider to be included in the group of having the gate height with the range of 10 to 13nm. Furthermore, if one is to understand the claim language as the gate height now has minimum gate height of 8.1 nm instead of 10nm, then claim 5 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 10nm is greater than 8.1nm, the device have gate height from 10-13nm automatically satisfying the requirement that the gate height is greater than 8.1nm.
Claim 6 recites “wherein the semiconductor devices with the gate length of 9 nanometers (nm) have a maximum gate height of 17.4 nanometers (nm)”. Claim 6 is dependent of claim 4, which requires that the gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm). Having maximum gate height 17.4 nm means some of these devices can have gate height from 13 nm to 17.4 nm, which falls outside of the range from 10 to 13 nm. So it is unclear how these devices that have gate height greater than 13 and less than 17.4 nm can still be considered to be in the group of having the gate height with the range of 10 to 13 nm. Furthermore, if one is to understand the claim language as the gate height now has maximum gate height of 17.4 nm instead of 13 nm, then claim 6 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 13 nm is less than 17.4 nm, the device have gate height from 10-13 nm automatically satisfying the requirement that the gate height is less than 17.4 nm.
Claim 8 recites “wherein the semiconductor devices with the gate length of 55 nanometers (nm) that are located in a corner of the die have a minimum gate height of 11.1 nanometers (nm)”. Claim 8 is dependent on claim 7, which requires that the semiconductor device with the gate length of 55 nm have a gate height of from 14 to 19 nm. Having minimum gate height of 11.1 nm means that some of these device can have gate height greater than 11.1 nm and less than 14 nm, which falls outside of the range from 14 to 19 nm. So it is unclear how these devices in the corner of the die that have gate height greater than 11.1 nm but less than 14 nm and still consider to be included in the group of having the gate height with the range of 14 to 19 nm. Furthermore, if one is to understand the claim language as the gate height now has minimum gate height of 11.1 nm instead of 14 nm, then claim 8 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 14 nm is greater than 11.1nm, the device have gate height from 14-19 nm automatically satisfying the requirement that the gate height is greater than 11.1nm.
Claim 9 recites “wherein the semiconductor devices with the gate length of 55 nanometers (nm) have a maximum gate height of 21.6 nanometers (nm)”. Claim 9 is dependent on claim 7, which requires that the semiconductor device with the gate length of 55 nm have gate height of from 14 to 19 nm. Having maximum gate height of 21.6 nm means that some of these devices can have gate height greater than 19 and less than 21.6nm, which falls outside of the range in claim 7. So it is unclear how these devices that have gate height greater than 19 nm but less than 21.6 nm and still consider to be included in the group of having the gate height with the range of 14 to 19 nm. Furthermore, if one is to understand the claim language as the gate height now has maximum gate height of 21.6 nm instead of 19 nm, then claim 9 now recites a broad range and narrow range in the same claim. It is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 21.6 nm is greater than 19 nm, the device have gate height from 14-19 nm automatically satisfying the requirement that the maximum gate height is greater than 21.6 nm.
Claim 11 recites “wherein the semiconductor devices with the gate length of 135 nanometers (nm) that are located in a corner of the die have a minimum gate height of 13.1 nanometers (nm)”. Claim 11 is dependent on claim 10, which requires that the devices with gate length of 135 nm have gate height in the range of 16 to 19 nm. Having minimum gate height of 13.1 nm means that some of these devices can have gate height greater than 13.1 nm and less than 16 nm, which falls outside of the range from 16 to 19 nm. So it is unclear how these devices in the corner of the die that have gate height greater than 13.1 nm but less than 16 nm and still consider to be included in the group of having the gate height with the range of 16 to 19 nm. Furthermore, if one is to understand the claim language as the gate height now has minimum gate height of 13.1 nm instead of 16 nm, then claim 11 now recites a broad range and narrow range in the same claim. This is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 16 nm is greater than 13.1nm, the device have gate height from 16-19 nm automatically satisfying the requirement that the gate height is greater than 13.1nm.
Claim 12 recites “wherein the semiconductor devices with the gate length of 135 nanometers (nm)have a maximum gate height of 20.5 nanometers (nm)”. Claim 12 is dependent on claim 10, which requires that gate length of 135nm has gate height in the range of 16 to 19 nm. Having maximum gate height of 20.5 nm means that some of these devices can have gate height greater than 19 and less than 20.5 nm, which falls outside of the range in claim 10. So it is unclear how these devices that have gate height greater than 19 nm but less than 20.5 nm and still consider to be included in the group of having the gate height with the range of 16 to 19 nm. Furthermore, if one is to understand the claim language as the gate height now has maximum gate height of 20.5 nm instead of 19 nm, then claim 12 now recites a broad range and narrow range in the same claim. This is indefinite as to which range is required for the claim. For the purpose of examination, the Examiner interpreted that since the gate height of 20.5 nm is greater than 19 nm, the device have gate height from 16-19 nm automatically satisfying the requirement that the maximum gate height is greater than 20.5 nm.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2021/0098450 A1) in view of and George et al. (US 2019/0044048 A1).
Regarding claim 1, Huang teaches a method (method in Figs. 4A-12B of Huang) for manufacturing semiconductor devices (nanosheet transistors 100A in Fig. 1A) on a die (substrate as described in [0015] of Huang), the method comprising:
forming semiconductor devices (devices 100A in Fig. 1A of Huang) with a gate length (L1 in Fig. 1A) of 3 nanometers (nm) (as described in [0037] of Huang) and having metal gates (as stated in [0076] of Huang).
But Huang does not teach that wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm).
Huang discloses that any number of nanowire channels (114 in Fig. 1A or 404 in Fig. 10A of Huang) can be included (see end of [0027] and [0047] of Huang) though 4 pairs of alternating layers is given as example.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the stack of three pairs of alternating layers in order to have a smaller capability device and lower cost (fewer channel layers typically means cheaper to make).
Since Huang discloses that the alternating layers in the stack (456 of Fig. 10A of Huang) have the same thickness (see [0048] of Huang) and that the height of the nanowire channel stack H4 is about 15nm to 120nm (see end of [0070] of Huang). This means each of alternating layer in the stack shown in Fig. 10A is about roughly less 2nm to 15nm in thickness. So for 3 pairs of alternating layers, the height H4 is about 11nm to 90nm. This range overlaps with claim range of 10 to 14nm.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the thickness of the first dielectric sidewall structure to be in a range of about 4-10 nanometers. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
But Huang does not teach that wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have the gate height of from 10 to 14 nanometers (nm).
George teaches a method of forming a replacement metal gate. The method includes depositing a conformal gate metal layer with thickness variation around 1%, and width below 5nm. The individual metal gate (404 in Fig. 27D-27F of George) has height variation less than 2% (see [0175] of George).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the metal replacement gate method of George in Huang’s method in order to have high quality devices with high reliability.
Regarding claim 2, Huang in view of George teaches all limitations of the method of claim 1, and also teaches wherein the semiconductor devices with the gate length of 3 nanometers (nm) that are located in a corner of the die have a minimum gate height of 6.2 nanometers (nm) (see interpretation in 112b rejection above).
Regarding claim 3, Huang in view of George teaches all limitations of the method of claim 1, and also teaches wherein the semiconductor devices with the gate length of 3 nanometers (nm) have a maximum gate height of 18.4 nanometers (nm) (see interpretation in 112b rejection above).
Regarding claim 4, Huang in view of George teaches all limitations of the method of claim 1, but does not teach explicitly that the method further comprising forming semiconductor devices with a gate length of 9 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm).
Huang teaches that the gate structures 110B have gate length L2, which is greater than L1 (see [0037] of Huang), and that the ratio of L2 to L1 is greater than 1. Since the gate length of 9nm is three times the gate length of 3nm, the reference Hung teaches that the gate structures 110B have gate length greater than 3nm, which includes the gate length 9nm of the claim. Thus, a prima facie case of obviousness exists.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the gate length of the gate structures 110B of Huang to be 9nm. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
As incorporated, the devices with 9nm also have gate height in the range of 10 to 14 nm.
But Huang in view of George does not teach that 90% of the semiconductor devices with gate length of 9 nm have gate height of from 10 to 13nm.
George teaches a method of forming a replacement metal gate. The method includes depositing a conformal gate metal layer with thickness variation around 1%. The individual metal gate (404 in Fig. 27D-27F of George) has height variation less than 2% (see [0175] of George).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the metal replacement gate method of George to make gate structures 110B in Huang’s method in order to have high quality devices with high reliability.
Regarding claim 5, Huang in view of George teaches all limitations of the method of claim 4, and also teaches wherein the semiconductor devices with the gate length of 9 nanometers (nm) that are located in a corner of the die have a minimum gate height of 8.1 nanometers (nm) (see interpretation in 112b rejection above).
Regarding claim 6, Huang in view of George teaches all limitations of the method of claim 4, and also teaches wherein the semiconductor devices with the gate length of 9 nanometers (nm) have a maximum gate height of 17.4 nanometers (nm) (see interpretation in 112b rejection above).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of and George, as applied in claim 1, and further in view of Srinivas (US 2017/0317645 A1).
Regarding claim 7, Huang in view of George teaches all limitations of the method of claim 1, but does not explicitly teach further comprising forming semiconductor devices with a gate length of 55 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm).
Huang teaches that the gate structures 110B have gate length L2, which is greater than L1 (see [0037] of Huang), and that the ratio of L2 to L1 is greater than 5.
Srinivas teaches a manufacturing method that yields the gate length of transistors of 55nm appropriate for low voltage process (see [0028] of Srinivas).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the gate structures 110B with gate length 55nm in order to minimize power consumption.
As incorporated, the gate structures of gate length 55nm are also made of metal gate by George’s method as combined in claim 1.
But Huang-George-Srinivas does not teach that wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm).
Huang discloses that the alternating layers in the stack (456 of Fig. 10A of Huang) have the same thickness (see [0048] of Huang) and that the height of the nanowire channel stack H4 is about 15nm to 120nm (see end of [0070] of Huang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the gate structures 110B with gate height at least 15nm to 120nm in order to completely cover all the nanowire channels.
Since the claimed ranges of 14-19 nm “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the gate height to be in a range of about 14-19 nanometers. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
But Huang-George-Srinivas does not teach that wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have the gate height of from 14 to 19 nanometers (nm).
George teaches a method of forming a replacement metal gate. The method includes depositing a conformal gate metal layer with thickness variation around 1%. The individual metal gate (404 in Fig. 27D-27F of George) has height variation less than 2% (see [0175] of George).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the metal replacement gate method of George in Huang’s method in order to have high quality devices with high reliability.
Regarding claim 8, Huang-GeorgeSrinivas teaches all limitations of the method of claim 7, and also teaches wherein the semiconductor devices with the gate length of 55 nanometers (nm) that are located in a corner of the die have a minimum gate height of 11.1 nanometers (nm) (see interpretation in 112b rejection above).
Regarding claim 9, Huang-GeorgeSrinivas teaches all limitations of the method of claim 7, and also teaches wherein the semiconductor devices with the gate length of 55 nanometers (nm) have a maximum gate height of 21.6 nanometers (nm) (see interpretation in 112b rejection above).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of and George, as applied in claim 1, and further in view of Chu et al. (US 2020/0273953 A1).
Regarding claim 10, Huang in view of George teaches all limitations of the method of claim1, but does not teach the method further comprising forming semiconductor devices with a gate length of 135 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 135 nanometers (nm)have a gate height of from 16 to 19 nanometers (nm).
Chu teaches a method of forming a short-channel and a long-channel devices (Figs. 1-2 of Chu). The short-channel device has gate length of 20nm or less and the long-channel device has gate length of 60-200nm (see [0018] of Chu). Chu also discloses that the long-channel devices are typically located in the peripheral circuitry (see [0003] of Chu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the gate length of the transistors 110B of Huang to be in the range of 60 to 200nm, as disclosed by Chu, in order to reduce power consumption (as disclosed in [0003] of Chu).
As incorporated, the claimed gate length of 135nm is within the prior art range of 60 to 200nm, so a prima facie case of obviousness exists.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the gate length of the transistors 110B of Huang to be 135 nm in order to reduce power consumption (as disclosed in [0003] of Chu). See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 11, Huang in view of George teaches all limitations of the method of claim 10, and also teaches wherein the semiconductor devices with the gate length of 135 nanometers (nm) that are located in a corner (as stated in [0003] of Chu, the long channel devices are located on the periphery of the die, which include the corner regions) of the die have a minimum gate height of 13.1 nanometers (nm) (please see interpretation in 112b rejection above).
Regarding claim 12, Huang in view of George teaches all limitations of the method of claim 10, and also teaches wherein the semiconductor devices with the gate length of 135 nanometers (nm)have a maximum gate height of 20.5 nanometers (nm) (please see interpretation in 112b rejection above).
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior art of record does not disclose or fairly suggest a method satisfying “wherein the gate height of less than 1% of the semiconductor devices with the gate length of 3 nanometers (nm) is greater than 14 nanometers (nm).
Regarding claim 15, the prior art of record does not teach or fairly suggest a method for manufacturing semiconductor devices on a die comprising “forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm); forming semiconductor devices with a gate length of 9 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm); forming semiconductor devices with a gate length of 55 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm); and forming semiconductor devices with a gate length of 135 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 135 nanometers (nm) have a gate height of from 16 to 19 nanometers (nm)”.
Regarding claim 17, the prior art of record does not teach or fairly suggest a semiconductor die comprising: “semiconductor devices with a gate length of 3 nanometers (nm) having a minimum gate height of 6.2 nanometers (nm) and a maximum gate height of 18.4 nanometers (nm); semiconductor devices with a gate length of 9 nanometers (nm) having a minimum gate height of 8.1 nanorneters (nm) and a maximum gate height of 17.4 nanometers (nm); semiconductor devices with a gate length of 55 nanometers (nm) having a minimum gate height of 11.1 nanometers (nm) and a maximum gate height of 21.6 nanometers (nm); and semiconductor devices with a gate length of 135 nanometers (nm) having a minimum gate height of 13.1 nanometers (nm) and a maximum gate height of 20.5 nanometers (nm)”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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