Prosecution Insights
Last updated: July 17, 2026
Application No. 18/353,976

BARRIER LAYERS IN SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Jul 18, 2023
Examiner
NGUYEN, DAO H
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1152 granted / 1261 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
29 currently pending
Career history
1288
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
51.7%
+11.7% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1261 resolved cases

Office Action

§102 §103
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the communications dated 03/12/2026. Claims 9-16, and 21-32 are pending in this application. Applicant made a provisional election without traverse to prosecute the invention of Group II, Species II, claims 9-16 and new claims 21-32, is acknowledged. Claims 1-8, and 17-20 have been cancelled. Applicant has the right to file a divisional application covering the subject matter of the non-elected claims. Acknowledges 2. Receipt is acknowledged of the following items from the Applicant. Information Disclosure Statement (IDS) filed on 03/12/2026. The references cited on the PTOL 1449 form have been considered. Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609. Specification 3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claims 28-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JO et al. (US 2019/0148521) Regarding claim 28, JO discloses a method, comprising: forming a polysilicon structure 180 (polysilicon gate structure, see fig. 6, and para. 0068) on a substrate 100; forming a nitride layer 150 (fig. 7) on the polysilicon structure 180 and the substrate 100; depositing a gate spacer 140 (fig. 10) on the nitride layer 150; removing an upper portion of the polysilicon structure 180 to expose an upper portion of the nitride layer 150 (figs. 11-12, and para. 0095); removing the upper portion of the nitride layer 150 (figs. 16-18: the nitride layer 150 being removed to completely expose the inner surface of the gate spacer 140, and having only portion 150c, or 150a in fig. 1 remained; see also para. 0108); removing a lower portion of the polysilicon structure (figs. 16-18; para. 0109); and forming a gate structure 130 on the nitride layer 150a (see fig. 1, and para. 0109). Regarding claim 29, JO discloses the method of claim 28, wherein forming the gate structure 130 comprises forming a gate dielectric layer 131 on top and side surfaces (end surfaces) of the nitride layer 150a. See figs. 1-3. Regarding claim 30, JO discloses the method of claim 28, wherein forming the nitride layer 150 comprises performing a nitridation treatment NP to side surfaces of the polysilicon structure 180. See fig. 7. Regarding claim 31, JO discloses the method of claim 28, wherein forming the nitride layer 150 comprises: forming a vertical portion 150b of the nitride layer 150 on a side surface of the polysilicon structure 180;and forming a horizontal portion 150a of the nitride layer 150 on a top surface of the substrate 100. See fig. 7. Claim Rejections - 35 U.S.C. § 103 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 7. Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over JO et al. (US 2019/0148521) Regarding claim 32, JO discloses the method of claim 28 comprising all claimed limitations, as discussed above, and wherein forming the nitride layer 150 further comprises forming the vertical and horizontal portions 150b, 150a, respectively (fig. 7), except for forming the vertical and horizontal portions with different thicknesses. However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions or thicknesses of the claimed elements, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in dimension / thickness of a component is generally recognized as being within the level of ordinary skill in the art. It is to be expected that a change in size / thickness would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955). The instant specification contains no disclosure of either the critical nature of the claimed dimensions/thicknesses or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).) The claimed limitation regarding to the different thicknesses of the nitride layer do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in thickness of a component. A change in dimentions/thicknesses is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04). 8. Claims 9, 11, 13-16, 28 are rejected under 35 U.S.C. 103 as being unpatentable over JO et al. (US 2019/0148521) in view of Hoentschel et al. (US 2011/0156099) Regarding claim 9, JO discloses a method, comprising: forming a polysilicon structure (polysilicon gate structure) 180 (see figs. 7-12, Figs. 16, and para. 0068) on a substrate 100; performing a nitridation process NP (Fig. 7, paras. 0008, 0087, 0125) to form a barrier layer 150 on the polysilicon structure 183; forming a gate spacer 140 (fig. 10) on the barrier layer 150; forming a source/drain region 161/162 adjacent to the barrier layer 150; adjusting a height of the barrier layer 150 (figs. 11, 12); and replacing the polysilicon structure 183 with a gate structure 130 (see para. 0113 and Fig. 1). JO fails to disclose: Performing an annealing process to densify the gate spacer. Hoentschel discloses: A method comprising performing an annealing process 309 to densify a gate spacer 356. See fig. 3f and para. 0060. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of JO to further include the step of performing an annealing process to densify the gate spacer, as that taught by Hoentschel, in order to imparting enhanced etch resistivity to the material. See para. 0060 of Hoentschel. Regarding claim 11, JO/Hoentschel discloses the method of claim 9, comprising all claimed limitations as discussed above, except for wherein performing the nitridation process comprises forming the barrier layer with a thickness of about 2 A to about 5 A. However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions or thicknesses of the claimed elements, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in dimension / thickness of a component is generally recognized as being within the level of ordinary skill in the art. It is to be expected that a change in dimension / thickness would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art, such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955). The instant specification contains no disclosure of either the critical nature of the claimed dimensions/thicknesses or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).) The claimed limitation regarding to the different thickness of the nitride layer do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in thickness of a component. A change in dimension/thickness is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04). Regarding claim 13, JO/Hoentschel discloses the method of claim 9, wherein performing the nitridation process comprises forming a hydrogen-free silicon nitride layer on the polysilicon structure. See para. 0040: gas source 292 contains nitrogen N2. Regarding claim 14, JO/Hoentschel discloses the method of claim 9, wherein adjusting the height of the barrier layer comprises: removing an upper portion 185 of the polysilicon structure 180; etching the barrier layer 150 using a lower portion of the polysilicon structure as a masking layer. See figs. 10-12, 16-18. Regarding claim 15, JO/Hoentschel discloses the method of claim 9, comprising all claimed limitation. See the rejection of claim 11. Regarding claim 16, JO/Hoentschel discloses the method of claim 9, wherein performing the nitridation process comprises forming the barrier layer 150 with an L-shaped cross-sectional profile. See figs. 9-10 of JO. Regarding claim 21, JO discloses a method, comprising: forming a polysilicon structure 183 (see figs. 7-12, Figs. 16, and para. 0068) on a substrate 100; forming a nitride layer 150 (fig. 7, paras. 0008, 0087, 0125) on the polysilicon structure 183; depositing a gate spacer 140 (fig. 10) on the nitride layer 150; forming a source/drain region 161/162 adjacent to the nitride layer 150; reducing a height of the nitride layer 150; and replacing the polysilicon structure 183 with a gate structure 130 (see para. 0113 and Fig. 1). JO fails to disclose: Increasing a density of the gate spacer. Hoentschel discloses: A method comprising increasing a density of a gate spacer 356 by performing an annealing process 309. See fig. 3f and para. 0060. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of JO to further include the step of increasing a density of the gate spacer, as that taught by Hoentschel, in order to imparting enhanced etch resistivity to the material. See para. 0060 of Hoentschel. Regarding claims 23, 25, and 27, JO/Hoentschel discloses the method comprising all claimed limitations. See the rejections of claims 11, 13, and 15, respectively. Regarding claim 26, JO/Hoentschel discloses the method of claim 21, further comprising forming a thermal oxide layer 181 between the polysilicon structure 183 and the substrate 100, wherein forming the nitride layer 183 comprises forming a portion of the nitride layer on a surface of the thermal oxide layer. See fig. 7. 9. Claims 10, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over JO et al. (US 2019/0148521) in view of Hoentschel et al. (US 2011/0156099) and further in view of Rogers et al. (US 2013/0109162) Regarding claims 10, and 22, JO/Hoentschel discloses the method, comprising all claimed limitations, as discussed above, except for wherein performing the nitridation process comprises exposing the polysilicon structure to a nitrogen plasma. Rogers discloses a method comprising performing the nitridation process to form a barrier layer 113 (fig. 1) on a polysilicon structure 106 comprises exposing the polysilicon structure 106 to a nitrogen plasma. See paras. 0038-0042. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of JO/Hoentschel so that the nitridation process comprises exposing the polysilicon structure to a nitrogen plasma, as that taught by Rogers, in order to improve the reliability of the tunnel oxide and/or the suppression of dopant diffusion. See para. 0038 of Rogers. Allowable Subject Matter 10. Claims 12, and 24 are allowable. Claims 12, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed method (in addition to the other limitations in the claim) comprising: Claim 12: The method of claim 9, wherein performing the nitridation process comprises exposing the polysilicon structure to a nitrogen plasma for a duration of about 1 sec to about 5 sec. Claim 24: The method of claim 21, wherein forming the nitride layer comprises controlling an exposure time of the polysilicon structure to a nitrogen plasma to be between about 1 sec and about 5 sec. Conclusion 11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 April 18, 2026
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Prosecution Timeline

Jul 18, 2023
Application Filed
Feb 18, 2025
Response after Non-Final Action
Apr 29, 2026
Non-Final Rejection mailed — §102, §103
Jun 18, 2026
Interview Requested
Jun 29, 2026
Examiner Interview Summary
Jun 29, 2026
Applicant Interview (Telephonic)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1261 resolved cases by this examiner. Grant probability derived from career allowance rate.

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