DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-20, 32-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao(USPGPUB DOCUMENT: 2021/0391237, hereinafter Kao) in view of Dote (USPGPUB DOCUMENT: 2016/0351474, hereinafter Dote) and Li (USPGPUB DOCUMENT: 2011/0139497, hereinafter Li).
Re claim 15 Kao discloses a method, comprising: providing a substrate(102); forming, over a frontside surface(103a) of the substrate(102), a plurality of metal layers(106/111/110) within at least one dielectric layer(104); forming a via(TSV)(112) electrically connected to a top metal layer of the plurality of metal layers(106/111/110) and extending through the frontside surface(103a) of the substrate(102); etching[0013] a region in a backside surface[0013] of the substrate(102) opposite the frontside surface(103a), the etched region extending through the frontside surface(103a); and forming a metal structure(118) over the etched region,.
Kao does not disclose forming a plurality of vias(TSV); wherein the plurality of vias extend into and contact the metal structure.
Dote disclose wherein the via(3) extend into and contact the metal structure(2A/2X/4/5)[0037].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Dote to the teachings of Kao in order to minimize separation that may occur from repeated expansion and contraction due to the heat generated during the fabrication process [0027, Dote].
Kao and Dote does not disclose forming a plurality of vias(TSV);
Li disclose forming a plurality of vias(TSV)(left/right 104);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of Kao in order to to ensure proper operation of the electrical package [0003, Li].
Kao and Li does not disclose wherein the plurality of vias extend into and contact the metal structure.
Liu disclose wherein the plurality of vias extend into and contact the metal structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of Kao in order to to ensure proper operation of the electrical package [0003, Li].
Re claim 16 Kao and Li and Liu disclose the method of claim 15, further comprising: forming at least one shallow trench isolation (STI) region in the substrate(102) at the frontside surface(103a) before forming the plurality of metal layers(106/111/110), wherein the metal structure(118) and the plurality of vias(TSV)(112) extend through the at least one STI region.
Re claim 17 Kao and Li and Liu disclose the method of claim 15, further comprising: forming, over the etched region before forming the metal structure(118), a dielectric structure, the dielectric structure isolating the metal structure(118) from the substrate(102).
Re claim 18 Kao and Li and Liu disclose the method of claim 15, further comprising: forming a plurality of doped regions within the substrate(102) among the plurality of vias(TSV)(112), wherein the plurality of doped regions are electrically isolated.
Re claim 19 Kao and Li and Liu disclose the method of claim 15, further comprising:forming a plurality of metal structure(118)s within at least one of the plurality of metal layers(106/111/110) among the plurality of vias(TSV)(112), wherein the plurality of metal structure(118)s are electrically isolated.
Re claim 20 Kao and Li and Liu disclose the method of claim 15, wherein: the plurality of vias(TSV)(112) are arranged in a two-dimensional array in a plan view of the substrate(102).
Re claim 32 Kao discloses a method, comprising: providing a substrate(102) having a frontside surface(103a) and a backside surface[0013] opposite the frontside surface(103a), the substrate(102) having an etched region in the backside surface[0013] that extends through the frontside surface(103a); forming at least one dielectric layer(104) disposed over the frontside surface(103a) of the substrate(102), the at least one dielectric layer(104) incorporating a plurality of metal layers(106/111/110); forming a vias(TSV)(112), each of the vias(TSV)(112) electrically connected to a top metal layer of the plurality of metal layers(106/111/110) and extending through a remaining one or more of the plurality of metal layers(106/111/110) and the frontside surface(103a) of the substrate(102); and forming a metal structure(118) extending from the backside surface[0013] into the substrate(102), covering the etched region,
Kao does not disclose forming a plurality of vias(TSV); wherein the plurality of vias extend into and contact the metal structure.
Li disclose forming a plurality of vias(TSV)(left/right 104);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of Kao in order to to ensure proper operation of the electrical package [0003, Li].
Kao and Li does not disclose wherein the plurality of vias extend into and contact the metal structure.
Liu disclose wherein the plurality of vias extend into and contact the metal structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of Kao in order to to ensure proper operation of the electrical package [0003, Li].
Re claim 33 Kao and Li and Liu disclose the method of claim 32, further comprising: forming at least one shallow trench isolation (STI) region disposed in the substrate(102) at the frontside surface(103a), wherein the metal structure(118) and the plurality of vias(TSV)(112) extend through the at least one STI region.
Re claim 34 Kao and Li and Liu disclose the method of claim 33, further comprising: forming a dielectric structure isolating the metal structure(118) from the substrate(102).
Claim(s) 21-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao(USPGPUB DOCUMENT: 2021/0391237, hereinafter Kao) in view of Li (USPGPUB DOCUMENT: 2011/0139497, hereinafter Li) and Yu (USPGPUB DOCUMENT: 2014/0225795, hereinafter Yu).
Re claim 21 Kao discloses a method, comprising: providing a substrate(102); forming at least one dielectric layer(104) disposed over a frontside surface(103a) of the substrate(102); forming a plurality of metal layers(106/111/110) residing in the at least one dielectric layer(104); forming a first via structure(112) comprising a vias(TSV)(112), the first via structure(112) electrically connected to one of the plurality of metal layers(106/111/110) and extending through the frontside surface(103a) of the substrate(102); and forming a via structure extending from a backside surface[0013] of the substrate(102) opposite the frontside surface(103a) into the substrate(102).
Kao does not disclose forming a second via structure; wherein the plurality of vias extend into and contact the second via structure
Li disclose forming a second via structure (left/right 104);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of Kao in order to affect the whole performance of the component [0007, Li].
Kao and Li does not disclose wherein the plurality of vias extend into and contact the second via structure
Yu disclose wherein the plurality of vias(19/13) extend into and contact the second via structure(19/13)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Kao in order to minimize separation that may occur from repeated expansion and contraction due to the heat generated during the fabrication process [0027, Yu].
Re claim 22 Kao and Li and Yu disclose the method of claim 21, wherein: forming the plurality of metal layers(106/111/110) comprises forming a top metal layer and forming at least one additional metal layer positioned between the top metal layer and the substrate(102), wherein the first via structure(112) extends from, and is electrically connected to, the top metal layer.
Re claim 23 Kao and Li and Yu disclose the method of claim 21, wherein: each of the plurality of vias(TSV)(112) is directly connected to the one of the plurality of metal layers(106/111/110) and extends into the substrate(102).
Re claim 24 Kao and Li and Yu disclose the method of claim 23, wherein:the plurality of vias(TSV)(112) are arranged in a two-dimensional array in a plan view of the substrate(102).
Re claim 25 Kao and Li and Yu disclose the method of claim 23, further comprising: forming a plurality of doped regions distributed among the plurality of vias(TSV)(112) within the substrate(102), wherein the plurality of doped regions are electrically isolated.
Re claim 26 Kao and Li and Yu disclose the method of claim 23, further comprising: forming a plurality of metal structure(118)s distributed among the plurality of vias(TSV)(112) within at least one of the plurality of metal layers(106/111/110), wherein the plurality of metal structure(118)s are electrically isolated.
Re claim 27 Kao and Li and Yu disclose the method of claim 21, further comprising: forming at least one shallow trench isolation (STI) region disposed in the substrate(102) at the frontside surface(103a), wherein the plurality of vias(TSV)(112) extend through the at least one STI region.
Re claim 28 Kao and Li and Yu disclose the method of claim 21, wherein: the substrate(102) defines an etched region extending from the backside surface[0013] and into the substrate(102); and the second via structure covers the etched region.
Re claim 29 Kao and Li and Yu disclose the method of claim 28, further comprising: forming at least one shallow trench isolation (STI) region disposed in the substrate(102) at the frontside surface(103a), wherein the second via structure contacts the at least one STI region in the etched region.
Re claim 30 Kao and Li and Yu disclose the method of claim 29, wherein the second via structure extends over a portion of the backside surface[0013] of the substrate(102).
Re claim 31 Kao and Li and Yu disclose the method of claim 21, further comprising:forming a dielectric structure isolating the first via structure(112) from the substrate(102).
Response to Arguments
Applicant’s arguments with respect to claim(s) 15-34 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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