DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on July 18, 2023 was considered by the Examiner.
Election/Restrictions
Applicant's election without traverse of Species H (FIG. 9) in the reply filed on April 6, 2025 is acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Applicant has withdrawn claims 2 and 20 as being directed to non-elected species. Claim 2 includes “wherein the L- shaped section is free of an AP overlying the second metal line.” Claim 20 includes “wherein the second seal ring structure [L-shaped in claim 19] is free of an AP layer”.
Similarly, claim 16 includes “wherein the second seal ring structure and the third seal ring structure are each free of an AP layer.” The third seal ring structure is L-shaped in claim 12.
In FIG. 9 of the instant application, the L-shaped line 375 and bridge section 366 include APs 264, [0043]. Accordingly, as Species H (FIG. 9) was elected, claim 16 is directed to a non-elected species and is hereby withdrawn from consideration. This withdrawal from consideration is consistent with Applicant’s withdrawal of claims 2 and 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2006332344A (“Takahashi”) in view of US20150357317A1 (“Chen”).
RE: Claim 1, Takahashi discloses A semiconductor structure, comprising:
a circuit region (23 in FIG. 7a, [0035]);
a seal ring (61 in FIGs. 7a, 10c, [0056]) surrounding the circuit region, wherein the seal ring forms a substantially rectangular periphery (FIG. 7a shows 61 forms a substantially rectangular periphery); and
a corner seal ring (CSR) structure (62 in FIG. 10c; since the connection between the line-shaped patterns becomes strong, it is possible to effectively prevent the peeling of the interlayer insulating film or the generation of cracks due to stress in a plurality of directions, [0079]; 61 is a seal ring, [0056]; 62 prevents peeling of insulating films or generation of cracks due to stress and therefore contributes to the sealing of the inside of the seal ring 61; Further, the reference US20080251923A1 (“Wang”) discloses Seal rings are stress protection structures around integrated circuits, protecting the internal circuit inside semiconductor chips from damage caused by the dicing, [0002]; Accordingly, under a broad reasonable interpretation, 62 is considered a corner seal ring structure as it is a corner stress protection structure) at an interior corner of the seal ring, wherein the CSR structure includes:
a first edge (bottom edge of horizontal portion of 61 in FIG. 10c) and a second edge (left edge of vertical portion of 61 in FIG. 10c) of the seal ring,
an L-shaped section (L-shaped section including L-shaped patterns 62f in FIG. 10c, [0079]) extending between the first edge and the second edge of the seal ring,
a first area (first area between 61 and 62 in FIG. 10c) between the seal ring and the L-shaped section,
a second area (second area immediately to the left and immediately below 62 in FIG. 10c),
wherein the seal ring includes a first top metal line (81d in FIG. 8a) and an aluminum pad (AP) (81f in FIG. 8a; seal ring 61 includes 81d, 81f, via 81e, [0061]; 81f and wirings 71b, 71d, 71f are formed of a common conductive material, [0061]; 71b, 71d, 71f are formed of an aluminum alloy, [0060]; Accordingly, 81f is formed of an aluminum alloy and under a broad reasonable interpretation, is considered an aluminum pad) disposed over and connected to the first top metal line (81f is disposed over and connected to 81d by via 81e in FIG. 8a),
wherein the L-shaped section includes a second top metal line (bottommost 62f in FIG. 10c which corresponds to 71f or 71d in FIG. 8a; L-shaped line patterns 62f are formed by combining line patterns, [0079]; FIG. 8a shows cross-sectional view of FIG. 7b which shows line patterns 62, [0057]; Accordingly, the cross-section of FIG. 8a would correspond to the cross-section of FIG. 10c across a line pattern of the L-shaped pattern 62f), the second top metal line having an L-shape (FIG. 10c shows bottommost 62f having an L-shape; Accordingly, 71f, 71d would have an L-shape), and
wherein the first area and the second area are free of dummy AP (as an interlayer insulating film between each wiring, a laminated structure such as an interlayer insulating film 41 and an interlayer insulating film 42, an interlayer insulating film 43 and an interlayer insulating film 44, and an interlayer insulating film 45 and an interlayer insulating film 46 are used, [0066] FIG. 8 shows an insulating portion of 41, 42, 43, 44, 45, 46 on either side of each line pattern 62a; Accordingly, an insulating portion of films 41, 42, 43, 44, 45, 46 would be on either side of the line-shaped segment of 62f; As a result, the first area between 61 and 62 and the second area immediately to the left and immediately below 62 in FIG. 10c would be occupied by an insulating film and therefore free of dummy AP).
Takahashi does not explicitly disclose:
a bridge section extending between the first edge and the second edge of the seal ring,
the L-shaped section is disposed between the seal ring and the bridge section;
the second area is between the L-shaped section and the bridge section.
In the same field of endeavor, Chen discloses in FIG. 13:
a bridge section (154b) extending between a first edge (bottom edge of horizontal portion of seal ring 152) and a second edge of a seal ring (left edge of vertical portion of seal ring 152),
an L-shaped section (L-shaped section formed by 154a) is disposed between the seal ring and the bridge section;
a second area (second area between 154a and the 154b) between the L-shaped section and the bridge section.
Chen further discloses The corner region 116 includes a seal ring 152 and a chip stress relief (CSR) pattern 154 a formed therein. A CSR pattern 154 b is formed proximate the corner region 116. In some embodiments, the CSR pattern 154 a and/or 154 b may comprise an alignment mark, for example. The seal ring 152 may comprise a metal ring formed proximate the scribe line region 111 of the integrated circuit die 102, for example. The CSR patterns 154 a and 154 b may comprise insulating materials, semiconductive materials, and/or conductive materials formed in predetermined shapes to reduce an impact of damage induced by thermal stress during packaging and in a field application, for example, [0053].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a bridge section extending between the first and second edges of the seal ring 61 and to dispose the L-shaped section 62 between the bridge section and the seal ring 61 as taught by Chen in order to reduce an impact of damage induced by thermal stress as further taught by Chen, [0053].
RE: Claim 3, Takahashi in view of Chen discloses The semiconductor structure of claim 1, further comprising a passivation layer disposed over the first top metal line and the second top metal line (FIG. 8a Takahashi shows passivation layer 47 disposed over the first top metal line 81d of 61 and the second top metal line 71d, 71f of 62, [0059]).
RE: Claim 4, Takahashi in view of Chen discloses The semiconductor structure of claim 1, wherein the second top metal line is spaced apart from the first top metal line (FIGs. 8a, 10c show each layer of 61 is spaced apart from each layer of 62).
RE: Claim 5, Takahashi in view of Chen discloses The semiconductor structure of claim 1, wherein the first top metal line has a first width, and the second top metal line has a second width greater than the first width (From Takahashi FIG. 10c shows the horizontal width of 62f is greater than the horizontal width of vertical portion of 61; Accordingly, the horizontal width of 71d, 71f is greater than horizontal width of 81d).
RE: Claim 10, Takahashi in view of Chen discloses The semiconductor structure of claim 1, wherein:
the bridge section includes a third top metal line (Chen discloses 154b comprises conductive materials, [0053]; conductive materials are copper, aluminum, other metals, [0017]; Accordingly, Chen teaches 154b is metal) connected to the first top metal line (FIG. 13 Chen shows 154b is connected to the metal seal ring 152, [0053]; Accordingly, as modified, 154b would be connected to the metal line 81d of the seal ring 61 in Takahashi); and
the second top metal line directly contacts the third top metal line (Chen discloses 154a comprises conductive materials, [0053]; conductive materials are copper, aluminum, other metals, [0017]; Accordingly, Chen teaches 154a is metal; FIG. 13 shows the L-shaped metal line 154a directly contacts 154b; Accordingly, as modified, the second top metal line 71d, 71f of Takahashi’s L-shaped 62f would directly contact the third top metal line of the bridge).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Chen as applied to claim 1, further in view of US20110284843A1 (“Chen-2”).
RE: Claim 6, Takahashi in view of Chen discloses The semiconductor structure of claim 1, wherein:
the AP is a first AP (81f in FIG. 8a in Takahashi is a first AP);
the L-shaped section includes a second AP (71f in FIG. 8a in Chen; 71f is formed of an aluminum alloy, [0060]; Accordingly, 71f is formed of an aluminum alloy and under a broad reasonable interpretation, is considered an aluminum pad) disposed over and connected to the second top metal line (FIG. 8a Chen shows 71f disposed over and connected to 71d by via 71e, [0080]).
Takahashi in view of Chen does not explicitly disclose:
the bridge section includes a third top metal line and a third AP disposed over and connected to the third top metal line;
the third AP is connected to the first AP; and
the third top metal line is connected to the first top metal line.
In the same field of endeavor, Chen-2 discloses in FIGs. 2-4:
a bridge section (110 in FIGs. 2, 4) includes a third top metal line (second layer of 110 at level M3 in FIG. 4, [0026]) and a third AP (first layer of 110 at level MT in FIG. 4; metallization layers include aluminum, [0027]; Accordingly under a broad reasonable interpretation, the first layer of 110 is an aluminum pad) disposed over and connected to the third top metal line (first and second layers of 110 are connected by a via at level V3, [0016], [0026]);
the third AP is connected to a first AP of a seal ring (first layer of seal ring 113 at level MT in FIG. 4; FIG. 4 shows the first layer of 110 and the first layer of 113 are at the same level MT; 113 is a seal ring structure, [0022]; 110 connects sides of the seal ring structure, [0016]; Accordingly, the first layer of 110 would be connected to the first layer of seal ring structure 113); and
the third top metal line is connected to a first top metal line (FIG. 4 shows the second layer of 110 and the second layer of 113 are at the same level M3; 110 connects sides of the seal ring structure, [0016]; Accordingly, the second layer of 110 would be connected to the second layer of seal ring structure 113).
Chen-2 further discloses With the formation of the enhanced structure 110, more metal structures exist at the corner region. The stress applied to the seal ring structure may thus be spread to more metal structures, and hence the seal ring structure is less likely to be damaged by stresses, [0016].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bridge section to include metal layers connecting sides of the seal ring 61 as taught by Chen-2 in order to spread stress to more metal structures and prevent damage to the seal ring 61 as further taught by Chen, [0016].
RE: Claim 7, Takahashi in view of Chen, Chen-2 discloses The semiconductor structure of claim 6, wherein the second AP is spaced apart from the first AP (In FIG. 8a, 10c, Takahashi, each layer of 62 is spaced apart from each layer of 61; Accordingly, as modified, the second AP of the L-shaped section 62 would be spaced apart from the first AP of the seal ring 61).
RE: Claim 8, Takahashi in view of Chen, Chen-2 discloses The semiconductor structure of claim 6, wherein the first AP has a first width, and the second AP has a second width greater than the first width (From Takahashi FIG. 10c, the horizontal width of each L-shaped section 62f is greater than horizontal width of vertical portion of 61; Accordingly, the second AP of the L-shaped section 62f would have a second width greater than a first width of the first AP).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Chen as applied to claim 1, further in view of US20050263855A1 (“Fu”).
RE: Claim 9, Takahashi in view of Chen does not explicitly disclose The semiconductor structure of claim 1, wherein the first area and the second area each include an array of dummy top metal lines.
However, in the same field of endeavor, Fu discloses a dummy metal pattern 140 for chip corner stress relief. The dummy metal pattern 140 may comprise a first corner stress relief (CSR) zone 142 and may further include a second CSR zone 144, [0014].
Fu further discloses dummy metal pattern 140 may comprise a plurality of patterned layers and a plurality of vertical columns coupled between the plurality of patterned layers. The dummy metal pattern 140 may be similar to multilayer interconnects formed in the integrated circuit region 120, [0017].
FIG. 1 shows a first area of the CSR zone 142 is between a registration feature 160 and the seal ring 150, and a second area of the CSR zone 142 between 160 and the bridge portion of 150.
Fu further discloses the registration feature 160 can include an L-shape, [0018].
FIG. 6 shows a registration feature 510 between a first area comprising a first stack of dummy metal layers 186, 182, 184, 180 and a second area comprising a second stack of dummy metal layers 186, 182, 184, 180.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of patterned dummy metal layers in each of the first and second areas as taught by Fu in order to provide corner stress relief.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Chen as applied to claim 1, further in view of US20190131255A1 (“Teng”).
RE: Claim 11, Takahashi in view of Chen discloses The semiconductor structure of claim 1, wherein the AP is a first AP, the seal ring is a first seal ring.
Takahashi in view of Chen does not explicitly disclose:
the semiconductor structure further comprises:
a second seal ring surrounding the first seal ring;
wherein the second seal ring includes a third top metal line and a second AP disposed over and connected to the third top metal line;
wherein the third top metal line is concentric to and spaced apart from the first top metal line; and
wherein the second AP is concentric to and spaced apart from the first AP.
However, in the same field of endeavor, Teng discloses:
a second seal ring (340a) surrounding a first seal ring (330a; 330a, 340a form seal ring 302, [0054]);
wherein the second seal ring includes a third top metal line (second wiring 222 from the top in 340a in FIG. 15) and a second pad (first wiring 222 from the top in 340a in FIG. 15) disposed over and connected to the third top metal line (the first wiring 222 is disposed over and connected to the second wiring 222 by a via 223);
wherein the third top metal line is concentric to and spaced apart from a first top metal line (330a, 340a are arranged concentrically, [0054]; FIG. 15 shows the second wiring 222 from top in 340a is spaced apart from the second wiring 222 from top in 330a); and
wherein the second pad is concentric to and spaced apart from the first AP (330a, 340a are arranged concentrically, [0054]; FIG. 15 shows the first wiring 222 from top in 340a is spaced apart from the first wiring 222 from top in 330a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second seal ring surrounding the first seal ring 61 as taught by Teng in order to provide additional sealing to the circuit region 23 in Takahashi.
Further, Takahashi discloses seal ring 61 includes 81d, 81f, via 81e, [0061]; 81f and wirings 71b, 71d, 71f are formed of a common conductive material, [0061]; 71b, 71d, 71f are formed of an aluminum alloy, [0060].
Accordingly, it would have been obvious to form the second seal ring out of the same aluminum alloy used to form the first seal ring 61 in Takahashi in order to simplify manufacturing. Accordingly, under a broad reasonable interpretation, the second pad (first wiring 222 from the top in FIG. 15 Teng) would be considered a second aluminum pad.
Claim(s) 12-13, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
RE: Claim 12, Chen discloses: A semiconductor structure (100A in FIGs. 1-4), comprising:
a substrate (102, 104, 105, 108 in FIG. 4) having a seal ring region (104, 105, 108) and a circuit region (102);
a first seal ring structure (113 in FIG. 4) disposed in the seal ring region;
a second seal ring structure (110 in FIG. 4) disposed in a corner section of the seal ring region and connecting two edges of the first seal ring structure (113 is a seal ring structure, [0022]; 110 connects sides of the seal ring structure, [0016]; Accordingly, 110 connects two edges of 113);
a third seal ring structure (1141, 1142, 1143, 112, 116) disposed between the first seal ring structure and the second seal ring structure (FIGs. 2, 4 shows the combination 1141, 1142, 1143, 112, 116 is disposed between 104, 113 and 110), the third seal ring structure having an L-shape (FIG. 2 shows the combination 1141, 1142, 1143, 112, 116 having an L-shape); and
wherein a first area (first area between 113 and 1142 in FIG. 4) between the first seal ring structure and the third seal ring structure and a second area (second area between 110 and 1141 in FIG. 4) between the second seal ring structure and the third seal ring structure are free of aluminum pads (APs) (FIG. 4 shows the first and second areas are free of aluminum pads as these areas are occupied by dielectric layers 118A, 118B).
Chen does not explicitly disclose:
the enhanced structure 110 is a second seal ring structure;
the combination of 1141, 1142, 1143, 112, 116 is a third seal ring structure.
However, Chen discloses With the formation of the enhanced structure 110, more metal structures exist at the corner region. The stress applied to the seal ring structure may thus be spread to more metal structures, and hence the seal ring structure is less likely to be damaged by stresses, [0016].
Chen further discloses that 108 is a corner stress relief region, [0014].
FIGs. 2, 4 show the combination of 1141, 1142, 1143, 112, 116 is in the corner stress relief region 108, [0018], [0020], [0026].
Chen further discloses The CSR region 108 may be designed on the chip 100A to prevent cracking of the chip induced by stress from backend processing such as die-sawing, packing, and plastic molding, [0014].
Further, the reference US20080251923A1 (“Wang”) discloses Seal rings are stress protection structures around integrated circuits, protecting the internal circuit inside semiconductor chips from damage caused by the dicing, [0002].
Accordingly, under a broad reasonable interpretation, the enhanced structure 110 is considered a second seal ring structure, and the combination of 1141, 1142, 1143, 112, 116 is considered a third seal ring structure as they are stress protection structures around a circuit region 102.
RE: Claim 13, Chen discloses The semiconductor structure of claim 12, wherein the first seal ring structure is spaced apart from the third seal ring structure (FIGs. 2, 4 shows 113, 104 is spaced apart from the combination 1141, 1142, 1143, 112, 116).
RE: Claim 17, Chen discloses The semiconductor structure of claim 12, wherein the second seal ring structure is connected to the first seal ring structure and the third seal ring structure is not connected to the first seal ring structure (113 is a seal ring structure, [0022]; 110 connects sides of the seal ring structure, [0016]; FIG. 2 shows the combination 1141, 1142, 1143, 112, 116 is spaced apart from 104 and therefore is not directly connected to 113).
Claims 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 12, further in view of Fu.
RE: Claim 14, Chen discloses The semiconductor structure of claim 12, wherein:
the first seal ring structure, the second seal ring structure, and the third seal ring structure include a first stack of metal layers (first stack of metal layers at level M3 and below in 113 in FIG. 4; plurality of stacked metal features and via pillars forms the seal ring structure 113, [0026]), a second stack of metal layers (second stack of metal layers at level M3 and below in 110 FIG. 4; 110 is stacked metal features and via pillars, [0016]), and a third stack of metal layers (third stack of metal layers at level M3 and below in 1141 and/or 1142 in FIG. 4; third portion of the plurality of stacked metal features 114B and via pillars forms various probe pad structures 1141 and 1142, [0026]), respectively;
the first seal ring structure includes an AP layer (upper metal layer at MT in 113; metallization layers and via layers include aluminum, [0027]; Accordingly, under a broad reasonable interpretation, the upper metal layer at MT in 113 is an aluminum pad) over the first stack of metal layers.
Chen does not explicitly disclose:
the first area and the second area include a first stack of dummy metal layers and a second stack of dummy metal layers, respectively.
However, in the same field of endeavor, Fu discloses a dummy metal pattern 140 for chip corner stress relief. The dummy metal pattern 140 may comprise a first corner stress relief (CSR) zone 142 and may further include a second CSR zone 144, [0014].
Fu further discloses dummy metal pattern 140 may comprise a plurality of patterned layers and a plurality of vertical columns coupled between the plurality of patterned layers. The dummy metal pattern 140 may be similar to multilayer interconnects formed in the integrated circuit region 120, [0017].
FIG. 1 shows a first area of the CSR zone 142 is between a registration feature 160 and the seal ring 150, and a second area of the CSR zone 142 between 160 and the bridge portion of 150.
Fu further discloses the registration feature 160 can include an L-shape, [0018].
FIG. 6 shows a registration feature 510 between a first area comprising a first stack of dummy metal layers 186, 182, 184, 180 and a second area comprising a second stack of dummy metal layers 186, 182, 184, 180.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a respective stack of dummy metal layers in each of the first and second areas as taught by Fu in order to provide corner stress relief.
RE: Claim 15, Chen in view of Fu discloses The semiconductor structure of claim 14, wherein the AP layer is a first AP layer, the second seal ring structure includes a second AP layer (upper metal layer at level MT in 110 in FIG. 4) over the second stack of metal layers, and the third seal ring structure includes a third AP layer (upper metal layer at level MT in 1141 or 1142 in FIG. 4; metallization layers and via layers include aluminum, [0027]; Accordingly, under a broad reasonable interpretation, the upper metal layers at MT in 110 and 1141, 1142 are aluminum pads) over the third stack of metal layers.
Claim 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 12, further in view of Teng.
RE: Claim 18, Chen does not explicitly disclose The semiconductor structure of claim 12, further comprising a fourth seal ring structure surrounding the first seal ring structure from a top view.
However, in the same field of endeavor, Teng discloses in FIG. 16:
a fourth seal ring structure (340a, [0054]) surrounding a first seal ring structure (330a) from a top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second seal ring surrounding the first seal ring structure 113 as taught by Teng in order to provide additional sealing to the circuit region 102 in Chen.
Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Fu.
RE: Claim 19, Chen discloses A semiconductor structure (100A in FIGs. 1-4), comprising:
a substrate (102, 104, 105, 108 in FIG. 4) having a seal ring region (104, 105, 108) and a circuit region (102);
a first seal ring structure (113, 104 in FIG. 4) disposed in the seal ring region and surrounding the circuit region (113 surrounds circuit region 102, [0022]), wherein a portion of the first seal ring structure having a first L-shape forms a corner in a corner section of the seal ring region (FIG. 2 shows portion of 104 has first L-shape forming a corner in corner section of 104; As 113 surrounds 102 and 113 is in 104, [0022], a portion of 113 forms a first L-shape forming a corner in corner section of the seal ring region; corner section is region including 110, 114, 112, 116 and corner of 104, 113);
a second seal ring structure (1141, 1142, 1143, 112, 116) disposed inside the corner section of the seal ring region, wherein the second seal ring structure has a second L-shape opposing the first L-shape (FIG. 2 shows the combination 1141, 1142, 1143, 112, 116 having a second L-shape opposing the first L-shape);
wherein the first seal ring structure includes a first stack of metal layers (first stack of metal layers at level M3 and below in 113 in FIG. 4; plurality of stacked metal features and via pillars forms the seal ring structure 113, [0026]) and an aluminum pad (AP) layer (upper metal layer at MT in 113; metallization layers and via layers include aluminum, [0027]; Accordingly, under a broad reasonable interpretation, the upper metal layer at MT in 113 is an aluminum pad layer) over the first stack of metal layers;
wherein the second seal ring structure includes a second stack of metal layers (second stack of metal layers at level M3 and below in 1141 and/or 1142 in FIG. 4; portion of the plurality of stacked metal features 114B and via pillars forms various probe pad structures 1141 and 1142, [0026]); and wherein an area between the first seal ring structure and the second seal ring structure is free of an AP layer (FIG. 4 shows the area between 113 and 1142 is free of aluminum pads as this area is occupied by dielectric layers 118A, 118B).
Chen does not explicitly disclose:
wherein the area between the first seal ring structure and the second seal ring structure includes a stack of dummy metal layers.
However, in the same field of endeavor, Fu discloses a dummy metal pattern 140 for chip corner stress relief. The dummy metal pattern 140 may comprise a first corner stress relief (CSR) zone 142 and may further include a second CSR zone 144, [0014].
Fu further discloses dummy metal pattern 140 may comprise a plurality of patterned layers and a plurality of vertical columns coupled between the plurality of patterned layers. The dummy metal pattern 140 may be similar to multilayer interconnects formed in the integrated circuit region 120, [0017].
FIG. 1 shows a first area of the CSR zone 142 is between a registration feature 160 and the seal ring 150, and a second area of the CSR zone 142 between 160 and the bridge portion of 150.
Fu further discloses the registration feature 160 can include an L-shape, [0018].
FIG. 6 shows a registration feature 510 between a first area comprising a first stack of dummy metal layers 186, 182, 184, 180 and a second area comprising a second stack of dummy metal layers 186, 182, 184, 180.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a stack of dummy metal layers in the area between 113 and 1142 as taught by Fu in order to provide corner stress relief.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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