Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restriction - Response to Amendment
1. Applicant’s election without traverse of Group II, claims 16-20. Applicant's amendment dated 11/04/2025 in which claims 1-15 were canceled has been entered of record. Because applicant's amendment has canceled claims drawn to a distinct invention, the restriction requirement (dated 10/07/2025) is now moot. New claims 21-35 were added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 16-22 and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Yates et al. (US 2007/0048955; hereinafter Yates) in view of Cho et al. (US 2015/0091133; hereinafter Cho).
Regarding claim 16, Yates, in fig. 2H, discloses a method of making a semiconductor device, the method comprising: forming a transistor (not labeled) on a substrate 12’ (fig. 2A); forming a dielectric layer 22’ on the transistor (fig. 2A); forming a trench 26’ in the dielectric layer 22’ (fig. 2A); and forming a bottom capacitor plate 42’of a capacitor in the trench such the bottom capacitor plate 42’ has a rough upper surface and is connected to a source region 20’of the transistor.
Yates discloses a method of making a capacitor as above but fails to disclose forming the bottom capacitor plate by plasma enhanced atomic layer deposition (PEALD).
However, Cho discloses a method of making a capacitor comprising: forming a bottom capacitor plate 200 of a capacitor in the trench by plasma enhanced atomic layer deposition (PEALD) (fig. 6 & [0055]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a bottom capacitor plate as taught by Cho, since the PEALD has the advantage that the bottom capacitor plate having a uniform thickness can be deposited on walls and bottom surfaces of a gap structure. Moreover, the PEALD method enables the bottom capacitor plate to be formed at low temperature, resulting in reducing a thermal budget to underlayers formed on the substrate.
Regarding claim 17, Cho discloses wherein the forming of the bottom capacitor plate 200 comprises depositing a TiN layer 200 in the trench (fig. 6 & [0054]). Yates discloses the bottom capacitor plate 42’of a capacitor has a rough upper surface (fig. 2H). Although the root mean square (RMS) surface roughness is not exactly as claimed (at least 1.14), this claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller,105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 18, Yates discloses further comprising: forming a capacitor dielectric layer 48’on the rough upper surface of the bottom capacitor plate 42’ (fig. 2H).
Regarding claim 19, Yates discloses wherein the forming of the bottom capacitor plate 42’ comprises forming the rough upper surface to have a recessed portion, and the forming of the capacitor dielectric layer 48’ comprises forming the capacitor dielectric layer 48’ in the recessed portion of the rough upper surface (fig. 2H).
Regarding claim 20, Yates discloses further comprising: forming an upper capacitor plate 50’ on the capacitor dielectric layer 48’ and in the recessed portion of the rough upper surface (fig. 2H).
Regarding claim 21, Yates, in fig. 2H, discloses a method of forming a capacitor, comprising: forming a trench 26 in a dielectric layer 22’ on a substrate 12’; depositing a conductive material 42’in the trench 26 to form a bottom capacitor plate 42’ having a rough upper surface; forming a capacitor dielectric layer 48’on the rough upper surface of the bottom capacitor plate 48’; and forming an upper capacitor plate 50’ on the capacitor dielectric layer 48’.
Yates discloses a method of making a capacitor as above but fails to disclose forming the bottom capacitor plate by plasma enhanced atomic layer deposition (PEALD).
However, Cho discloses a method of making a capacitor comprising: forming a bottom capacitor plate 200 of a capacitor in the trench by plasma enhanced atomic layer deposition (PEALD) (fig. 6 & [0054]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a bottom capacitor plate as taught by Cho, since the PEALD has the advantage that the bottom capacitor plate having a uniform thickness can be deposited on walls and bottom surfaces of a gap structure. Moreover, the PEALD method enables the bottom capacitor plate to be formed at low temperature, resulting in reducing a thermal budget to underlayers formed on the substrate.
The combination of Yates and Cho fails to disclose the rough upper surface has a root mean square (RMS) surface roughness of at least 1.14. Although the root mean square (RMS) surface roughness is not exactly as claimed (at least 1.14), this claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller,105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 22, Cho discloses wherein the depositing of the conductive material comprises depositing a TiN layer 200 (fig. 6 & [0054]).
Regarding claim 29, Yates discloses wherein the rough upper surface comprises a recessed portion (fig. 2H).
Regarding claim 30, Yates discloses wherein a depth of the recessed portion is greater than a thickness of the capacitor dielectric layer 48’ (fig. 2H).
3. Claims 23-28 are rejected under 35 U.S.C. 103 as being unpatentable over Yates (US 2007/0048955) in view of Cho (US 2015/0091133); and further in view of Okura (US 9,540,729; hereinafter Okura).
Regarding claim 23, the combination of Yates and Cho discloses a method of making a capacitor as above but fails to disclose the PEALD cycles.
However, Okura discloses wherein the depositing of the TiN layer comprises: exposing the substrate to a titanium precursor (col. 17, lines 17-31 & col. 18, lines 6-12); purging the titanium precursor (col. 18, lines 18-21); and exposing the substrate to a plasma comprising NH3 and Ar (col. 18, lines 14-17 & col. 18, line 54 through col. 19, line 4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a TiN layer as taught by Okura in order to improve the growth rate of the TiN layer.
Regarding claim 24, Okura discloses wherein the titanium precursor comprises tetrakis (dimethylamido) titanium (TDMAT) (col. 17, lines 17-31).
Regarding claim 25, Okura discloses wherein the exposing the substrate to the plasma comprises exposing to a plasma having a power of about 300 W (col. 19, lines 43-52).
Regarding claim 26, Okura discloses wherein the depositing of the TiN layer is performed at a temperature of 250°C or less (col. 19, lines 55-57).
Regarding claim 27, Okura discloses further comprising: performing a post-deposition hydrogen plasma treatment on the TiN layer to reduce resistivity of the TiN layer (col. 18, lines 66-67).
Regarding claim 28, Okura discloses wherein the post-deposition hydrogen plasma treatment comprises exposing the TiN layer to hydrogen plasma balanced in argon at a temperature of 250°C or less (col. 19, lines 55-57).
Allowable Subject Matter
4. Claims 31-36 are allowed.
5. The following is an examiner's statement of reason for allowance: the prior art of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of "depositing a conductive material in the trench by plasma enhanced atomic layer deposition (PEALD) at a temperature of 250°C or less to form a bottom capacitor plate, wherein the depositing forms a rough upper surface on the bottom capacitor plate having a root mean square (RMS) surface roughness of at least 1.14; conformally depositing a dielectric material on the rough upper surface to form a capacitor dielectric layer; and depositing a conductive material on the capacitor dielectric layer to form an upper capacitor plate” (claim 31) as instantly claimed and in combination with the additionally claimed method steps.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance".
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818